KR20080105734A - Copper wiring formation method of semiconductor device - Google Patents
Copper wiring formation method of semiconductor device Download PDFInfo
- Publication number
- KR20080105734A KR20080105734A KR1020070053710A KR20070053710A KR20080105734A KR 20080105734 A KR20080105734 A KR 20080105734A KR 1020070053710 A KR1020070053710 A KR 1020070053710A KR 20070053710 A KR20070053710 A KR 20070053710A KR 20080105734 A KR20080105734 A KR 20080105734A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- inter
- film
- forming
- copper wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 239000010949 copper Substances 0.000 title claims abstract description 44
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 230000004888 barrier function Effects 0.000 claims abstract description 42
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000007943 implant Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 61
- 239000010410 layer Substances 0.000 description 20
- 239000011148 porous material Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 구리배선 형성 방법에 관한 것이다. The present invention relates to a method for forming copper wiring of a semiconductor device.
본 발명은, 기판상에 배선간절연막을 형성하는 제1단계와, 상기 배선간절연막내에 비아홀 및 트렌치를 형성하는 제2단계와, 상기 비아홀 및 상기 트렌치 내벽을 포함하는 상기 배선간절연막 표면에 대해 특정 원소의 임플란트를 실시하여 확산방지층을 형성하는 제3단계와, 상기 확산방지층상에 배리어막을 형성하는 제4단계와, 상기 비아홀 및 상기 트렌치내에 구리배선막을 매립하여 형성하는 제5단계와, 상기 배선간절연막 상부의 상기 구리배선막, 상기 배리어막 및 상기 확산방지층을 제거하는 제6단계를 포함한다. The present invention relates to a first step of forming an inter-wire insulating film on a substrate, a second step of forming a via hole and a trench in the inter-wire insulating film, and a surface of the inter-wire insulating film including the via hole and the inner wall of the trench. A third step of forming a diffusion barrier layer by implanting a specific element, a fourth step of forming a barrier layer on the diffusion barrier layer, and a fifth step of embedding a copper wiring layer in the via hole and the trench; And removing the copper wiring film, the barrier film, and the diffusion barrier layer on the inter-wire insulating film.
따라서, 배리어막의 원소가 배선간절연막내로 확산되어 유전상수를 증가시키는 것을 방지할 수 있게 되므로, 신호 지연 문제를 방지하여 제조되는 반도체 소자의 신뢰성을 향상시킬 수 있는 효과가 있다. Therefore, since the element of the barrier film can be prevented from being diffused into the inter-wire insulating film to increase the dielectric constant, it is possible to prevent the signal delay problem and to improve the reliability of the manufactured semiconductor device.
Description
도 1a 내지 도 1g는 종래의 반도체 소자의 구리배선 형성 방법을 순차적으로 보여주는 공정 단면도, 1A through 1G are cross-sectional views sequentially illustrating a method of forming a copper wiring of a conventional semiconductor device;
도 2a 내지 도 2h는 본 발명에 따른 반도체 소자의 구리배선 형성 방법을 순차적으로 보여주는 공정 단면도이다. 2A through 2H are cross-sectional views sequentially illustrating a method of forming copper wirings of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 기판 10a : 층간절연막10
20 : 배선간절연막 20a : 비아홀20: interwire
20b : 트렌치 22 : 확산방지층20b: trench 22: diffusion barrier layer
30 : 배리어막 40 : 구리배선막30
본 발명은 반도체 소자의 구리배선 형성 방법에 관한 것으로서, 더욱 상세하게는 다공성 물질로 이루어지는 배선간절연막의 표면에 대해 임플란트를 실시하여 확산방지층을 형성함으로써 추후의 고온 공정시에 인접된 박막으로부터 원소가 확 산되는 것을 차단하여 해당 배선간절연막의 유전상수 값이 증가되는 것을 방지할 수 있는 반도체 소자의 구리배선 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly, to form a diffusion barrier layer by implanting a surface of an inter-wire insulating film made of a porous material, thereby forming elements from adjacent thin films at a later high temperature process. The present invention relates to a method for forming a copper wiring of a semiconductor device which can prevent diffusion and prevent an increase in the dielectric constant value of the inter-wire insulating film.
일반적으로, 최근 들어 반도체 소자의 고성능화가 요구되면서 기존의 알루미늄(Al) 보다 전도성이 우수한 구리(Cu)를 이용하여 금속배선을 형성하고 있으며, 구리배선의 경우에는 식각(etching) 공정을 이용한 패터닝(patterning)이 용이하지 않기 때문에 통상적인 섭트랙티브(subtractive) 패터닝 방식을 대신하여 다마신(damascene) 공정을 이용하여 패터닝하게 된다. In general, in recent years, as the performance of semiconductor devices is required, metal wires are formed using copper (Cu), which is more conductive than conventional aluminum (Al). In the case of copper wires, patterning using an etching process is performed. Since patterning is not easy, patterning is performed using a damascene process instead of a conventional subtractive patterning method.
도 1a 내지 도 1h는 종래의 구리배선 형성 방법을 순차적으로 보여주는 공정 단면도이다. 1A to 1H are cross-sectional views sequentially illustrating a method of forming a conventional copper wiring.
먼저, 도 1a와 같이, 하부배선(미도시) 및 층간절연막(10a)을 포함하는 기판(10)상에 구리배선 형성을 위한 배선간절연막(20)을 증착(deposition)하여 형성한다. First, as shown in FIG. 1A, an interwire
그 후, 도 1b와 같이, 사진 식각 공정을 통해 해당 배선간절연막(20)의 일부를 관통되도록 제거하여 비아홀(via hole)(20a)을 형성하며, 또한 또 한 차례의 사진 식각 공정을 통해 도 1c와 같이 비아홀(20a)의 상부 일부를 제거하여 트렌치(trench)(20b)를 형성한다. Thereafter, as illustrated in FIG. 1B, a portion of the
물론, 비아홀(20a) 형성시에 기판(10)상의 층간절연막(10a) 부분까지 제거하여 형성하게 된다. Of course, even when the
그 다음, 도 1d와 같이, 비아홀(20a) 및 트렌치(20b) 내벽을 포함하는 배선간절연막(20)의 전면에 대해 배리어(barrier)막(30)을 증착하여 형성하며, 해당 배 리어막(30)은 이후 구리배선막(40) 형성시에 구리 원소의 확산을 막는 역할을 하게 되고, 통상 탄탈 나이트라이드(TaN) 또는 탄탈늄(Ta)을 이용하여 형성하게 된다. Next, as shown in FIG. 1D, a
이어서, 도 1e와 같이, 배리어막(30)상의 비아홀(20a) 및 트렌치(20b) 내부에 대해 전기화학도금법(Electro Chemical Plating : ECP)을 이용하여 구리막을 매립함으로써 구리배선막(40)을 형성한다. Subsequently, as shown in FIG. 1E, the
이때, 구리막 매립 전에 먼저 증착법 또는 전기화학도금법을 이용하여 배리어막(30)상에 다소 얇은 구리시드(seed)층(미도시)을 형성하여 이후 구리배선막(40)이 원활히 형성되도록 할 수 있다. At this time, before the copper film is embedded, a rather thin copper seed layer (not shown) may be formed on the
그 다음, 도 1f와 같이, 배선간절연막(20) 상부에 존재하는 구리배선막(40) 및 배리어막(30)을 CMP(Chemical Mechanical polishing) 공정을 통해 제거하여 평탄화한다. Next, as shown in FIG. 1F, the
그 후, 도 1g와 같이, 구리배선막(40)내의 스트레스(stress)를 완화하기 위해 어닐링 열처리(annealing heat treatment)를 실시한다. Thereafter, as shown in FIG. 1G, annealing heat treatment is performed to relieve stress in the
이로써, 최종적인 구리배선막(40)을 통해 구리배선이 완성되게 된다. As a result, the copper wiring is completed through the final
한편, 최근 들어 반도체 소자의 고기능화 및 고집적화의 진행에 따라 디자인룰(design rule)이 작아지면서 금속배선, 즉 구리배선간의 거리도 좁아지고 있으며, 따라서 금속배선간을 절연하는 배선간절연막(20)으로 기존에 사용되던 실리콘 옥사이드(SiO2)로는 신호 지연 문제가 발생되게 된다. On the other hand, in recent years, as the semiconductor device becomes more functional and highly integrated, as design rules become smaller, the distance between metal wires, that is, copper wires, is also narrowing. Conventional silicon oxide (SiO 2 ) causes signal delay problems.
따라서, 이러한 신호 지연 문제를 해결하기 위해 배선간절연막(20)으로 다공 성(porous) 물질이어서 낮은 유전상수 값(k)을 갖는 카본 도핑 실리콘 옥사이드(carbon-doped SiO2)로 대체하여 이용하고 있다. Therefore, in order to solve such a signal delay problem, the
그러나, 카본 도핑 실리콘 옥사이드는 결정조직 내부에 기공이 다량 존재하는 다공성 물질이므로, 구리배선막(40) 형성 후에 진행하는 어닐링 고온 공정시에 배리어막(30)인 탄탈 나이트라이드(TaN) 또는 탄탈늄(Ta)내의 원소들이 해당 배선간절연막(20)내로 확산되어 기공을 채우게 됨으로써 배선간절연막(20)의 유전상수 값을 증가시켜, 신호 지연 문제를 발생시키고, 제조되는 반도체 소자의 신뢰성을 저하시키는 문제점이 있었다. However, since the carbon doped silicon oxide is a porous material in which a large amount of pores exist in the crystal structure, tantalum nitride (TaN) or tantalum, which is the
본 발명은 상기와 같은 제반 문제점을 해결하기 위하여 창안된 것으로서, 배리어막의 형성 전에 배선간절연막 표면에 대해 임플란트(implant)를 실시하여 표면측에 확산방지층을 형성함으로써 이후 고온 공정시에 배리어막내의 원소가 배선간절연막으로 확산되어 유전상수 값을 증가시키는 것을 방지할 수 있는 반도체 소자의 구리배선 형성 방법을 제공하는데 그 목적이 있다. The present invention has been devised to solve the above problems. An implant is formed on the surface of an inter-wiring insulating film before the barrier film is formed to form a diffusion barrier layer on the surface side, so that the element in the barrier film at a later high temperature process is formed. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a copper wiring of a semiconductor device capable of preventing the diffusion of a dielectric into the inter-wire insulating film and increasing the dielectric constant value.
본 발명의 상기 목적과 여러가지 장점은 이 기술분야에 숙련된 사람들에 의해 첨부된 도면을 참조하여 아래에 기술되는 발명의 바람직한 실시예로부터 더욱 명확하게 될 것이다.The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.
상술한 목적을 달성하기 위한 본 발명의 반도체 소자의 구리배선 형성 방법 은, 기판상에 배선간절연막을 형성하는 제1단계와, 상기 배선간절연막내에 비아홀 및 트렌치를 형성하는 제2단계와, 상기 비아홀 및 상기 트렌치 내벽을 포함하는 상기 배선간절연막 표면에 대해 특정 원소의 임플란트를 실시하여 확산방지층을 형성하는 제3단계와, 상기 확산방지층상에 배리어막을 형성하는 제4단계와, 상기 비아홀 및 상기 트렌치내에 구리배선막을 매립하여 형성하는 제5단계와, 상기 배선간절연막 상부의 상기 구리배선막, 상기 배리어막 및 상기 확산방지층을 제거하는 제6단계를 포함한다. A method for forming a copper wiring of a semiconductor device of the present invention for achieving the above object includes a first step of forming an inter-wire insulating film on a substrate, a second step of forming a via hole and a trench in the inter-wire insulating film, and A third step of forming a diffusion barrier layer by implanting a specific element on the surface of the inter-wire insulating layer including the via hole and the inner wall of the trench, and a fourth step of forming a barrier layer on the diffusion barrier layer, the via hole and the And a fifth step of embedding a copper wiring film in the trench, and a sixth step of removing the copper wiring film, the barrier film, and the diffusion barrier layer on the inter-wire insulating film.
이하, 첨부된 도면을 참조로 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명에 따른 반도체 소자의 구리배선 형성 방법을 순차적으로 보여주는 공정 단면도이다. 2A through 2H are cross-sectional views sequentially illustrating a method of forming copper wirings of a semiconductor device according to the present invention.
먼저, 도 2a와 같이, 하부배선(미도시) 및 층간절연막(10a)을 포함하는 기판(10)상에 배선간절연막(20)을 형성하며, 해당 배선간절연막(20)으로는 다공성으로 저유전상수(low-k) 물질인 카본 도핑 실리콘 옥사이드(carbon-doped SiO2)가 이용되게 된다. First, as shown in FIG. 2A, an interwire
그 후, 도 2b와 같이, 해당 배선간절연막(20)을 관통하도록 비아홀(20a)을 형성하고, 또한 도 2c와 같이 해당 비아홀(20a)의 상부 일부를 제거하여 트렌치(20b)를 형성한다. Thereafter, as shown in FIG. 2B, the
다음으로, 도 2d와 같이, 비아홀(20a) 및 트렌치(20b) 내벽을 포함하는 배선 간절연막(20)의 표면에 대해 임플란트(implant) 공정을 실시하여 특정 원소를 도핑시킴으로써 표면측에 확산방지층(22)을 형성하며, 해당 확산방지층(22)은 추후의 어닐링 열처리시에 배리어막(30)의 원소가 배선간절연막(20)측으로 확산되는 것을 차단하게 된다. Next, as shown in FIG. 2D, an implant process is performed on the surface of the inter-wire
즉, 특정 원소가 이온 주입되어 배선간절연막(20) 표면측 내부의 기공들에 삽입되어 치밀한 결정구조를 형성하는 것에 의해 확산방지층(22)을 형성하게 되며, 이때 도핑되는 도펀트(dopant)로는 질소(N) 원소를 이용할 수 있고, 확산방지층(22)은 약 500Å 정도의 두께를 갖도록 형성할 수 있으며, 임플란트 공정조건은 이온주입에너지 20~300keV, 이온주입량(즉, 도즈(doze)량) 3E13~3E14atoms/㎠로 실시할 수 있다. That is, a specific element is ion-implanted to insert into the pores inside the surface side of the inter-wire
그 다음, 도 2e와 같이, 확산방지층(22)상의 전면에 대해 배리어막(30)을 형성하며, 해당 배리어막(30)은 이후의 구리배선막(40) 형성시에 구리 원소의 확산을 막는 역할을 하며, 통상 탄탈 나이트라이드(TaN) 또는 탄탈늄(Ta)으로 형성되게 된다. Next, as shown in FIG. 2E, a
그 후, 도 2f와 같이, 비아홀(20a) 및 트렌치(20b) 내부에 전기화학도금법을 이용하여 구리막을 매립함으로써 구리배선막(40)을 형성한다. Thereafter, as shown in FIG. 2F, the
다음으로, 도 2g와 같이, 배선간절연막(20) 상부에 존재하는 구리배선막(40), 배리어막(30) 및 확산방지층(22)을 CMP 공정을 통해 제거하여 평탄화한다. Next, as shown in FIG. 2G, the
그 다음, 도 2h와 같이, 구리배선막(40)내의 스트레스를 완화하기 위해 어닐링 열처리를 실시한다. Next, as shown in FIG. 2H, annealing heat treatment is performed to relieve stress in the
이로써, 최종적인 구리배선막(40)을 통해 구리배선이 완성되게 된다. As a result, the copper wiring is completed through the final
이상과 같은 본 발명에 의하면, 배리어막(30)의 형성 전에 배선간절연막(20)의 표면에 대해 임플란트 공정을 실시하여 확산방지층(22)을 형성함으로써 추후의 어닐링 열처리시에 배리어막(30)내의 원소가 배선간절연막(20)내로 확산되어 배선간절연막(20)의 유전상수 값을 증가시켜 신호 지연 문제를 발생시키고 제조되는 반도체 소자의 신뢰성을 저하시키는 것을 방지할 수 있게 된다. According to the present invention as described above, the
이상, 상기 내용은 본 발명의 바람직한 일 실시예를 단지 예시한 것으로 본 발명의 당업자는 본 발명의 요지를 변경시킴이 없이 본 발명에 대한 수정과 변경을 가할 수 있음을 인지해야 한다.In the foregoing description, it should be understood that those skilled in the art can make modifications and changes to the present invention without changing the gist of the present invention as merely illustrative of a preferred embodiment of the present invention.
본 발명에 따르면, 배리어막의 원소가 배선간절연막내로 확산되어 유전상수를 증가시키는 것을 방지할 수 있게 되므로, 신호 지연 문제를 방지하여 제조되는 반도체 소자의 신뢰성을 향상시킬 수 있는 효과가 달성될 수 있다. According to the present invention, since the elements of the barrier film can be prevented from being diffused into the inter-wire insulating film to increase the dielectric constant, the effect of preventing the signal delay problem and improving the reliability of the manufactured semiconductor device can be achieved. .
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070053710A KR20080105734A (en) | 2007-06-01 | 2007-06-01 | Copper wiring formation method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070053710A KR20080105734A (en) | 2007-06-01 | 2007-06-01 | Copper wiring formation method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20080105734A true KR20080105734A (en) | 2008-12-04 |
Family
ID=40366974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020070053710A Ceased KR20080105734A (en) | 2007-06-01 | 2007-06-01 | Copper wiring formation method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20080105734A (en) |
-
2007
- 2007-06-01 KR KR1020070053710A patent/KR20080105734A/en not_active Ceased
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8138082B2 (en) | Method for forming metal interconnects in a dielectric material | |
| US7868455B2 (en) | Solving via-misalignment issues in interconnect structures having air-gaps | |
| JP5493096B2 (en) | Manufacturing method of semiconductor device | |
| KR101389191B1 (en) | Semiconductor device and manufacturing method of the same | |
| WO2008028850A1 (en) | CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES | |
| US20030160332A1 (en) | Semiconductor devices and methods of manufacturing such semiconductor devices | |
| US20090115019A1 (en) | Semiconductor device having air gap and method for manufacturing the same | |
| US7585768B2 (en) | Combined copper plating method to improve gap fill | |
| KR100546209B1 (en) | Copper wiring formation method of semiconductor device | |
| KR100939773B1 (en) | Metal wiring of semiconductor device and forming method thereof | |
| US6833321B2 (en) | Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability | |
| CN100533725C (en) | Method for forming metal interconnection of semiconductor device | |
| US20040038526A1 (en) | Thermal process for reducing copper via distortion and crack | |
| US20080160753A1 (en) | Method of forming metal wire in semiconductor device | |
| JP5310721B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR100845715B1 (en) | Metal wiring structure of semiconductor device and method of forming the same | |
| KR20080105734A (en) | Copper wiring formation method of semiconductor device | |
| JP2009027048A (en) | Manufacturing method of semiconductor device | |
| KR20100036008A (en) | Method for forming metal wiring of semiconductor device | |
| JP2011142169A (en) | Semiconductor device and manufacturing method thereof | |
| KR100859952B1 (en) | Manufacturing Method of Semiconductor Device | |
| JP2006319116A (en) | Semiconductor device and its manufacturing method | |
| KR20080001905A (en) | Metal wiring formation method of semiconductor device | |
| KR100580775B1 (en) | Method of forming interlayer insulating film of semiconductor device | |
| KR100854877B1 (en) | Metal wiring formation method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20070601 |
|
| PA0201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20080414 Patent event code: PE09021S01D |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20081013 Patent event code: PE09021S01D |
|
| PG1501 | Laying open of application | ||
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20090409 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20081013 Comment text: Notification of reason for refusal Patent event code: PE06011S01I Patent event date: 20080414 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |