KR20080081401A - Gate Forming Method of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method for forming a gate of a semiconductor device, comprising the steps of: providing a semiconductor substrate including a cell region and a peripheral circuit region, a device isolation film formed in a field region, and a tunnel insulating film and a first conductive film formed in an active region; Forming a dielectric layer and a second conductive layer on the semiconductor substrate including the first conductive layer and the isolation layer; patterning the second conductive layer, the dielectric layer, and the first conductive layer to form word lines and select lines; And patterning the second conductive layer included in the select line formed at the outermost portion of the cell region to overlap the edge of the device isolation layer formed at the boundary between the cell region and the peripheral circuit region.

Description

Method of forming a gate in semiconductor device

1A to 1D are cross-sectional views illustrating a method of forming a gate of a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel insulating film

104: first conductive film 106: device isolation film

108: dielectric film 110: second conductive film

112: photoresist pattern 114: dummy gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate of a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device to prevent damage to an active region during an etching process for forming a dummy gate.

Semiconductor memory devices that store data may be classified into volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data if their power supply is interrupted, while nonvolatile memory devices retain their stored data even if their power supply is interrupted.

Nonvolatile memory devices include flash memory devices. The unit cell of the flash memory device includes an active region defined on a predetermined region of a semiconductor substrate, a tunnel insulating layer formed on the active region, a floating gate formed on the tunnel insulating layer, a gate interlayer insulating layer formed on the floating gate, and a gate interlayer insulating layer. A structure including a control gate electrode formed on is widely adopted. In particular, flash memory is widely used in MP3 players, digital cameras, bios storage memory of computers, mobile phones, portable data storage devices, and the like.

The flash memory device includes a cell region in which a cell is formed and a peripheral circuit region in which a circuit for operating the cell is configured. A plurality of cells are formed in the cell region, which are formed on the active region, and the cells and the cells are separated by the device isolation layer.

A manufacturing method of a general flash memory device is as follows.

An active region and a field region are defined by an element isolation film formed in a predetermined region of the semiconductor substrate, and the element is separated from the element. In addition, the same active as that formed in the cell region is formed in the boundary region between the cell region and the peripheral circuit region, which is called a dummy active region. A floating gate pattern is formed in the active region, and a control gate is defined in a direction crossing the active region and the field region.

However, in case of a wide line such as a source select line (SSL) or a drain select line (DSL) formed at the edge of the cell array during the etching process to form a word line, the etching is excessive. Faster and excessively etched into the active area. This becomes more vulnerable because the improved self-aligned Shallow Trench Isolation (STI) structure or the Self Align Floating Gate structure has an etching process using a mask that only opens the cell region.

The present invention proposes a method for preventing excessive loss of an active region during an etching process for forming a dummy active region in a boundary region between a cell region and a peripheral circuit region.

A method of forming a gate of a semiconductor device according to an embodiment of the present invention includes a semiconductor substrate including a cell region and a peripheral circuit region, an isolation layer formed in a field region, and a tunnel insulating layer and a first conductive layer formed in an active region. . A dielectric film and a second conductive film are formed over the semiconductor substrate including the first conductive film and the device isolation film. The second conductive film, the dielectric film, and the first conductive film are patterned to form word lines and select lines, and a second conductive film included in the select line formed at the outermost part of the cell region is formed at the boundary between the cell region and the peripheral circuit region. Patterning is performed so as to overlap the edge of the device isolation layer.

In the above, the second conductive film is left to overlap the edge of the device isolation layer 30nm to 1000nm. In the word line and select line forming process, a dummy gate line is formed in the outermost region of the cell region. The dummy gate line is floating. The dummy gate line is connected to a well pickup.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a method of forming a gate of a semiconductor device according to an embodiment of the present invention, and form dummy active regions in a boundary region between a cell region and a peripheral circuit region.

Referring to FIG. 1A, a tunnel insulating film 102, a floating conductive first conductive film 104, and a hard mask film (not shown) are sequentially formed on the semiconductor substrate 100. In this case, the tunnel insulating film 102 is formed of an oxide, the first conductive film 104 is formed of a polysilicon film, and the hard mask film is formed of a nitride film.

Next, the hard mask layer, the first conductive layer 104, the tunnel insulation layer 102, and the semiconductor substrate 100 are etched through an etching process to form a trench, and then the upper portion of the semiconductor substrate 100 including the trench to fill the trench. An insulating film is formed in the film. In this case, the insulating film is formed of a high density plasma (HDP) oxide film. A chemical mechanical polishing (CMP) process is performed until the upper portion of the hard mask layer is exposed to form the device isolation layer 106. By forming the device isolation film 106, an active region and a field region are defined. The device isolation layer 106 is also formed at the boundary between the active region and the peripheral circuit region.

Then, the effective field height (EFH) of the device isolation layer 106 is adjusted by an etching process using a mask that removes the hard mask layer and then opens only the cell region.

Referring to FIG. 1B, a dielectric layer 108 and a second conductive layer 110 for a control gate are formed on the semiconductor substrate 100 including the first conductive layer 104 and the device isolation layer 106. In this case, the second conductive layer 110 is formed in a structure in which a polysilicon layer and a tungsten silicide layer WSix are stacked.

Referring to FIG. 1C, a photoresist pattern 112 is formed on the second conductive layer 110 to perform an etching process for forming a gate. In this case, the photoresist pattern 112 is used to define a word line or a select line. The photoresist pattern 112 is formed to overlap the edge of the active region of the device isolation layer 106 formed between the active region and the peripheral circuit region. That is, the photoresist pattern 112 is formed on the second conductive layer 110 in the edge region of the device isolation layer 106 as well as the region where the select line is formed at the outermost of the cell array. Here, the photoresist pattern 112 is formed to overlap 30nm to 1000nm in the device isolation region.

Referring to FIG. 1D, the second conductive layer 110, the dielectric layer 108, the first conductive layer 104, and the tunnel insulating layer 102 are etched using the photoresist pattern 112 as an etching mask. ), A plurality of word lines and select lines (not shown) including the first conductive film 104, the dielectric film 108, and the second conductive film 110 are formed. In this case, the dummy gate line 114 is formed in the outermost region of the cell array, and the second conductive layer 110 and the dielectric layer 108 of the dummy gate line 114 are device isolation layers formed in the active region and the peripheral circuit region. It remains up to the top of the edge of 106. Since the second conductive layer 110 and the dielectric layer 108 remain, between the dummy gate line 114 and the device isolation layer 106 formed at the outermost side of the cell array during the etching process for forming the word line and the select line. The semiconductor substrate 100 is not exposed. Therefore, damage to the active region can be prevented. Although not shown in the drawings, the dummy gate line 114 may be connected to a well pickup to be in a ground state or a floating state. The photoresist pattern 112 is removed.

As described above, during the etching process for forming the dummy gate 114 in the boundary region between the cell region and the peripheral circuit region, the photoresist pattern 112 is not formed only on the active region but partially overlapped with the field region. By performing the process, an overlap margin between the field region and the active region can be secured to prevent excessive loss of the active region due to overetching. By preventing excessive loss of the active region, it is possible to improve the yield and contribute to the reliability.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the effects of the present invention are as follows.

First, the photoresist pattern is not formed only on the active region but partially overlaps the field region, thereby performing an etching process to form a dummy gate, thereby securing an overlap margin between the field region and the active region, thereby overwriting the active region. Excessive loss can be prevented.

Second, it is possible to improve the yield and to contribute to the reliability by preventing excessive loss of the active region.

Claims (5)

Providing a semiconductor substrate including a cell region and a peripheral circuit region, wherein a device isolation film is formed in a field region, and a tunnel insulating film and a first conductive film are formed in an active region; Forming a dielectric film and a second conductive film on the semiconductor substrate including the first conductive film and the device isolation film; The second conductive layer, the dielectric layer, and the first conductive layer are patterned to form a word line and a select line, wherein the second conductive layer included in the select line formed at the outermost part of the cell region is the cell region and the peripheral circuit region. And patterning the pattern so that the edge of the device isolation layer overlaps with the edge of the device isolation layer. The method of claim 1, The method of forming a gate of a semiconductor device, wherein the second conductive film is left to overlap an edge of the device isolation layer by 30 nm to 1000 nm. The method of claim 1, And a dummy gate line is formed in the outermost region of the cell region during the word line and select line forming process. The method of claim 3, And the dummy gate line is floating. The method of claim 3, And the dummy gate line is connected to a well pickup.

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