KR20080061524A - Method of forming dielectric film of semiconductor device - Google Patents
Method of forming dielectric film of semiconductor device Download PDFInfo
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- KR20080061524A KR20080061524A KR1020060136363A KR20060136363A KR20080061524A KR 20080061524 A KR20080061524 A KR 20080061524A KR 1020060136363 A KR1020060136363 A KR 1020060136363A KR 20060136363 A KR20060136363 A KR 20060136363A KR 20080061524 A KR20080061524 A KR 20080061524A
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 150000001408 amides Chemical class 0.000 claims description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- GEIAQOFPUVMAGM-UHFFFAOYSA-N ZrO Inorganic materials [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 4
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 claims description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 239000002243 precursor Substances 0.000 claims description 3
- 229910021193 La 2 O 3 Inorganic materials 0.000 claims description 2
- -1 Ta 2 O 5 Inorganic materials 0.000 claims description 2
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
Description
도 1 내지 도 6은 본 발명의 일실시 예에 따른 반도체 소자의 유전체막 형성 방법을 설명하기 위한 소자의 단면도이다.1 to 6 are cross-sectional views of devices for describing a method of forming a dielectric film of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
100 : 반도체 기판 101 : 제1 산화막100
102 : 제1 크리스탈 라인막 103 : 제2 산화막102: first crystal line film 103: second oxide film
104 : 고유전체막 105 : 폴리 실리콘막104: high dielectric film 105: polysilicon film
본 발명은 반도체 소자의 유전체막 형성 방법에 관한 것으로, 특히 고유전율을 갖는 유전체막의 형성 방법에 관한 것이다.The present invention relates to a method for forming a dielectric film of a semiconductor device, and more particularly to a method for forming a dielectric film having a high dielectric constant.
최근의 반도체 장치는 고집적 및 고성능을 제공하도록 디자인되고 있으며, 특히, 모오스 트랜지스터 및 커패시터에 사용되는 유전체막은 가능한 얇게 형성하 고 있다. 이는, 모오스 트랜지스터의 게이트 유전체막의 두께가 감소할수록 모오스 트랜지스터의 구동전류가 증가하며, 상기 커패시터의 유전체막의 두께가 감소할수록 축적 용량이 증가되기 때문이다. 때문에, 소자의 성능을 향상시키기 위하여 극도로 얇을 뿐만 아니라 신뢰성이 있고 결함이 적은 유전체막을 형성하는 것이 점점 중요해지고 있다.Recently, semiconductor devices are designed to provide high integration and high performance, and in particular, dielectric films used for MOS transistors and capacitors are formed as thin as possible. This is because the driving current of the MOS transistor increases as the thickness of the gate dielectric film of the MOS transistor decreases, and the storage capacitance increases as the thickness of the dielectric film of the capacitor decreases. Therefore, in order to improve the performance of the device, it is increasingly important to form a dielectric film that is not only extremely thin but also reliable and has few defects.
종래에는 일반적으로 게이트 유전막으로 실리콘 산화막을 사용하여 왔다. 이는, 실리콘 기판을 산화시켜 형성하므로 공정이 간단하면서도 매우 안정적이기 때문이다. 그러나, 실리콘 산화막은 3.9 정도의 낮은 유전상수를 가지므로 실리콘 산화막으로 이루어진 게이트 유전체막의 두께를 감소시키는 데에는 한계가 있다. 또한, 상기 실리콘 산화막을 사용하여 게이트 유전막을 매우 얇게 형성하는 경우, 상기 게이트 유전막을 통하여 터널 전류가 흐르게되어 누설 전류가 매우 증가하게 된다. 이에 따라, 상기 게이트 유전막을 고유전 물질을 사용하여 형성하는 방법이 개발되고 있다. 상기 게이트 유전막을 고유전 물질로 형성하는 경우에는, 상기 실리콘 산화물로 형성할 때보다 더 두껍게 형성하면서도 상기 실리콘 산화물과 동일한 커패시턴스를 수득할 수 있다. 따라서, 상기 실리콘 산화물에 비해 높은 유전상수를 갖는 금속산화물들이 게이트 유전체막 또는 커패시터 유전체막에 대한 대체 유전물질들로 제안되어 왔다.Conventionally, a silicon oxide film has been used as the gate dielectric film. This is because the process is simple and very stable since the silicon substrate is formed by oxidizing. However, since the silicon oxide film has a low dielectric constant of about 3.9, there is a limit in reducing the thickness of the gate dielectric film made of the silicon oxide film. In addition, in the case where the gate dielectric layer is formed very thin using the silicon oxide layer, a tunnel current flows through the gate dielectric layer, thereby increasing leakage current. Accordingly, a method of forming the gate dielectric layer using a high dielectric material has been developed. When the gate dielectric layer is formed of a high dielectric material, the same capacitance as that of the silicon oxide may be obtained while being formed thicker than that of the silicon oxide. Accordingly, metal oxides having a higher dielectric constant than silicon oxide have been proposed as alternative dielectric materials for gate dielectric films or capacitor dielectric films.
또한, 상기 실리콘 기판 표면은 고유전 금속산화물과 쉽게 반응하거나 고유전 금속산화물을 증착 또는 후속 열공정을 실시하는 동안 쉽게 산화된다. 따라서, 실리콘기판 및 금속산화막 사이에 실리콘 산화막과 같은 경계막이 형성된다. 결과 적으로, 등가산화막(EOT) 두께가 증가되어 소자의 성능이 저하된다.In addition, the silicon substrate surface easily reacts with the high dielectric metal oxide or is easily oxidized during the deposition or subsequent thermal process of the high dielectric metal oxide. Thus, a boundary film such as a silicon oxide film is formed between the silicon substrate and the metal oxide film. As a result, the equivalent oxide film (EOT) thickness is increased to deteriorate the performance of the device.
또한, 게이트 전극으로 폴리실리콘을 사용하는 경우에는 폴리실리콘 내의 도펀트들이 확산되어 트랜지스터의 특성이 저하된다.In addition, when polysilicon is used as the gate electrode, dopants in the polysilicon are diffused, thereby degrading the characteristics of the transistor.
본 발명이 이루고자 하는 기술적 과제는 고유전체인 크리스탈라인, 산화막, 및 크리스탈라인을 순차적으로 적층된 샌드위치 구조로 형성함으로써, 유전율은 높이고 낮은 게이트 누설전류 특성을 갖는 반도체 소자의 유전체막 형성 방법을 제공한다.SUMMARY OF THE INVENTION The present invention provides a method for forming a dielectric film of a semiconductor device having a high dielectric constant and low gate leakage current by forming a sandwich structure in which crystal lines, oxide films, and crystal lines, which are high dielectric constants, are sequentially stacked. .
본 발명의 일실시 예에 따른 반도체 소자의 유전체막 형성 방법은 반도체 기판 상에 제1 산화막, 제1 크리스탈 라인막, 제2 산화막, 고유전체막, 및 폴리 실리콘막을 순차적으로 적층하는 단계와, 열처리 공정을 실시하여 상기 고유전체막을 제2 크리스탈 라인막으로 형성하는 단계, 및 하드마스크 패턴을 이용한 식각 공정으로 상기 폴리 실리콘막, 상기 제2 크리스탈 라인막, 상기 제2 산화막, 상기 제1 크리스탈 라인막, 및 상기 제1 산화막을 패터닝하여 게이트 유전체막을 형성하는 단계를 포함한다.A dielectric film forming method of a semiconductor device according to an embodiment of the present invention comprises the steps of sequentially depositing a first oxide film, a first crystal line film, a second oxide film, a high dielectric film, and a polysilicon film on a semiconductor substrate, and heat treatment Performing a process to form the high dielectric film as a second crystal line film, and an etching process using a hard mask pattern, and the polysilicon film, the second crystal line film, the second oxide film, and the first crystal line film. And patterning the first oxide film to form a gate dielectric film.
상기 제1 산화막은 1 내지 10Å의 두께의 SiO2막으로 형성하며, 상기 제1 산화막은 650 내지 900℃의 온도에서 형성한다.The first oxide film is formed of a SiO 2 film having a thickness of 1 to 10 GPa, and the first oxide film is formed at a temperature of 650 to 900 ° C.
상기 제1 크리스탈 라인막은 PVD, ALD 또는 MOCVD 방식에 의해 증착시 결정화되도록 형성하며, 상기 제1 크리스탈 라인막은 HfO2, ZrO, La2O3, Ta2O5, TiO2 유전체 중 하나를 결정화하여 형성하며, 상기 제1 크리스탈 라인막은 아미드(amide)계 전구체와 O2 가스를 소스로 300 내지 350℃의 온도에서 40 내지 60Å의 두께로 형성한다.The first crystal line film is formed to crystallize when deposited by PVD, ALD or MOCVD method, the first crystal line film is formed by crystallizing one of HfO2, ZrO, La2O3, Ta2O5, TiO2 dielectric, the first crystal line The film is formed to a thickness of 40 to 60 kPa at a temperature of 300 to 350 ℃ source of the amide (amide) precursor and O 2 gas.
상기 제2 산화막은 ALD 방식을 이용하여 Al2O3 또는 SiO2막으로 형성하며, 상기 제2 산화막은 1 내지 10Å의 두께로 형성한다.The second oxide film is formed of an Al 2 O 3 or SiO 2 film by using an ALD method, and the second oxide film is formed to a thickness of 1 to 10 Å.
상기 고유전체막은 아모포스 물질을 사용하여 형성하며, 상기 고유전체막은 HfO2, ZrO, La2O3, Ta2O5, TiO2 유전체 중 하나로 형성하며, 상기 고유전체막은 ALD 방식을 이용하여 20 내지 40Å의 두께로 형성한다.The high-k dielectric film is formed using an amorphous material, the high-k dielectric film is formed of one of HfO2, ZrO, La2O3, Ta2O5, TiO2 dielectric, the high-k dielectric film is formed to a thickness of 20 to 40Å by ALD method.
상기 열처리 공정은 RTP 방법에 의해 900 내지 1300℃의 고온에서 진행한다.The heat treatment process is carried out at a high temperature of 900 to 1300 ℃ by the RTP method.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허청구범위에 의해서 이해되어야 한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.
도 1 내지 도 6은 본 발명의 일실시 예에 따른 반도체 소자의 유전체막 형성 방법을 설명하기 위한 소자의 단면도이다.1 to 6 are cross-sectional views of devices for describing a method of forming a dielectric film of a semiconductor device according to an embodiment of the present invention.
도 1을 참조하면, 먼저 세정 공정을 실시하여 반도체 기판(100) 표면의 불순물을 제거한다. 세정 공정은 100 : 1로 물로 희석된 HF 용액을 사용하는 것이 바람직하다. 반도체 기판(100) 상에 제1 산화막(101)을 형성한다. 제 1 산화막(101)은 RTO 또는 습식 산화 방식을 이용하여 형성하는 것이 바람직하다. 또한 제 1 산화막(101)은 SiO2막으로 형성하는 것이 바람직하다. SiO2막은 1 내지 10Å의 두께로 형성하는 것이 바람직하다. 제 1 산화막(101)은 650 내지 900℃의 온도에서 형성하는 것이 바람직하다.Referring to FIG. 1, first, a cleaning process is performed to remove impurities from the surface of the
도 2를 참조하면, 제 1 산화막(101)을 포함하는 전체 구조 상부에 제1 크리스탈 라인막(102)을 형성한다. 제1 크리스탈 라인막(102)은 PVD, ALD 또는 MOCVD 방식에 의해 증착시 결정화되는 두께로 형성한다. 제1 크리스탈 라인막(102)은 HfO2, ZrO, La2O3, Ta2O5, TiO2 유전체 중 하나로 형성하는 것이 바람직하다. 또한 제1 크리스탈 라인막(102)은 40 내지 60Å의 두께로 형성하는 것이 바람직하다. 제1 크리스탈 라인막(102)은 아미드(amide)계 전구체와 O2 가스를 소스로 300 내지 350℃의 온도에서 형성하는 것이 바람직하다.Referring to FIG. 2, the first
도 3을 참조하면, 제1 크리스탈 라인막(102)을 포함하는 전체 구조 상부에 제2 산화막(103)을 형성한다. 제2 산화막(103)은 ALD 방식을 이용하여 Al2O3 또는 SiO2막으로 형성하는 것이 바람직하다. Al2O3 또는 SiO2막은 1 내지 10Å의 두께로 형성하는 것이 바람직하다. 제2 산화막(103)은 후속 형성되는 제2 크리스탈 라인과 제1 크리스탈 라인(102)과의 그레인 바운더리(grain boundary) 미스매치(mismatch) 를 유발하여 전류 패스를 차단하는 막으로 사용된다.Referring to FIG. 3, a
도 4를 참조하면, 제2 산화막(103)을 포함하는 전체 구조 상에 고유전체막(104)을 형성한다. 고유전체막(104)은 아모포스 물질을 사용하여 형성하는 것이 바람직하다. 고유전체막(104)은 HfO2, ZrO, La2O3, Ta2O5, TiO2 유전체 중 하나로 형성하는 것이 바람직하다. 고유전체막(104)은 ALD 방식을 이용하여 20 내지 40Å의 두께로 형성하는 것이 바람직하다.Referring to FIG. 4, a high
도 5를 참조하면, 고유전체막(104)을 포함하는 전체 구조 상에 폴리 실리콘막(105)을 형성한다.Referring to FIG. 5, a
도 6을 참조하면, 열처리 공정을 실시하여 도 4을 고유전체막(104) 결정화하여 제2 크리스탈 라인(104')으로 형성한다. 열처리 공정은 RTP 방법에 의해 900 내지 1300℃의 고온에서 진행하는 것이 바람직하다.Referring to FIG. 6, a heat treatment process is performed to form FIG. 4 to crystallize the high
이 후, 도면으로 도시되진 않았지만 하드 마스크 패턴을 이용한 식각 공정을 진행하여 폴리 실리콘막(105), 제2 크리스탈 라인(104'), 제2 산화막(103), 제1 크리스탈 라인(102), 및 제1 산화막(101)을 식각하여 게이트 유전체를 형성한다. Subsequently, although not shown in the drawings, an etching process using a hard mask pattern may be performed to form the
상술한 바와 같이 고유전체막인 제1 크리스탈 라인(102), 제2 산화막(103), 및 제2 크리스탈 라인(104')의 샌드위치 구조로 유전체막을 형성함으로써, 결정화된 고유전체로부터 낮은 EOT와 낮은 게이트 누설 전류 특성을 얻을 수 있어 고집적, 고성능의 게이트 유전체막을 형성할 수 있다. As described above, the dielectric film is formed in the sandwich structure of the
본 발명의 기술 사상은 상기 바람직한 실시 예에 따라 구체적으로 기술되었 으나, 상기한 실시 예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다. Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명의 일실시 예에 따르면, 고유전체인 크리스탈라인, 산화막, 및 크리스탈라인을 순차적으로 적층된 샌드위치 구조로 형성함으로써, 유전율은 높이고 낮은 게이트 누설전류 특성을 갖는 반도체 소자의 유전체막을 형성할 수 있다.According to an embodiment of the present invention, by forming a sandwich structure in which crystal lines, oxide films, and crystal lines, which are high dielectric materials, are sequentially stacked, a dielectric film of a semiconductor device having a high dielectric constant and low gate leakage current characteristics may be formed. .
Claims (12)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101125567B1 (en) * | 2009-12-24 | 2012-03-22 | 삼성모바일디스플레이주식회사 | Polymer substrate and method of manufacturing the same and display device including the polymer substrate and method of manufacturing the display device |
| US11522082B2 (en) | 2019-09-18 | 2022-12-06 | Samsung Electronics Co., Ltd. | Electronic device and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101125567B1 (en) * | 2009-12-24 | 2012-03-22 | 삼성모바일디스플레이주식회사 | Polymer substrate and method of manufacturing the same and display device including the polymer substrate and method of manufacturing the display device |
| US11522082B2 (en) | 2019-09-18 | 2022-12-06 | Samsung Electronics Co., Ltd. | Electronic device and method of manufacturing the same |
| US11824118B2 (en) | 2019-09-18 | 2023-11-21 | Samsung Electronics Co., Ltd. | Electronic device and method of manufacturing the same |
| US12230711B2 (en) | 2019-09-18 | 2025-02-18 | Samsung Electronics Co., Ltd. | Electronic device and method of manufacturing the same |
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