KR20080056845A - Nonvolatile Semiconductor Memory Device Reduces Erasing Stress and Erasing Time - Google Patents

Abstract

The present invention discloses a nonvolatile semiconductor memory, such as a flash memory, which can minimize or reduce the electrical stress and erase time resulting from an erase operation. According to the present invention, a nonvolatile semiconductor memory having a memory cell array includes a current erase operation for information on an erase voltage that has been applied as a last erase voltage in a previous erase operation mode in each erase block unit of the memory cell array. By providing an erasing circuit for erasing with reference in the mode, the electrical stress and the erasing time applied to the memory cell transistor are reduced as compared with the conventional erasing method. Accordingly, there is an advantage in that the reliability characteristics and the erase performance of the erase operation of the nonvolatile semiconductor memory device are improved.

Description

Non-volatile semiconductor memory device with reduced erase stress and erase time

1 is a diagram illustrating an application level of an erase voltage in an erase operation mode of a conventional nonvolatile semiconductor memory.

2 is a flowchart illustrating an erase operation of the erase operation mode according to FIG. 1.

3 shows an increase in the voltage pulse applied with an increase in program and erase cycles according to FIG.

4 is a diagram illustrating an erase voltage application method in an erase operation mode of a nonvolatile semiconductor memory according to an exemplary embodiment of the present invention.

5 is a flowchart illustrating an erase operation of the erase operation mode according to FIG. 4.

6 is a diagram illustrating storing information regarding an erase voltage in a spare bit area according to FIG. 4.

FIG. 7 shows an increase in the voltage pulse applied with an increase in program and erase cycles according to FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to nonvolatile semiconductor memories, and more particularly to nonvolatile semiconductor memories that store data by injecting or releasing charges into floating gates.

In recent years, with the rapid development of information processing apparatuses such as computers, semiconductor memory devices employed as important components of information processing apparatuses have also become high-speed operation and large capacity.

In general, semiconductor memory devices are largely divided into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. Volatile semiconductor memory devices may be further classified into dynamic random access memory and static random access memory. Such a volatile semiconductor memory device is fast in terms of read and write speed, but has a disadvantage in that contents stored in a memory cell are lost when the external power supply is cut off. The nonvolatile semiconductor memory device may include a mask read only memory (MROM), a programmable read only memory (PROM), an erasable and programmable read only memory (EPROM), and an electrical device. And erasable programmable read only memory (EEPROM).

The nonvolatile semiconductor memory device of this kind is mainly used to store contents to be preserved regardless of the power supply since the contents can be permanently stored in the memory cell even when the external power supply is interrupted. However, in the case of the MROM, PROM, and EPROM, general users are not free to erase and write (or program) themselves through an electronic system. In other words, it is not easy to erase or reprogram the programmed contents on-board. On the other hand, in the case of the EEPROM, since the operation of electrically erasing and writing is possible by the system itself, the application to the system program storage device or the auxiliary memory device requiring continuous contents update is continuously expanding.

Many electronic devices controlled by modern computers or microprocessors have further demanded the development of high density electrically erasable and programmable EEPROMs. Moreover, data storage devices, such as digital cameras, are required to be compact in size, and the use of a hard disk device having a rotating magnetic disk as a secondary memory device as a secondary memory device in a portable computer or notebook-sized battery-powered computer system is also required. Designers of such systems are very interested in the development of high density, high performance EEPROMs that occupy smaller areas.

NAND-type flash EEPROMs with flash erase function, which have emerged with the advancement of EEPROM design and manufacturing technology, have a high degree of integration compared to conventional EEPROMs, which is very advantageous for application to large capacity auxiliary storage devices. The flash EEPROM is classified into a NAND type, a NOR type, or an AND type according to the type of a unit memory cell array configuration. The NAND type has a higher density than the NOR or AND type. It is widely known in the art.

The construction of a conventional nonvolatile semiconductor memory device block and a cross-section of the memory cells in a memory cell array are disclosed, for example, in US Pat. No. US 6,295,227, registered September 25, 2001 in the United States.

In the above patent, a data input / output buffer, a row decoder for selecting word lines, a column decoder, a column gate, a sense amplifier circuit, a booster circuit for generating a boosting voltage for sensing and storing input / output data of memory cell transistors, and a memory device. The control circuit that controls the operation, and the memory cell array, constitute a NAND type EEPROM.

The memory cell array includes bit lines for transmitting and receiving data to memory cell transistors in a NAND cell unit (or cell string), gates of the memory cell transistors in the NAND cell unit and the select transistors while crossing the bit lines. It includes word lines for controlling the.

In a memory cell array, a NAND cell unit is formed in a p-type well formed on top of an n-type well. The NAND cell unit forming one string unit includes a first selection transistor SST having a drain connected to a bit line, a second selection transistor ST having a source connected to a common source line, and the first selection transistor SST. And 16 or 32 memory transistors connected in series between the source and the drain of the second selection transistor ST. Each memory cell transistor constituting the NAND cell unit has a floating gate formed on the channel region between its source and drain regions via a gate oxide film, and a control gate formed on the floating gate through an interlayer insulating film. Charges that function as program data are accumulated in the floating gate FG by a program voltage applied to the control gate CG.

The erase, write, and read operations of the NAND type EEPROM are described as follows. Erase and program (or write) operations are accomplished by using known F-N tunneling currents. For example, during erasing, a very high potential is applied to the substrate and a low potential is applied to the CG. In this case, a potential determined by the capacitance between CG and FG and the coupling ratio between the FG and the capacitance between the substrate is applied to the FG. If the potential difference between the floating gate voltage Vfg applied to the FG and the substrate voltage Vsub applied to the substrate is greater than the potential difference that may cause F-N tunneling, electrons collected in the FG move from the FG to the substrate. When such an operation occurs, the threshold voltage Vt of the memory cell transistor including CG, FG, source, and drain is lowered. Even when the Vt is sufficiently low and 0 V is applied to the CG and the source, when the current flows when a moderately high voltage is applied to the drain, we say that it is "ERASE" and logically denoted as "1". .

On the other hand, during writing, 0 V is applied to the source and drain, and a very high voltage is applied to CG. At this time, an inversion layer is formed in the channel region so that both the source and the drain have a potential of 0V. If the potential difference applied between Vfg and Vchannel (0 V), determined by the ratio of capacitances between CG and FG and between the FG and channel regions, is large enough to cause F-N tunneling, electrons move from the channel region to FG. In this case, Vt increases, and if the current is not flowing when a preset positive voltage is applied to CG, 0 V is applied to the source, and a proper voltage is applied to the drain, we call it "PROGRAM." "Is often indicated.

In the configuration of the memory cell array, a page unit refers to memory cell transistors in which a control gate is commonly connected to one word line. A plurality of pages including a plurality of memory cell transistors is called a cell block, and a unit of one cell block typically includes one or a plurality of cell strings per bit line. The NAND flash memory has a page program mode for high speed programming. The page program operation consists of a data loading operation and a program operation. The data loading operation sequentially latches and stores byte sized data from the input / output terminals in the data registers. Data registers are provided to correspond to each bit line. A program operation is an operation of temporarily writing data stored in the data registers into memory transistors on a selected word line through bit lines.

The NAND type EEPROM as described above generally performs read (read), program (write) operations in units of pages, and erase operations in units of blocks. In practice, the electron movement between the FG and the channel of the memory cell transistor occurs only in a program and erase operation, and in the read operation, an operation of only reading data stored in the memory cell transistor without harmless after the operations are terminated occurs. .

In a read operation, a voltage (typically a read voltage) higher than a voltage (usually a ground voltage) applied to the CG of the selected memory cell transistor is applied to the unselected CG of the memory cell transistor. Then, current may or may not flow on the corresponding bit line according to the program state of the selected memory cell transistor. If a threshold voltage of a programmed memory cell is higher than a reference value under a predetermined voltage condition, the memory cell is read off-cell and a high level voltage is charged on a corresponding bit line. On the contrary, if the threshold voltage of the programmed memory cell is lower than the reference value, the memory cell is read on-cell and the corresponding bit line is discharged to a low level. This bit line state is finally read as "0" or "1" through the sense amplifier called the page buffer.

In the nonvolatile semiconductor memory as described above, the conventional method of applying the erase voltage in the erase operation mode is shown in FIG.

1 is a view illustrating an application level of an erase voltage in an erase operation mode of a conventional nonvolatile semiconductor memory. 2 is a flowchart illustrating an erase operation of the erase operation mode according to FIG. 1, and FIG. 3 is a diagram illustrating an increase in a voltage pulse applied according to an increase in a program and an erase cycle according to FIG. 1.

Referring to FIG. 1, in the first erase operation cycle # 1, a preset initial erase voltage is applied as much as the level L1, and verification is performed to verify whether the erase for the erase block is successful. If the threshold voltage of the memory cell transistor selected by the initial erase voltage is about -3V, it is normal that the verification result is failed when it turns out to be -2V and is out of the error range. Here, the initial voltage of the erase voltage may be determined by laser cutting or an electrically blowable fuse after fabrication of the memory.

Thus, the second erase operation cycle # 2 proceeds for the erased block that failed verification. In the second cycle # 2, the voltage L2 increased by the predetermined level DELTA VISEP from the erase voltage level L1 is applied as the erase voltage. The above voltages are provided in high voltage pumps. If the verification fails as a result of the second cycle # 2, the third erase operation cycle # 3 is performed. Also in the third erase operation cycle # 3, the voltage L3 increased by one step from the voltage L2 is applied. As described above, it can be seen that as the failure failures are repeated, the level of the erase voltage applied thereafter gradually increases.

As a result, in the conventional erasing operation, similarly to the program voltage application method of the program operation, the erase voltage application operation of multiple cycles and the erase verify operation of multiple cycles are performed. An erase operation sequence is performed to implement the erase operation as shown in FIG. 2 as a chart.

That is, referring to FIG. 2, when the block erase command is received in step S20, an initial erase voltage and the number of times are set in step S21, and the erase voltage is applied in block S22 by applying an erase voltage in step S22. Verify is performed in step S23, and the erase operation is terminated if the result of the verify check in step S24 is successful. However, if it fails in step S24, the number is increased by one in step S25, and the process proceeds to step S26. In step S26, the voltage of which the predetermined unit step voltage is increased from the initial erase voltage is determined as the erase voltage in the next cycle. When the execution of the step S26 is completed, the step S22 is restarted to apply the erase voltage and the erase verifier in the next cycle.

As shown in FIG. 3 in which the horizontal axis X is represented by the cycling number and the vertical axis Y is represented by the erase voltage, the P / E (program / erase) cycling of the memory device proceeds. Since the occurrence of electron traps also increases, the erase voltage that must be applied in an erase operation in which the memory cell must be lowered to a voltage below a certain erase threshold voltage (Erase Vth) is required to be increased. Therefore, the erase time required for the erase operation is also increased.

As a result, in the conventional case, when VeriFi fails by applying the set super erase voltage, the erase voltage which is increased by a predetermined voltage (ΔVISEP: Incremental Step Erase Pulse) from the initial erase voltage is additionally applied again. Pi has been performing the action. In this manner, as shown in FIG. 3, as the P / E cycling increases, the number of erase voltage pulses applied increases.

The problem with the conventional erase operation as described above is as follows.

First, an increase in the number of erase pulses due to an increase in P / E cycling causes an increase in electrical stress applied to the memory cell transistor. As a result, the reliability characteristics of the memory cells are deteriorated.

Second, there is a problem of increasing erase time. As a result, an increase in erase time becomes a factor causing performance degradation of the semiconductor memory device.

Accordingly, there is a need in the art for certain measures to reduce the erase voltage stress and the erase time that a memory cell transistor receives in an erase operation mode of a nonvolatile semiconductor memory.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory that can overcome the problems of the prior art.

Another object of the present invention is to provide a nonvolatile semiconductor memory capable of minimizing or reducing electrical stress caused by an erase operation.

It is still another object of the present invention to provide a method of performing an erase operation in a nonvolatile semiconductor memory such as a flash memory capable of minimizing or reducing an erase time required for erase in an erase operation mode.

A nonvolatile semiconductor memory according to an aspect of the present invention for achieving the above technical problem relates to an erase voltage applied as a last erase voltage in a previous erase operation mode in each erase block unit of the memory cell array. And an erase circuit for erasing by referring to the information in the current erase operation mode.

Preferably, the information about the erase voltage can be stored in the spare cell area of each erase block, and the erase voltage that was applied as the last erase voltage is the erase voltage that caused the erase verification pass. The erase circuit may be configured to apply the last erase voltage as the first erase voltage in the current erase operation mode by referring to information stored in the spare cell area of each erase block. If the matter is different, the erase circuit applies a voltage one step lower or higher than the last erase voltage as the first erase voltage in the current erase operation mode by referring to the information stored in the spare cell area of each erase block. You can do that.

According to another aspect of the invention, a method of performing an erase operation in a nonvolatile semiconductor memory having a memory cell array,

Applying an initial erase voltage in units of erase blocks of a memory cell array in a first erase operation mode and executing erase verification;

Applying a voltage gradually increased from the initial erase voltage by a predetermined level when the erase verifier fails, and performing an erase verifier every time;

Storing information on the erase voltage applied in the success step of the verify in the erase block unit upon success of the erase verify;

In a second erase operation mode performed after the end of the first erase operation mode, reading information on the stored erase voltage and determining an erase voltage to be currently applied;

And applying the determined erase voltage as a new initial erase voltage in units of erase blocks of a memory cell array.

According to the device method configuration of the present invention described above, the electrical stress and the erase time applied to the memory cell transistors are reduced compared to the conventional erase method. Accordingly, there is an advantage in that the reliability characteristics and the erase performance of the erase operation of the nonvolatile semiconductor memory device are improved.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 to 7 without any intention other than to provide a thorough understanding of the present invention by those skilled in the art. .

First, in order to reduce the electrical stress and erasure time applied to the memory cell transistors compared to the conventional erasing method, in the case of the present invention, each erase block of the memory cell array is used in the previous erase operation mode. And an erase circuit for performing erasure by referring to information on the erase voltage that has been applied as the last erase voltage in the current erase operation mode.

The erase circuit applies an erase voltage corresponding to the selected block with reference to bit information for setting an optimized erase voltage for each erase block in an erase operation mode. As a result, an advantage of improving reliability characteristics and erase performance of the memory cell is achieved through the present invention.

4 is a diagram illustrating an erase voltage application method in an erase operation mode of a nonvolatile semiconductor memory according to an exemplary embodiment of the present invention. 5 is a flowchart of an erase operation of the erase operation mode according to FIG. 4. FIG. 6 is a diagram illustrating storing information about an erase voltage in a spare bit area according to FIG. 4, and FIG. 7 is a diagram illustrating an increase of a voltage pulse applied according to an increase in program and erase cycles according to FIG. 4. to be.

First, referring to FIG. 4, the erase voltage application method according to the present invention is well illustrated. When the erase operation is performed for a certain erase block for the first time, that is, in the initial state, the initial erase voltage is applied and the verification is performed in the same manner as the conventional erase voltage application method. As shown by arrow AR1, if Verify is unsuccessful, a voltage increased by a predetermined level (ΔVISEP) is applied as the erase voltage of the next cycle and Verify is performed. As a result, when the erase verifier fails due to one erase voltage application, the erase operation is cumulatively increased by a predetermined voltage ΔVISEP and the erase operation is performed until the successful verification. In this way, if the verification is successful in a cycle, information about the erase voltage used at this time is stored in the spare area of the memory cell array corresponding to the erased block.

After the erase verification is successful, in the case where the next erase operation is performed again after the program and read operations, the initial erase voltage preset by the fuse or the like is no longer applied. That is, from now on, the erase voltage is directly referenced to (or read) information about the erase voltage applied as the last erase voltage in the previous erase operation mode so that the erase verification can be successful at one time in the current erase operation mode. It is authorized. Because of great importance, it is emphasized again that after the arrival of the second erase mode of operation, such an erase voltage is applied from the beginning, which can bring the success of the erase verifier in one shot. As a result, this scheme significantly shortens the erase time and reduces the erase voltage stress that the selected memory cell transistors are subjected to.

Following arrow AR2 of FIG. 4, it is shown that in the next erase operation, the newly corrected erase voltage is applied immediately in the first cycle. For those who understand the description so far, further explanation may be pointed out, but the description of FIG. 5 will be continued in order to provide a more thorough understanding of the present invention.

Referring to FIG. 5, in order to reduce an application and time of an unnecessary erase pulse according to an inherent technical concept of the present invention, an erase voltage used for reading the information about the erase voltage stored in the erase block and immediately before erasing, or the like. A sequence of performing the current erase operation using the newly defined erase voltage based on the voltage is shown as steps S50 to S59.

Before applying the erase voltage of step S52 of FIG. 5, an m value, which is a past erase value representing information of a previous erase voltage, is first read in step S51. In the first erasing operation mode, since the past erasing value is not stored, the m value becomes zero. As a result, the initial erase voltage becomes the erase voltage level set by the fuse. As a result, in the first erase operation mode, an initial erase voltage is applied in units of erase blocks of the memory cell array in step S53, and erase erase is performed in step S54. When the erase verifier fails (step S55), steps S58 and S59 are executed to apply a voltage gradually increased from the initial erase voltage by a predetermined level step, and erase erase is performed every time. Subsequently, in step S55, steps S56 and S57 are executed to store and update information on the erase voltage applied in the erase block in the erase block unit upon success of the erase verifier.

In the second erase operation mode performed after the end of the first erase operation mode, the information on the stored erase voltage is read in step S51 and the erase voltage to be applied currently is determined in step S52. In operation S53, the determined erase voltage is applied as an initial erase voltage in units of erase blocks of the memory cell array, and an erase verifier is executed in step S54. In the case where the erase verifier fails in step S55, steps (S58 and S59) are performed to apply a voltage gradually increased from the initial erase voltage by a predetermined level step and perform an erase verifier every time. However, upon the success of the erase verifier, a step (S57) of updating the previously stored information with information on the erase voltage applied in the success stage of the verify is performed.

As a result, once the erase verifier result is successful, the m value at that time is stored correspondingly for each erase block, and in the next erase operation mode, the verifier succeeds at once with reference to the stored information. A voltage that can be applied is applied as the erase voltage.

As an example of a method of storing the m value, there may be a method of storing the spare value of each block constituting the memory cell array as shown in FIG. 6. Reference numeral 60 indicates that the optimum erase voltage for each block is set in the spare bit area.

The effects of the present invention are as follows.

By using the technique of the present invention, since the erase pulse is basically applied only once, as shown in FIG. 7 as opposed to FIG. 3, since the voltage stress applied to the memory cell is not continuous, The voltage stress of the memory cell transistors is greatly reduced. As a result, the reliability characteristics of the memory cell are improved. And while the erase time in the erase operation is shortened, a constant time can be maintained on average. Thus, the performance of the NAND flash memory is improved.

Meanwhile, an erase circuit for selecting normal memory cells corresponding to an input address and erasing data by applying an erase voltage from the selected normal memory cells includes a data input / output buffer, a row decoder, a column decoder, a column gate, a high voltage generation circuit, and a control. It consists of a circuit.

The description in the above embodiments is only given by way of example with reference to the drawings for a more thorough understanding of the present invention, it should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention. For example, when the case is different, the level of the initial erase voltage applied in the late erase operation cycle may be set differently, or the configuration or operation of the erase circuit may be changed differently.

According to the nonvolatile semiconductor memory and the erase operation method of the present invention as described above, information about the erase voltage that has been applied as the last erase voltage in the previous erase operation mode in each erase block unit of the memory cell array may be erased. Since an erase circuit for performing an erase with reference in the operation mode is provided, an electrical stress and an erase time applied to the memory cell transistor are reduced as compared with the conventional erase scheme. Therefore, there is an advantage in that the reliability characteristics and the erase performance of the erase operation of the nonvolatile semiconductor memory device are improved.

Claims (12)

In a nonvolatile semiconductor memory having an array of memory cells: And an erase circuit configured to perform erase by referring to the information on the erase voltage applied as the last erase voltage in the previous erase operation mode in each erase block unit of the memory cell array in the current erase operation mode. Volatile Semiconductor Memory. The nonvolatile semiconductor memory of claim 1, wherein the information about the erase voltage is stored in a spare cell area of each erase block. 2. The nonvolatile semiconductor memory according to claim 1, wherein the erase voltage applied as the last erase voltage is an erase voltage causing an erase verification pass. 3. The non-volatile memory according to claim 2, wherein the erase circuit applies the last erase voltage as an initial erase voltage in a current erase operation mode by referring to information stored in a spare cell area of each erase block. Volatile Semiconductor Memory. The erase circuit of claim 2, wherein the erase circuit applies a voltage one step lower or higher than the last erase voltage as an initial erase voltage in a current erase operation mode by referring to information stored in the spare cell area of each erase block. Nonvolatile semiconductor memory, characterized in that. In a nonvolatile semiconductor memory having an array of memory cells: Information about the erase voltage applied as the last erase voltage in the previous erase operation mode in order to reduce the electrical stress applied to the memory cell transistor and reduce the erase time when the erase operation is performed in each erase block unit of the memory cell array. And an erasing circuit for erasing by referring to the current erasing operation mode. The nonvolatile semiconductor memory of claim 6, wherein the information about the erase voltage is stored in a spare cell area of each erase block. 7. The nonvolatile semiconductor memory of claim 6, wherein the erase voltage applied as the last erase voltage is an erase voltage causing an erase verification pass. 8. The non-volatile memory of claim 7, wherein the erase circuit applies the last erase voltage as an initial erase voltage in a current erase operation mode by referring to information stored in a spare cell area of each erase block. Volatile Semiconductor Memory. The erase circuit of claim 7, wherein the erase circuit applies a voltage one step lower or higher than the last erase voltage as an initial erase voltage in a current erase operation mode by referring to information stored in the spare cell area of each erase block. Nonvolatile semiconductor memory, characterized in that. A method of performing an erase operation in a nonvolatile semiconductor memory having a memory cell array, the method comprising: Applying an initial erase voltage in units of erase blocks of a memory cell array in a first erase operation mode and executing erase verification; Applying a voltage gradually increased from the initial erase voltage by a predetermined level when the erase verifier fails, and performing an erase verifier every time; Storing information on the erase voltage applied in the success step of the verify in the erase block unit upon success of the erase verify; In a second erase operation mode performed after the end of the first erase operation mode, reading information on the stored erase voltage and determining an erase voltage to be currently applied; And applying the determined erase voltage as a new initial erase voltage in units of erase blocks of a memory cell array. A method of performing an erase operation in a nonvolatile semiconductor memory having a memory cell array, the method comprising: Applying an initial erase voltage in units of erase blocks of a memory cell array in a first erase operation mode and executing erase verification; Applying a voltage gradually increased from the initial erase voltage by a predetermined level when the erase verifier fails, and performing an erase verifier every time; Storing information on the erase voltage applied in the success step of the verify in the erase block unit upon success of the erase verify; In a second erase operation mode performed after the end of the first erase operation mode, reading information on the stored erase voltage and determining an erase voltage to be currently applied; Applying the determined erase voltage as an initial erase voltage in units of erase blocks of a memory cell array and executing erase verification; Applying a voltage gradually increased from the initial erase voltage by a predetermined level when the erase verifier fails, and performing an erase verifier every time; And updating the previously stored information with the information on the erase voltage applied in the successful step of the successful verification when the erase verifier is successful.

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