KR20080053645A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the exemplary embodiment of the present invention is formed on a substrate, a gate line formed on the substrate, a first conductive layer of a common signal line formed of the same layer as the gate line, and the gate line. A gate insulating film having a first contact hole exposing a conductive layer, a semiconductor layer formed on the gate insulating film, a data line and a drain electrode formed on the gate insulating film or the semiconductor layer and including a source electrode, and the same as the data line A second conductive layer of a common signal line connected to the first conductive layer through the first contact hole, and a pixel electrode connected to the drain electrode.

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

1 is a perspective view schematically illustrating a structure of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a layout view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

3 and 4 are cross-sectional views of the thin film transistor array panel of FIG. 2 taken along lines III-III and IV-IV, respectively.

FIG. 5 is a plan view illustrating the structure of the common signal line in more detail in the thin film transistor array panel of FIG. 2.

FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI.

7, 12, 16, and 20 are layout views sequentially illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention.

8 and 9 are cross-sectional views illustrating the thin film transistor array panel of FIG. 7 taken along lines VIII-VIII and IX-IX,

13 and 14 are cross-sectional views of the thin film transistor array panel of FIG. 12 taken along lines XIII-XIII and XIV-XIV.

17 and 18 are cross-sectional views of the thin film transistor array panel of FIG. 16 taken along lines XVII-XVII and XVIII-XVIII.

21 and 22 are cross-sectional views of the thin film transistor array panel of FIG. 20 taken along lines XXI-XXI and XXII-XXII.

10, 11, 15, 19 and 23 are cross-sectional views showing the manufacturing process sequence of the common signal line according to the manufacturing process sequence of the thin film transistor array panel.

24 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

25 and 26 are cross-sectional views of the thin film transistor array panel of FIG. 24 taken along lines XXV-XXV and XXVI-XXVI.

27 is a cross-sectional view illustrating a structure of a common signal line in a thin film transistor array panel according to another exemplary embodiment of the present invention.

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel displays, and includes a field generating electrode that generates an electric field such as a pixel electrode and a common electrode, and a liquid crystal layer filled in the gap between the display panel and the display panel having a gap therebetween. It includes. In such a liquid crystal display, an electric field is formed on the liquid crystal layer by applying a voltage to two field generating electrodes to determine the alignment of liquid crystal molecules and to adjust the polarization of incident light to display an image.

The liquid crystal display includes a plurality of pixels including a field generating electrode and a thin film transistor connected thereto and arranged in a matrix form, and a plurality of signal lines transferring signals thereto. The signal line includes a gate line for transmitting a scan signal and a data line for transmitting a data signal, and each pixel includes a color filter for displaying color in addition to the field generating electrode and the thin film transistor.

The gate line, the data line, the pixel electrode, and the thin film transistor are disposed on one of the two display panels, and this display panel is commonly referred to as a thin film transistor display panel. The other display panel is generally provided with a common electrode and a color filter. The display panel is generally referred to as a common electrode display panel, and a liquid crystal layer exists between the thin film transistor array panel and the common electrode display panel, and the two display panels have a short point. Are electrically connected to each other through In this case, the common electrode receives a common voltage through a short point, and the common voltage is transmitted to a short point through a common signal line from the outside.

However, corrosion occurs frequently at the contact portion of the common signal line in contact with the short circuit point, thereby increasing the specific resistance of the signal line. As a result, distortion of the common voltage occurs, thereby causing cross talk or flicker, thereby degrading the display device.

Accordingly, an object of the present invention is to solve the above problems and to provide a thin film transistor array panel and a method of manufacturing the same which can ensure reliability of a common signal line.

The thin film transistor array panel according to the exemplary embodiment of the present invention is formed on a substrate, a gate line formed on the substrate, a first conductive layer of a common signal line formed of the same layer as the gate line, and the gate line. A gate insulating film having a first contact hole exposing a conductive layer, a semiconductor layer formed on the gate insulating film, a data line and a drain electrode formed on the gate insulating film or the semiconductor layer and including a source electrode, and the same as the data line A second conductive layer of a common signal line connected to the first conductive layer through the first contact hole, and a pixel electrode connected to the drain electrode.

The display device may further include a contact auxiliary member connected to the second conductive layer through a passivation layer formed between the pixel electrode and the drain electrode and a second contact hole of the passivation layer.

The common signal line is preferably formed in a slit or grate shape, and the first contact hole or the second contact hole preferably has a slit or grate shape along the shape of the common signal line connected to the contact auxiliary member.

In a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, forming a first conductive layer of a gate line and a common signal line on a substrate, and having a first contact hole exposing the first conductive layer on the gate line. Forming an insulating layer, forming a semiconductor layer on the gate insulating layer, and a second conductive layer of the common signal line connected to the first conductive layer through a data line, a drain electrode, and the first contact hole on the semiconductor layer. Forming a pixel electrode connected to the drain electrode.

A contact auxiliary member connected to the second conductive layer may be formed on the same layer as the pixel electrode, and a passivation layer having a second contact hole connecting the second conductive layer and the contact auxiliary member is formed between the pixel electrode and the drain electrode. It may further comprise the step.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1.

1 is a perspective view illustrating a structure of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display according to the present exemplary embodiment includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer (not shown) interposed therebetween. In addition, the liquid crystal display device confines the liquid crystal layer filled between the two display panels 100 and 200, and electrically connects the sealing material 310 for bonding the two display panels 100 and 200 to the two display panels 100 and 200. Includes a shorting point 410. The short point 410 is for transmitting a common voltage to a common electrode (not shown) formed on the upper panel 200, and the lower panel 100 is common for transferring a common voltage to the short point 410. Signal lines (not shown) are disposed, which will be described in detail with reference to FIGS. 5 and 6.

The liquid crystal display is divided into a display area DA and a peripheral area PA positioned outside the display area DA, and the sealing material 310 is positioned at a boundary between the display area DA and the peripheral area PA. The shorting point 410 is disposed to overlap with the sealing material 310. The position and number of the short circuit point 410 may be changed in various ways.

Next, the thin film transistor array panel 100 (lower display panel) according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 6.

FIG. 2 is a layout view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 3 and 4 illustrate the thin film transistor array panel of FIG. 2 taken along lines III-III and IV-IV, respectively. 5 is a plan view illustrating the structure of the common signal line in the thin film transistor array panel of FIG. 2 in detail. FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI.

A plurality of gate lines 121, a plurality of storage electrode lines 131, and a first conductive layer of the common signal line 400 may be formed on an insulating substrate 110 made of transparent glass or plastic. 128) are formed.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding downward and an end portion 129 having a large area for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal may be mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110, It may be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage, and includes a stem line extending substantially in parallel with the gate line 121 and a plurality of pairs of storage electrodes 133a and 133b separated therefrom. Each of the storage electrode lines 131 is positioned between two adjacent gate lines 121, and the stem line is closer to the lower side of the two gate lines 121. Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line and a free end opposite thereto. The fixed end of one sustain electrode 133a has a large area, and its free end is divided into two parts, a straight part and a bent part. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The common signal line 400 transmits a common voltage of a common electrode (not shown) formed on the upper panel 200 (see FIG. 1) facing the thin film transistor array panel 100 and receives a common signal from the outside. A portion 430 and a short point 410 (see FIG. 1) are formed to include a contact portion 420 electrically connected to the upper panel 200. At this time, the common signal line 400 has a slit or grate shape, which is blocked by the common signal line 400 when the ultraviolet rays are irradiated to incline the sealing material 310 (see FIG. 1) during the manufacturing process. To minimize this.

The first conductive layer 128 of the gate line 121, the storage electrode line 131, and the contact portion 420 includes lower layers 124p, 128p, 131p, 133ap, and 133bp made of aluminum-based metal such as aluminum or an aluminum alloy. And upper films 124q, 128q, 131q, 133aq, and 133bq containing molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys.

3 and 4, the lower layer of the gate electrode 124 and the storage electrode line 131 is denoted by the letter p and the letter q of the upper layer.

Side surfaces of the first conductive layer 128 of the gate line 121, the storage electrode line 131, and the common signal line 400 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 degrees to about 80 degrees.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121 and the storage electrode line 131. The gate insulating layer 140 has a contact hole 148 exposing the first conductive layer 128 of the contact portion 420 of the common signal line 400. In this case, the boundary line of the contact hole 148 is positioned inside the boundary line of the first conductive layer 128 so that the contact hole 148 has a shape similar to that of the first conductive layer 128. However, the contact hole 148 may have various shapes unlike the shape of the first conductive layer 128.

A plurality of linear semiconductors 151 including hydrogenated amorphous silicon (a-Si: H) are formed on the gate insulating layer 140. The linear semiconductor 151 mainly extends in the longitudinal direction and includes a plurality of projections 154 extending toward the gate electrode 124. The linear semiconductor 151 has a wider width in the vicinity of the gate line 121 and the storage electrode line 131 and covers them widely.

A plurality of linear and island ohmic contacts 161 and 165 are formed on the semiconductor 151. The ohmic contacts 161 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus (P) are heavily doped, or may be made of silicide. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 degrees to about 80 degrees.

The upper conductive layer 178 of the plurality of data lines 171, the plurality of drain electrodes 175, and the common signal line 400 may be disposed on the ohmic contacts 161 and 165 and the gate insulating layer 140. ) Is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and is formed between a set of adjacent storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and an end portion 179 having a large area for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with respect to the gate electrode 124. Each drain electrode 175 has one end portion having a large area and the other end portion having a rod shape. The wide end portion overlaps the storage electrode line 131, and the rod-shaped end portion is partially surrounded by the source electrode 173 bent in a U shape.

The second conductive layer 178 of the common signal line 400 is connected to the first conductive layer 128 through the contact hole 148 of the gate insulating layer 140, and is almost the same shape as the first conductive layer 128. It is formed. Therefore, in the present invention, the common signal line 400 includes the first conductive layer 128 and the second conductive layer 178 connected through the contact hole 148. In the drawing, the first and second conductive layers 128 and 178 are illustrated by one line. In an embodiment of the invention,

The second conductive layer 178 of the data line 171 and the common signal line 400 may include a single layer containing molybdenum, such as pure molybdenum or molybdenum alloy, or a multi-layer layer capable of etching under the same etching conditions, for example, molybdenum. It is made of a multilayer film containing a conductive film and a conductive film containing aluminum.

The second conductive layer 178 of the data line 171, the drain electrode 175, and the common signal line 400 may also be inclined at an inclination angle of about 30 degrees to about 80 degrees with respect to the surface of the substrate 110. .

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 thereon, and lower the contact resistance therebetween. In most places, the width of the linear semiconductor 151 is smaller than the width of the data line 171. However, as described above, the width of the linear semiconductor 151 is widened at the portion where it meets the gate line 121 to smooth the profile of the surface. Prevents disconnection. The semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the exposed semiconductor 154. The passivation layer 180 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). : F, etc. can be mentioned. The passivation layer 180 may be formed by having photosensitivity among the organic insulations, and the surface of the passivation layer 180 may be flat. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 151 while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 includes a plurality of contact holes 182 exposing the end portion 179 of the data line 171, the drain electrode 175, and the second conductive layer 178 of the common signal line 400, respectively. 185 and 188 are formed, and the passivation layer 180 and the gate insulating layer 140 have a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 and the fixed end of the sustain electrode 133a. A plurality of contact holes 183a exposing a part of the sustain electrode line 131 and a plurality of contact holes 183b exposing a part of the free end of the sustain electrode 133a are formed.

The contact hole 188 may have substantially the same shape as the contact hole 148 of the gate insulating layer 140, but may have a different shape from the contact hole 148 of the gate insulating layer 140 or may be changed into various shapes.

A plurality of pixel electrodes 191, a plurality of overpasses 83, and a plurality of contact assistants 81, 82, and 88 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied has a liquid crystal between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. The direction of the liquid crystal molecules in the layer (not shown) is determined. The pixel electrode 191 and the common electrode form a capacitor (hereinafter referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the storage electrode line 131 including the storage electrodes 133a and 133b. A capacitor formed by the pixel electrode 191 and the drain electrode 175 electrically connected to the pixel electrode 191 overlapping the storage electrode line 131 is called a storage capacitor, and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor.

The contact auxiliary members 81, 82, and 88 are connected to the end portion 129 of the gate line 121, the end portion 179 of the data line 171, and the common signal line through the contact holes 181, 182, and 188, respectively. It is connected to the second conductive layer 178 of 400. The contact auxiliary members 81, 82, and 188 compensate for and protect the adhesion between the end portions 179 and 129 of the data line 171 and the gate line 121 and the external device.

The connecting leg 83 crosses the gate line 121 and exposes the exposed portion of the storage electrode line 131 and the storage electrode through contact holes 183a and 183b positioned on opposite sides with the gate line 121 interposed therebetween. 133a) is connected to the exposed end of the free end. The storage electrode lines 131 including the storage electrodes 133a and 133b may be used together with the connecting legs 83 to repair defects in the gate line 121, the data line 171, or the thin film transistor.

Next, a method of manufacturing the thin film transistor array panel shown in FIGS. 2 to 6 will be described in detail with reference to FIGS. 7 to 23.

7, 12, 16, and 20 are layout views sequentially illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 8 and 9 are lines VIII-VIII of the thin film transistor array panel of FIG. 7. And FIG. 13 and FIG. 14 are cross-sectional views of the thin film transistor array panel of FIG. 12 taken along lines XIII-XIII and XIV-XIV, and FIGS. 17 and 18 are FIGS. 16 is a cross-sectional view of the thin film transistor array panel cut along the XVII-XVII line and the XVIII-XVIII line, and FIGS. 21 and 22 illustrate the thin film transistor array panel of FIG. 20 along the XXI-XXI line and the XXII-XXII line. 10, 11, 15, 19, and 23 are cross-sectional views showing the manufacturing process sequence of the common signal line according to the manufacturing process sequence of the thin film transistor array panel.

First, as shown in FIGS. 7 to 10, the lower layer including aluminum and the upper layer including molybdenum are sequentially stacked on the insulating substrate 110 made of transparent glass or plastic, and then the lower layer and the upper layer are wet-etched ( first etching of the plurality of gate lines 121 including the gate electrode 124 and the end portion 129, the plurality of storage electrode lines 131 including the storage electrodes 133a and 133b, and the common signal line by wet etching. Form layer 128. In this case, the upper layer and the lower layer are preferably patterned in a tapered structure under one etching condition.

Next, as shown in FIG. 11, silicon nitride (SiNx) or silicon oxide (SiO ₂ ) to cover the first conductive layer 128 of the gate line 121, the sustain electrode line 131, and the common communication line 400. After the deposition, the gate insulating layer 140 is formed, and then the gate insulating layer 140 is etched by a photolithography process using a mask to form a contact hole 148 exposing the first conductive layer 128.

12 to 15, an intrinsic amorphous silicon layer and an impurity doped amorphous silicon layer are sequentially stacked on the gate insulating layer 140, and the impurities are doped. Photo-etched the amorphous silicon layer and the intrinsic amorphous silicon layer to form a linear intrinsic semiconductor layer 151 each comprising a plurality of protrusions 154 and a plurality of impurity semiconductor patterns 164 and an amorphous silicon layer doped with impurities. .

Next, as shown in FIGS. 16 to 19, the molybdenum or molybdenum alloy is laminated on the impurity doped amorphous silicon layer and the gate insulating layer 140 by sputtering or the like and etched by a photolithography process using a mask. The second conductive layer 178 of the data line 171 including the electrode 173 and the end 179, the drain electrode 175, and the common signal line 400 is formed.

Next, the exposed impurity semiconductor layer 164 that is not covered by the source electrode 173 and the drain electrode 175 is removed, and the plurality of linear ohmic contacts 161 including the plurality of protrusions 163 and the plurality of island types are formed. While completing the ohmic contact layer 165, the portion of the intrinsic semiconductor 154 beneath it is exposed. In this case, oxygen (O ₂ ) plasma is performed to stabilize the surface of the exposed intrinsic semiconductor 154.

Next, as shown in FIGS. 20 to 23, an organic insulating material or an inorganic insulating material is coated to form the passivation layer 180, and dry etching is performed by a photo process to produce a plurality of contact holes 188, 185, 183a, and 183b. , 181, 182.

Next, as shown in FIGS. 2 to 6, a transparent conductive layer such as ITO or IZO is sputtered on the passivation layer 180 and then patterned to form the pixel electrode 191 and the contact auxiliary members 81, 82, and the like. 88 and a connecting leg 83.

As described above, in the thin film transistor array panel according to the exemplary embodiment of the present invention and the manufacturing method thereof, the contact portion 420 of the common signal line 400 having the short circuit point is formed to have a double film structure without under-cut, Since the first conductive layer 128 and the insulating layers 180 and 140 support or surround the second conductive layer 178, the contact portion 420 may be prevented from being corroded by the etchant during the manufacturing process. Accordingly, the distortion of the common voltage may be minimized, thereby minimizing cross talk or flicker, thereby improving characteristics of the display device.

 Example 2

Hereinafter, a thin film transistor array panel according to another exemplary embodiment of the present invention will be described with reference to FIGS. 24 to 27.

24 is a layout view of a thin film transistor array panel according to another exemplary embodiment. FIGS. 25 and 26 are cross-sectional views of the thin film transistor array panel of FIG. 24 taken along lines XXV-XXV and XXVI-XXVI. 27 is a cross-sectional view illustrating a structure of a common signal line in a thin film transistor array panel according to another exemplary embodiment of the present invention.

The structure of the thin film transistor array panel according to the present embodiment is almost the same as that shown in FIGS. 2 to 6.

A plurality of gate lines 121 having a gate electrode 124 and an end portion 129 on the substrate 110, a plurality of storage electrode lines 131 having the storage electrodes 133a and 133b, and a common signal line 400. A first insulating layer 128, a gate insulating film 140 having a contact hole 148 exposing the first conductive layer 128 thereon, a plurality of linear semiconductors 151 including protrusions 154, A plurality of linear ohmic contacts 161 and a plurality of island-type ohmic contacts 165 having protrusions 163 are formed in this order. On the ohmic contacts 161 and 165, a plurality of data lines 171 including a source electrode 173 and an end portion 179, a plurality of drain electrodes 175, and a second conductive layer of the common signal line 400 ( 178 is formed and a passivation layer 180 is formed thereon. A plurality of contact holes 181, 182, 183a, 183b, 185, and 188 are formed in the passivation layer 180 and the gate insulating layer 140, and the plurality of pixel electrodes 191 and the plurality of contact assistants 81 are formed thereon. 82 and 88 and a plurality of connecting legs 83 are formed.

However, unlike the thin film transistor array panel illustrated in FIGS. 2 to 6, the thin film transistor array panel according to the present exemplary embodiment may include the data line 171 except for the protrusion 154 where the thin film transistor is located. The drain electrode 175 has a planar shape substantially the same as that of the ohmic contacts 161 and 165. That is, the linear semiconductor layer 151 is not exposed below the data line 171 and the drain electrode 175 and the ohmic contacts 161 and 165 below the source line 173 and the drain electrode 175. ) Has an exposed portion between them. In addition, amorphous silicon layers 158 and 168 are formed under the second conductive layer 178 in the same planar shape as the second conductive layer 178.

In the method of manufacturing a thin film transistor array panel having such a structure, the photoresist pattern is formed so as to have a different thickness between the photoresist pattern having a different thickness depending on the position, that is, the first part corresponding to the wiring and the second part corresponding to the channel. The metal layer and the amorphous silicon layer are etched together using an etching mask to form the data line, the drain electrode, and the semiconductor layer together.

As described above, there may be various methods of forming the thickness of the photoresist film differently according to the position. A semi-transparent area as well as a transparent area and a light blocking area may be formed in the exposure mask. For example. The semi-transmissive region includes a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

As described above, by forming a signal line with a lower layer of molybdenum-niobium alloy and an upper layer of copper, it is possible to compensate for contact between the upper layer and minimize residues and process errors generated during the manufacturing process, thereby improving reliability of the signal line. Can be improved.

Claims (8)

Board, A gate line formed on the substrate, A first conductive layer of a common signal line formed of the same layer as the gate line, A gate insulating layer formed on the gate line and having a first contact hole exposing the first conductive layer; A semiconductor layer formed on the gate insulating film, A data line and a drain electrode formed on the gate insulating film or the semiconductor layer and including a source electrode, and A second conductive layer of a common signal line formed of the same layer as the data line and connected to the first conductive layer through the first contact hole; and A pixel electrode connected to the drain electrode Thin film transistor array panel comprising a. The thin film transistor array panel of claim 1, further comprising a passivation layer formed between the pixel electrode and the drain electrode. The thin film transistor array panel of claim 2, further comprising: a contact auxiliary member connected to the second conductive layer through a second contact hole of the passivation layer. In claim 3, The common signal line is a thin film transistor array panel formed in a slit or grate shape. In claim 4, The first contact hole or the second contact hole is formed in a slit or grate shape along the shape of the common signal line connected to the contact auxiliary member. Forming a first conductive layer of a gate line and a common signal line on the substrate, Forming a gate insulating film having a first contact hole exposing the first conductive layer on the gate line, Forming a semiconductor layer on the gate insulating film, Forming a second conductive layer of the common signal line connected to the first conductive layer through the data line, the drain electrode, and the first contact hole on the semiconductor layer; Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor array panel comprising a. The method of claim 6, wherein the contact assistant member connected to the second conductive layer is formed on the same layer as the pixel electrode. 8. The method of claim 7, further comprising forming a passivation layer having a second contact hole connecting the second conductive layer and the contact auxiliary member between the pixel electrode and the drain electrode.

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