KR20080043515A - Liquid crystal display and driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof for improving display quality and reducing manufacturing cost.

A liquid crystal display device according to the present invention comprises: a display panel having a plurality of data lines; A first data integrated circuit having a first output channel group connected to the data line and capable of outputting data, and a first dummy channel group blocked from outputting the data; A second data integrated circuit having a second output channel group connected to the data line and capable of outputting data, and a second dummy channel group blocked from outputting the data; And a controller for sequentially supplying digital video data to the data integrated circuits and generating a first start signal and a second start signal; The first data integrated circuit starts sampling the digital video data in response to the first start signal, and the second data integrated circuit starts sampling the digital video data in response to the second start signal. It features.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

1 is a view schematically showing a conventional liquid crystal display device.

2A illustrates a gate integrated circuit included in a conventional gate driver.

2B is a diagram showing a data integrated circuit included in a conventional data driver.

3 is a waveform diagram for explaining delay of digital video data.

4 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 shows an example of a data driver that implements a specific resolution of 277 × 124. FIG.

6 is a timing diagram of a source sampling clock input to the data driver of FIG. 5;

<Description of Symbols for Main Parts of Drawings>

2,102 liquid crystal panel 4,104,204 data driver

6,106 gate driver 7: liquid crystal cell

8,108 timing controller 10 gate IC

16,116-1 to 116-k, 216-1,216-2: data IC

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving display quality and reducing manufacturing cost.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field.

To this end, the liquid crystal display device includes a liquid crystal panel 2 having liquid crystal cells arranged in a matrix form as shown in FIG. 1, and a gate driver for driving gate lines GL1 to GLn of the liquid crystal panel 2. 6), a data driver 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2, and a timing controller 8 for controlling the gate driver 6 and the data driver 4. Equipped.

The liquid crystal panel 2 includes a thin film transistor TFT formed at each intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm, and a liquid crystal cell 7 connected to the thin film transistor TFT. do. The thin film transistor TFT is turned on when the gate high voltage VGH is supplied from the gate line GL to supply the pixel signal from the data line DL to the liquid crystal cell 7. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell 7.

The liquid crystal cell 7 is equivalently represented by a liquid crystal capacitor, and includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell 7 further includes a storage capacitor so that the charged pixel signal is stably maintained until the next pixel signal is charged. The liquid crystal cell 7 realizes gradation by adjusting light transmittance by using an arrangement state of liquid crystals that vary according to pixel signals charged through the thin film transistor TFT.

The timing controller 8 uses the clock CLK and the synchronization signals Vsync and Hsync supplied from a video card (not shown) and the gate control signals GSP, GSC, and GOE and the data control signals SSP, SSC, SOE, POL). The gate control signals GSP, GSC, and GOE are supplied to the gate driver 6 to control the gate driver, and the data control signals SSP, SSC, SOE, and POL are supplied to the data driver 4 to provide data. Take control of the driver. In addition, the timing controller 8 rearranges and supplies the red (R), green (G), and blue (B) digital video data VD to the data driver 4.

The gate driver 6 sequentially drives the gate lines GL1 to GLn. For this purpose, the gate driver 6 includes a plurality of gate integrated circuits (hereinafter, referred to as "ICs") 10 as shown in FIG. 2A. The gate ICs 10 sequentially supply the gate high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE supplied from the timing controller 8.

The data driver 4 supplies the pixel signals for one line to the data lines DL1 to DLm every horizontal period. For this purpose, the data driver 4 has a plurality of data ICs 16 as shown in FIG. 2B. The data ICs 16 supply data voltages to the data lines DL1 to DLm in response to data control signals SSP, SSC, SOE, and POL supplied from the timing controller 8.

Such a conventional liquid crystal display device requires different numbers of output channels of the data IC 16 and the number of data IC 16 according to the resolution of the liquid crystal panel 2. This is because the number of data lines DL varies depending on the resolution of the liquid crystal panel 2. For example, a liquid crystal display device having an XGA (eXtended Graphics Array) resolution of the liquid crystal panel 2 has 3072 (1024 × 3) data lines (DLs), so that four data ICs having 768 data output channels are provided. (16) is required. Since the liquid crystal display device having a resolution of SXGA + (Super eXtended Graphics Adapter +) of the liquid crystal panel 2 has 4200 (1400 × 3) data lines (DL), six data ICs 16 having 702 data output channels are provided. Need. At this time, the remaining 12 output channels are treated as dummy channels.

Recently, as the range of use of liquid crystal display devices is widened, the development of unusual inches and unusual resolutions has been progressed. A typical example is a 5 inch liquid crystal display having a resolution of (277 x 124). In the liquid crystal display having such a specific resolution, the frequency of output channels not connected to the data line is treated as a dummy channel because the number of output channels of the data IC and the number of data lines of the liquid crystal display that have been developed so far are not exactly matched. high. The dummy channels not connected to the data line are mainly disposed between two data ICs.

However, in the conventional liquid crystal display device, as described above, dummy channels not connected to the data line are mainly disposed between two data ICs, resulting in loss of digital video data. That is, in the conventional liquid crystal display, when a certain number of dummy channels exist between the first data IC and the second data IC, digital video data to be sampled in the second data IC before the carry signal is generated from the first data IC. Is applied to the dummy channels, causing a problem of degrading the display quality. To solve this problem, a separate line memory is provided in the timing controller to delay digital video data by one horizontal line and supply the data IC to the data IC.

3 is a waveform diagram for explaining delay of digital video data. Two line memories are provided in the timing controller. The timing controller stores digital video data to be supplied to the first horizontal line in the first line memory as shown in FIG. The timing controller is configured to store the digital video data to be supplied to the first horizontal line stored in the first line memory when the digital video data to be supplied to the second horizontal line disposed below the first horizontal line is stored in the second line memory. To feed.

As such, when a separate line memory is provided in the timing controller and a new data enable signal is generated in synchronization with the falling edge of the data enable signal DE, loss of digital video data due to dummy channels is prevented. However, there is an economic disadvantage disadvantage in that an additional cost for using a separate memory is incurred.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of driving the same, which can reduce the manufacturing cost and improve display quality by controlling the start of sampling of data ICs by generating source start pulses individually for each data IC. To provide.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention comprises a display panel having a plurality of data lines; A first data integrated circuit having a first output channel group connected to the data line and capable of outputting data, and a first dummy channel group blocked from outputting the data; A second data integrated circuit having a second output channel group connected to the data line and capable of outputting data, and a second dummy channel group blocked from outputting the data; And a controller for sequentially supplying digital video data to the data integrated circuits and generating a first start signal and a second start signal; The first data integrated circuit starts sampling the digital video data in response to the first start signal, and the second data integrated circuit starts sampling the digital video data in response to the second start signal. It features.

The first output channel group is disposed on the left side of the first data integrated circuit, and the first dummy channel group is disposed on the right side of the first data integrated circuit.

The second output channel group is disposed on the left side of the second data integrated circuit, and the second dummy channel group is disposed on the right side of the second data integrated circuit.

According to an exemplary embodiment of the present invention, a display panel having a data line, a first data integrated circuit having a first output channel group capable of outputting data and a first dummy channel group blocked from outputting the data, and capable of outputting data A second data integrated circuit having a second output channel group and second dummy channels of which data output is blocked, and a controller for sequentially supplying digital video data to the data integrated circuits, Generating a first start signal and a second start signal in the controller; Starting sampling of the digital video data in the first data integrated circuit in response to the first start signal; And starting sampling of the digital video data in the second data integrated circuit in response to the second start signal.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 6.

4 is a schematic structural diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a liquid crystal display according to an exemplary embodiment of the present invention provides a liquid crystal panel 102 in which liquid crystal cells are arranged in a matrix and for driving gate lines GL1 to GLn of the liquid crystal panel 102. A timing controller for controlling the gate driver 106, the data driver 104 for driving the data lines DL1 to DLm of the liquid crystal panel 102, and the gate driver 106 and the data driver 104 ( 108).

The liquid crystal panel 102 includes a thin film transistor TFT formed at each intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm, and a liquid crystal cell connected to the thin film transistor TFT. It is provided. The thin film transistor TFT is turned on in response to the gate high voltage VGH from the gate line GL to supply the data voltage from the data line DL to the liquid crystal cell. The thin film transistor TFT is turned off in response to the gate low voltage VGL from the gate line GL to maintain the pixel signal charged in the liquid crystal cell.

The liquid crystal cell is equivalently replaced by a liquid crystal capacitor, and includes a common electrode facing the pixel electrode connected to the thin film transistor TFT with the liquid crystal interposed therebetween. The liquid crystal cell further includes a storage capacitor so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor may be formed between the pixel electrode and the previous gate line, and may be formed between the pixel electrode and the storage line. The liquid crystal cell implements grayscale by controlling light transmittance by changing an arrangement state of liquid crystals having dielectric anisotropy in response to pixel signals charged through thin film transistors (TFTs).

The timing controller 108 uses the control signals DE, CLK, Vsync, and Hsync supplied from a video card (not shown) to control the gate control signals GSP, GSC, and GOE and the data control signals SSP1 to SSPk, SSC, SOE, and POL). In particular, the first to kth source start pulses SSP1 to SSPk are control signals indicating the start of sampling of the digital video data VD in the first to kth data ICs 116-1 to 116-k, respectively. The gate control signals GSP, GSC, and GOE are supplied to the gate driver 106 to control the gate driver, and the data control signals SSP1 to SSPk, SSC, SOE, and POL are supplied to the data driver 104. To control the data driver. In addition, the timing controller 108 rearranges and supplies the digital video data VD supplied from the video card to the data driver 104.

The gate driver 106 sequentially drives the gate lines GL1 to GLn. The gate driver 106 is provided with a plurality of gate ICs (not shown). The gate IC sequentially supplies a scan signal to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE supplied from the timing controller 108. In detail, the gate IC sequentially shifts the gate start pulse GSP according to the gate shift clock GSC to generate a shift output signal. The gate IC converts the generated shift output signal into a scan signal having a voltage level suitable for driving the thin film transistor TFT and supplies it to the gate lines GL1 to GLn. The scan signal swings between the gate high voltage VGH, which is a voltage higher than or equal to the threshold voltage of the thin film transistor TFT, and the gate low voltage VGL, which is a voltage lower than or equal to the threshold voltage of the thin film transistor TFT.

The data driver 104 supplies the pixel signals for one line to the data lines DL1 to DLm every horizontal period. The data driver 104 is equipped with a plurality of data ICs 116-1 through 116-k. Each of the data ICs 116-1 through 116-k is mounted on a tape carrier package (hereinafter referred to as "data TCP") 110. These data ICs 116-1 to 116-k are electrically connected to the data lines DL1 to DLm via the data TCP pad 112, the data pad 114, and the link unit 118. The data ICs 116-1 through 116-k have output channel groups for this connection. Each of the data ICs 116-1 to 116-k includes dummy channels (not shown) which are redundant channels in which connection to the data lines DL1 to DLm is blocked in addition to the output channel group. This is a result of using existing data ICs instead of developing data ICs in various resolutions. These dummy channels are disposed to the right of the output channel group of each of the data ICs 116-1 to 116-k.

The data ICs 116-1 to 116-k apply data voltages to the data lines DL1 to DLm in response to the data control signals SSP1 to SSPk, SSC, SOE, and POL supplied from the timing controller 108. Supply. In detail, the first to k-th data ICs 116-1 to 116-k respectively shift the first source start pulses SSP1 to the kth source start pulse SSPk according to the source sampling clock SSC and sample the samples. Generate each signal. The first through k-th data ICs 116-1 through 116-k sequentially latch the digital video data VD in predetermined units in response to the sampling signal. Subsequently, the first through k-th data ICs 116-1 through 116-k convert the latched one horizontal line of digital video data VD into an analog data voltage to enable the source output enable signal SOE. The data lines DL1 to DLm are supplied during the period. In this case, the first to k-th data ICs 116-1 to 116-k may convert the digital video data VD into positive or negative data voltages according to the polarity control signal POL. As described above, each of the data ICs 116-1 to 116-k generates a sampling signal by using the source start pulses SSP1 to SSPk supplied independently, thereby providing the data ICs 116-1 to 116-k. This prevents the loss of digital video data due to dummy channels arranged to the right of the output channel group. In addition, each of the data ICs 116-1 to 116-k generates a sampling signal using the source start pulses SSP1 to SSPk supplied independently, thereby eliminating a separate line memory in the timing controller.

5 shows an example of a data driver that implements a specific resolution of 277 × 124.

Referring to FIG. 5, the data driver shifts the first source start pulse SSP1 to generate a sampling signal, and shifts the second source start pulse SSP2 to generate a sampling signal. The 2nd data IC 216-2 which generate | occur | produces is provided. Here, the data ICs 216-1 and 216-2 have 480 channels.

The first data IC 216-1 has 480 shift registers corresponding to the number of channels. The first data IC 216-1 sequentially shifts the first source start pulse SSP1 from the timing controller 108 according to the source sampling signal SSC using the first to 417th shift registers. Output by sampling signal. The first data IC 216-1 does not output the sampling signal through the 418 th to 480 th shift registers. Accordingly, the first data IC 216-1 has 417 output channels and 63 dummy channels.

The second data IC 216-2 includes 480 shift registers corresponding to the number of channels. The second data IC 216-2 sequentially shifts and samples the second source start pulse SSP2 from the timing controller 108 according to the source sampling signal SSC using the first to 414th shift registers. Output as a signal. The second data IC 216-2 does not output the sampling signal through the 415 th to 480 th shift registers. Accordingly, the second data IC 216-2 has 414 output channels and 66 dummy channels.

6 is a diagram illustrating a timing at which a source sampling clock is input to the data driver of FIG. 5. The illustrated VD is RGB data input in parallel. For example, D1 represents three data of the same gradation.

The timing controller 108 inputs RGB data per one source sampling clock SSC to each data IC 216-1 and 216-2 in parallel. As described with reference to FIG. 5, the first data IC 216-1 has 417 output channels and 63 dummy channels. Accordingly, the timing controller 108 supplies the first source start pulse SSP1 to the first data IC 216-1, and from this time, 139 {(480-63) / 3} source sampling clocks SSCs are supplied. The first to 139th digital video data D1 to D139 are supplied to the first data IC 216-1 during the generated period. Subsequently, the timing controller 108 sets the timing of supply of the first source start pulse SSP1 to the start point to block supply of the digital video data after the 140th time to the dummy channels of the first data IC 216-1. As soon as the 140 th source sampling clock SSC is generated, the second source start pulse SSP2 is supplied to the second data IC 216-2.

The first data IC 216-1 sequentially shifts the first source start pulse SSP1 from the timing controller 108 in accordance with the source sampling signal SSC, so that the first to 139th digital video data D1 to D139. Sampling).

The second data IC 216-2 sequentially shifts the second source start pulse SSP2 from the timing controller 108 in accordance with the source sampling signal SSC to convert the 140 th to 277th digital video data D140 to D277. Sampling).

As described above, the liquid crystal display device and the driving method thereof according to the present invention generate source start pulses individually for each data IC to control sampling start of the data ICs, thereby preventing loss of data by the dummy channel, thereby improving display quality. Can be improved.

Furthermore, the liquid crystal display and the driving method thereof according to the present invention generate a source start pulse for each data IC individually and control the start of sampling of the data ICs, thereby eliminating a separate memory included in the timing controller, thereby reducing manufacturing costs. Can be saved.

 Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A display panel having a plurality of data lines; A first data integrated circuit having a first output channel group connected to the data line and capable of outputting data, and a first dummy channel group blocked from outputting the data; A second data integrated circuit having a second output channel group connected to the data line and capable of outputting data, and a second dummy channel group blocked from outputting the data; And A controller for sequentially supplying digital video data to said data integrated circuits and for generating a first start signal and a second start signal; The first data integrated circuit starts sampling the digital video data in response to the first start signal, and the second data integrated circuit starts sampling the digital video data in response to the second start signal. A liquid crystal display device. The method of claim 1, And the first output channel group is disposed on the left side of the first data integrated circuit, and the first dummy channel group is disposed on the right side of the first data integrated circuit. The method of claim 1, And the second output channel group is disposed on the left side of the second data integrated circuit, and the second dummy channel group is disposed on the right side of the second data integrated circuit. A display panel having a plurality of data lines, a first data integrated circuit having a first output channel group capable of outputting data and a first dummy channel group blocked from outputting the data, and a second output channel group capable of outputting data And a second data integrated circuit having second dummy channels of which data output is cut off, and a controller for sequentially supplying digital video data to the data integrated circuits. Generating a first start signal and a second start signal in the controller; Starting sampling of the digital video data in the first data integrated circuit in response to the first start signal; And And starting the sampling of the digital video data in the second data integrated circuit in response to the second start signal.

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