KR20080040117A - Manufacturing method of display board - Google Patents

Abstract

Disclosed is a method of manufacturing a display substrate for reducing defects due to metal precipitation. A method of manufacturing a display substrate in which a plurality of unit pixels are defined by gate lines and data lines that are insulated from each other and intersect with each other, and each unit pixel includes a first circuit including gate lines and storage lines on the substrate. Forming a metal pattern, forming a gate insulating layer on the substrate on which the first metal pattern is formed, forming an active layer of the switching element on the gate insulating layer, and forming a gate insulating layer on the active insulating layer Forming a patterned first electrode corresponding to the unit pixel at the second pixel, forming a second metal pattern including data lines on the substrate on which the first electrode is formed, and passivating the substrate on which the second metal pattern is formed Forming a layer and forming a second electrode on the passivation layer corresponding to the unit pixel. As a result, it is possible to prevent the metal precipitation phenomenon occurring in the manufacturing process of the conventional FFF MODE display substrate in which the first electrode, which is the common electrode, is formed under the gate insulating layer.

Description

Manufacturing method of display substrate {METHOD FOR MANUFACTURING DISPLAY SUBSTRATE}

1 is a plan view of a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 to 9 are process diagrams illustrating a method of manufacturing a display substrate according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: display substrate 200: opposing substrate

300: liquid crystal layer 110: base substrate

120: gate insulating layer 151: first electrode

160: passivation layer 170: second electrode

171: first line 172: second line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a display substrate, and more particularly, to a method of manufacturing a display substrate applied to a liquid crystal display panel in a lateral field switching mode.

In general, a transverse electric field type liquid crystal display panel is composed of a display substrate, an opposing substrate, and a liquid crystal layer interposed between the display substrate and the opposing substrate, and the display substrate includes a plurality of liquid crystal layers intersecting each other. Unit pixels are defined.

 In the unit pixel, a thin film transistor, a common electrode, and a pixel electrode are formed. The thin film transistor includes a gate electrode, a first insulating layer formed on the gate electrode, an active layer overlapping the gate electrode on the first insulating layer, and a source electrode and a drain electrode formed to partially overlap the active layer on the active layer. A second insulating film is formed on the thin film transistor, and the pixel electrode is formed on the second insulating film corresponding to the unit pixel. The common electrode is formed on the same layer as the gate electrode corresponding to the unit pixel, and the pixel electrode is connected to the first line and the first line parallel to the data line to form a transverse electric field therebetween. It is patterned to include a plurality of parallel second lines.

On the other hand, the common electrode is formed of a transparent conductive material such as indium tin oxide to improve the aperture ratio of the unit pixel.

In this case, when the common electrode is formed of a transparent conductive material such as indium tin oxide, a metal component may be precipitated from the common electrode by a high temperature deposition process for forming the first insulating layer and the active layer. The metal component deposited from the common electrode rapidly reduces the transmittance and display characteristics of the liquid crystal display panel.

In order to suppress this, when the deposition process for forming the first insulating film and the active layer is carried out at a low temperature, the film quality of the first insulating film and the active layer may be changed to reduce the reliability of the liquid crystal display panel and cause various defects such as an afterimage defect. There is a problem.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a method of manufacturing a display substrate for reducing defects.

In order to achieve the above object of the present invention, in accordance with an embodiment, a plurality of unit pixels are defined by gate lines and data lines that are insulated and intersected with each other, and each unit pixel has a switching element formed therein. Forming a first metal pattern on the substrate, the first metal pattern including the gate wirings and the storage wirings; forming a gate insulating layer on the substrate on which the first metal pattern is formed; Forming an active layer of the switching element, forming a first electrode patterned corresponding to the unit pixel on the gate insulating layer on which the active layer is formed, and forming the data on a substrate on which the first electrode is formed Forming a second metal pattern including wirings, and forming a passivation layer on the substrate on which the second metal pattern is formed And forming a second electrode on the system and the passivation layer corresponding to the unit pixel.

According to the method of manufacturing the display substrate, it is possible to prevent the metal precipitation phenomenon occurring at the common electrode when the gate insulation layer is formed in the conventional transverse electric field structure display substrate in which the common electrode is formed below the gate insulation layer.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view of a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along lines II ′ and II-II ′ of FIG. 1.

1 and 2, the liquid crystal display panel 400 includes an opposing substrate 200 and a liquid crystal layer 300 interposed between the display substrate 100 and the opposing substrate 200.

 The display substrate 100 includes a base substrate 110. The base substrate 110 is made of a transparent material through which light can pass. In one example, the base substrate 110 is a glass substrate. Gate lines GL extending in the first direction X and data lines DL extending in the second direction Y crossing the first direction X are formed on the base substrate 110. A plurality of unit pixels P is defined.

A thin film transistor TFT connected to the gate line GL and the data line DL, a storage line STL extending in the same direction as the gate lines GL, and a first electrode in the unit pixel P 150 and the second electrode 170 are formed.

In detail, the gate lines GL and the storage line STL are first metal patterns formed by patterning the same metal layer. In addition, the first metal pattern includes a gate electrode G protruding from the gate line GL.

A gate insulating layer 120 is formed on the base substrate 110 on which the first metal pattern including the gate lines GL, the gate electrode G, and the storage line STL is formed. For example, the gate insulating layer 120 is formed of silicon nitride (SiNx), and the first insulating hole H1 exposes the storage wiring STL in the unit pixel P in the gate insulating layer 120. Is formed. In addition, a second hole H2 exposing one end of the gate line GL and a third hole H3 exposing one end of the storage line STL are also formed. One end of the gate line GL and the storage line STL is an area in which the gate pad part GP and the storage pad part STP are formed to electrically contact an external driving chip.

The active layer A overlapping the gate electrode G is formed on the gate insulating layer 120. For example, the active layer A has a structure in which a semiconductor layer 131 made of amorphous silicon and an ohmic contact layer 132 made of n + ion-doped amorphous silicon are sequentially stacked.

The data lines DL, the source electrode S, and the drain electrode D are formed on the gate insulating layer on which the active layer A is formed. The data lines DL, the source electrode S, and the drain electrode D are second metal patterns formed by patterning the same metal layer.

The source electrode S protrudes from the data line DL and partially overlaps the active layer A. The drain electrode D is formed spaced apart from the source electrode S by a predetermined interval and partially overlaps the active layer A.

In this case, the ohmic contact layer 132 is removed from the source electrode S and the drain electrode D to expose the semiconductor layer 131. The region where the semiconductor layer 131 is exposed is a region where an electrical channel of the thin film transistor TFT is formed.

The gate electrode G, the active layer A, the source electrode S, and the drain electrode D constitute the thin film transistor TFT in the unit pixel P.

The second metal pattern may further include a cover electrode CE formed on the second hole H2 and the third hole H3.

The first electrode 150 patterned to correspond to the unit pixel P is formed on the base substrate 110 on which the second metal pattern is formed.

For example, the first electrode 150 is made of a transparent conductive material. As the transparent conductive material, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like may be used.

The first electrode 150 is in electrical contact with the storage electrode STL through the first hole H1 formed in the gate insulating layer 120. That is, the first electrode 150 is a common electrode to which a common voltage is applied from the storage line STL.

The passivation layer 160 is formed on the base substrate 110 on which the first electrode 150 is formed. The passivation layer 160 may be formed of, for example, silicon nitride, silicon oxide, or the like. In the passivation layer 160, a contact hole 161 exposing one end of the drain electrode D is formed. In addition, the passivation layer 160 has a fourth hole H4 corresponding to the second hole H2, a fifth hole H5 corresponding to the third hole H3, and the data line DL. The sixth hole H6 exposing one end of the hole is formed.

Accordingly, at one end of the gate line GL, the data line DL, and the storage common line STL, a gate pad GP, a data pad DP, and a storage pad STP are connected to the driving IC. Each is formed.

The second electrode 170 is formed on the passivation layer 160 to correspond to the unit pixel P. For example, the second electrode 170 is made of a transparent conductive material. Indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like may be used as the transparent conductive material.

The second electrode 170 is electrically connected to the drain electrode D through the contact hole 161 and receives a pixel voltage provided from the data line DL.

In this case, the second electrode 170 is connected to the first line 171 and the first line 171 extending in the same direction as the data line DL and extends in the same direction as the gate line GL. A plurality of second lines 172.

Since different voltages are applied to the first electrode 150 and the second electrode 170, an electric field of a transverse electric field is formed between the plurality of second lines 172 and the first electrode 150. The liquid crystal molecules of the liquid crystal layer 300 are rearranged by the electric field.

Accordingly, light provided from the rear surface of the liquid crystal display panel 400 is transmitted to display an image on the counter substrate 200.

Hereinafter, a method of manufacturing a display substrate according to an exemplary embodiment of the present invention will be described.

3 to 9 are process diagrams illustrating a method of manufacturing the display substrate illustrated in FIG. 2.

1 and 3, a first metal layer (not shown) is formed on the base substrate 110. The first metal layer may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, or the like, and is deposited by a sputtering process. In addition, the first metal layer may be formed of two or more layers having different physical properties.

Subsequently, the first metal layer is patterned by a photo-etching process using a first exposure mask to form a first metal pattern including gate lines GL, a gate electrode G, and a storage line STL.

The gate lines GL extend in the first direction X on the base substrate 110. The gate electrode G is formed to protrude from the gate line GL. The storage line STL extends in the first direction X between the gate lines GL.

An etching process of forming the first metal pattern is, for example, a wet etching process.

Referring to FIG. 4, the gate insulating layer 120 is formed on the base substrate 110 on which the first metal pattern is formed by using a chemical vapor deposition method. For example, the gate insulating layer 120 may be formed of silicon nitride or silicon oxide. In addition, the gate insulating layer 120 may be formed in a double layer structure having different materials and forming processes.

Subsequently, the semiconductor layer 131 and the ohmic contact layer 132 are sequentially formed on the gate insulating layer 120 using the chemical vapor deposition method.

The semiconductor layer 131 is made of, for example, amorphous silicon, and the ohmic contact layer is made of, for example, amorphous silicon doped with a high concentration of n-type ions.

Next, the ohmic contact layer 132 and the semiconductor layer 131 are simultaneously patterned by a photo-etching process using a second exposure mask to form an active layer A overlapping the gate electrode G. FIG.

1 and 5, the first hole exposing the storage common wiring STL formed in the unit pixel P by patterning the gate insulating layer 120 by a photo-etching process using a third exposure mask. (H1), a second hole H2 exposing one end of the gate line GL, and a third hole H3 exposing one end of the storage common line STL.

1 and 6, a conductive material layer (not shown) is formed on the gate insulating layer on which the first, second, and third holes H1, H2, and H3 are formed. The conductive material layer may be formed of, for example, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like, which is a transparent conductive material, and is deposited by a sputtering method. Alternatively, the conductive material layer may be made of metal.

Subsequently, the conductive material layer is patterned by a photo-etching process using a fourth exposure mask to form a first electrode 150 corresponding to the unit pixel P.

The first electrode 150 contacts the storage common wiring STL through the first hole H1.

1 and 7, a second metal layer (not shown) is formed on the base substrate 110 on which the first electrode 150 is formed. The second metal layer may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, an alloy thereof, or the like, and is deposited by a sputtering process. In addition, the second metal layer may be formed of two or more layers having different physical properties.

Subsequently, the second metal layer is patterned by a photo-etching process using a fifth exposure mask to form a second metal pattern including the data line DL, the source electrode S, and the drain electrode D. FIG.

The data line DL extends in a second direction Y that crosses the first direction X. FIG. Accordingly, the unit pixels P having a matrix shape are defined by the gate lines GL and the data lines DL on the base substrate 110.

The source electrode S protrudes from the data line DL and partially overlaps the active layer A. The drain electrode D is formed spaced apart from the source electrode S by a predetermined interval and partially overlaps the active layer A.

The second metal pattern may further include a cover electrode CE formed to correspond to the second hole H2 and the third hole H3.

Next, the ohmic contact layer 132 exposed at the spaced portion between the source electrode S and the drain electrode D is etched to expose the semiconductor layer 131.

Accordingly, the thin film transistor TFT including the gate electrode G, the source electrode S, the drain electrode D, and the active layer A is formed in the unit pixel P.

 1 and 8, the passivation layer 160 is formed on the base substrate 110 on which the thin film transistor TFT is formed. The passivation layer 160 may be formed by, for example, a chemical vapor deposition method, and may be formed of silicon nitride or silicon oxide.

Subsequently, the passivation layer 160 may be patterned by a photo-etching process using a sixth exposure mask to expose one end of the drain electrode D, and the second hole H2 may correspond to the second hole H2. The sixth hole H6 exposing the fourth hole H4, the fifth hole H5 corresponding to the third hole H3, and one end of the data line DL is formed.

Accordingly, one end of the data line DL, the gate line GL, and the storage common line STL may include a data pad DP, a gate pad GP, and a storage pad for connecting the wirings to the driving IC. (STP) are each formed.

1 and 9, a transparent electrode layer (not shown) is formed on the passivation layer 160 where the contact hole 161, the third hole H3, the fourth hole, and the fifth hole are formed. The transparent electrode layer may be formed of, for example, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like, and may be formed by a sputtering method.

Next, the transparent electrode layer is patterned by a photo-etching process using a seventh exposure mask to form a second electrode 170 corresponding to the unit pixel P. In detail, the second electrode 170 is connected to the first line 171 and the first line 171 patterned to extend in the same direction as the data line DL in the unit pixel P. The plurality of second lines 172 extend in the same direction as the gate line GL.

As a result, the display substrate 100 according to the exemplary embodiment of the present invention is completed.

According to the method of manufacturing the display substrate according to the exemplary embodiment of the present invention, the first electrode 150, which is a common electrode, is formed after the active layer A and the gate insulating layer 120 formed by the high temperature deposition process are formed. Form. Accordingly, it is possible to prevent the metal precipitation phenomenon occurring in the conventional manufacturing process of the display substrate in which the first electrode 150, which is the common electrode, is formed under the active layer A and the gate insulating layer 120.

Therefore, the reduction of the aperture ratio of the liquid crystal display panel due to the metal precipitation can be suppressed and the defect of the liquid crystal display panel can be reduced.

In addition, when the first electrode 150 is formed after the second metal pattern is formed, the second metal pattern is prevented from being etched up to the second metal pattern during the wet etching process of patterning the first electrode 150. A cover electrode made of the same material as the first electrode 150 should be further formed on the cover electrode. However, in the exemplary embodiment of the present invention, since the first electrode 150 is formed before forming the second metal pattern, the etching of the second metal pattern which may occur during the wet etching process of patterning the first electrode 150 is performed. It can prevent.

As described above, according to the present invention, since the first electrode, which is a common electrode, is formed after the active layer and the gate insulating layer formed by the high temperature deposition process are formed, the first electrode is formed by the active layer and the gate insulating layer. The metal precipitation phenomenon which occurs in the manufacturing process of the conventional display substrate which was formed in the lower part can be prevented. As a result, defects in the display substrate and reduction of the aperture ratio due to metal precipitation can be suppressed.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (7)

In the method of manufacturing a display substrate in which a plurality of unit pixels are defined by gate lines and data lines that are insulated from each other and cross each other, and each unit pixel has a switching element. Forming a first metal pattern on the substrate, the first metal pattern including the gate lines and the storage lines; Forming a gate insulating layer on the substrate on which the first metal pattern is formed; Forming an active layer of the switching element on the gate insulating layer; Forming a patterned first electrode on the gate insulating layer on which the active layer is formed, corresponding to the unit pixel; Forming a second metal pattern including the data lines on the substrate on which the first electrode is formed; Forming a passivation layer on the substrate on which the second metal pattern is formed; And Forming a second electrode on the passivation layer corresponding to the unit pixel. The display substrate of claim 1, further comprising patterning the gate insulation layer to form a first hole exposing the storage common line and a second hole exposing one end of the gate line. Manufacturing method. The method of claim 2, wherein the first electrode is in contact with the storage common wiring through the first hole. The method of claim 2, wherein the second metal pattern further comprises a cover electrode covering the second hole. The method of claim 2, further comprising: forming a third hole corresponding to the second hole, a fourth hole exposing one end of the data line, and a contact hole exposing the drain electrode of the switching element by patterning the passivation layer. The method of manufacturing a display substrate further comprising. The display device of claim 1, wherein the second electrode is patterned to include a first line extending in the same direction as the data line and a plurality of second lines connected to the first line and extending in the same direction as the gate line. The manufacturing method of the display substrate characterized by the above-mentioned. The method of claim 1, wherein the first electrode is formed of a transparent electrode layer that transmits light.

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