KR20080039702A - System-on-Chip and Test Method - Google Patents

Abstract

The present invention relates to a system on chip and a system on chip test method. System on a chip according to the invention has a plurality of functional blocks, a plurality of mode pins; A plurality of data pins; A mode determination unit determining whether a test mode corresponds to a predetermined test mode by a combination of input signals input to the mode pins; And a test data switching unit configured to receive test data input from the data pin and transmit the test data to the functional block corresponding to the test mode. As a result, the test time of the system-on-chip can be shortened.

Description

System-on-chip and its test method {SYSTEM-ON-A CHIP AND TEST METHOD THEREOF}

1 is a block diagram schematically showing the configuration of a conventional system-on-chip;

2 is a block diagram schematically showing the configuration of a system on a chip according to the present invention;

3 is a flowchart of a test method of a system on a chip according to the present invention.

* Explanation of symbols for the main parts of the drawings

100: image processing apparatus 110: processor core portion

120: internal memory 123: special function register (SFR)

130: mode determination unit 140: test data switching unit

The present invention relates to a system-on-chip and a test method thereof, and more particularly, to a system-on-chip and a test method that can reduce the test time.

With the development of semiconductor processing technology, the number of circuit elements that can fit in a single chip has been greatly increased as compared with the related art. As a result, individual functional blocks such as a memory, a microprocessor, a core processor, and the like, which existed as each separate chip, can be integrated into one chip. As such, a chip composed of a plurality of functional blocks is called a System on a Chip (SoC).

As shown in FIG. 1, the conventional system-on-chip 1 includes a processor core 10, an internal memory 20, a plurality of functional blocks 30 and 40, and a pad 50 including a plurality of pins. Have

In order to test the system-on-chip (1), the designer of the system-on-chip (1) not only checks whether the system-on-chip (1) is operating normally during the design process but also checks the system-on-chip (1) by ATE (Automatic Test Equipment, 3). Complete a test vector and test plan for testing with.

On the other hand, each of the logic (33, 43) of the functional block (30, 40) of the system-on-chip 1 applies a predetermined signal through the pad 50 in the ATE (3) and each functional block 30, It is tested for defects by checking whether the output signal for it in 40) falls within the tolerance range. In order to test whether the function blocks 30 and 40 operate normally, a test including a special function register (SFR) 23 of the internal memory unit 20, a system environment setting and a start / end condition, etc. You must write a vector. In this case, the processor core unit 10 sets the SFR 23 of the internal memory unit 20 and sets the system environment for the functional test of each function convex 30 or 40.

However, when the number of functional blocks to be tested or the number of SFRs to be set for the test of the functional blocks is large, it takes a lot of time to write a test vector. In addition, the processor core unit 10 that processes the load is a lot of time is required to test the system-on-chip (1).

It is therefore an object of the present invention to provide a system-on-chip and a test method thereof that can shorten the test time.

The object is a System on Chip (SoC) having a plurality of functional blocks, comprising: a plurality of mode pins; A plurality of data pins; A mode determination unit determining whether a test mode corresponds to a predetermined test mode by a combination of input signals input to the mode pins; And a test data switching unit for receiving test data input from the data pin and transmitting the test data to the functional block corresponding to the test mode.

The function block may further include a multiplexer for setting a special function register (SFR) with the test data transmitted from the test data switching unit when the test block corresponds to the predetermined test mode. .

In addition, in accordance with the present invention, in the method of testing a System on Chip (SoC) having a plurality of mode pins, a plurality of data pins, a special function register (SFR) and a plurality of functional blocks, (a Determining whether the special function register setting corresponds to a test mode required by the combination of input signals input to the mode pin; (b) receiving predetermined test data input from said data pin; and (c) transmitting the received test data to the functional block corresponding to the test mode.

In addition, the method may include temporarily storing the transmitted test data.

The method may further include setting the special function register SFR with the temporarily stored test data.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the system on a chip 100 according to the present invention.

The system-on-chip 100 may include a processor core unit 110, an internal memory unit 120, a mode determination unit 130, a test data switching unit 140, and a plurality of functional blocks 150 and 160 sharing a bus. Include.

If the value of the test mode pin is "1", the mode determination unit 130 determines that the test mode is a normal mode. If necessary, if the test mode pins are reversed, the test mode and the normal mode may be determined. In the test mode, a signal input to four mode pins of the OM [3: 0] is combined to determine which of the 32 individual test modes is stored. In addition, it is determined whether the test mode requires the SFR setting among 32 individual test modes. In particular, in the case of a functional test for testing whether each functional block operates properly, it is required to set a predetermined SFR 123 to appropriate test data. Accordingly, when it is determined that the function plate end 130 is a function test requiring SFR setting, the mode plate end 130 outputs the information of the function blocks 150 and 160 to be the target of the function test to the test data switching unit 140 to be described later. .

If the number of individual test modes is large, the number of modes that can be determined by the mode determination unit 130 may be increased by adding one more OM [4] pin.

The test data switching unit 140 receives the test result from the mode determining unit 130 and predetermined test data from the data pins 31 and 0. Therefore, the test function block information, which is the target of the functional test requiring the SFR setting, is input from the mode determination unit 130 and the data pins [31: 0] to the temporary storage units 157 and 167 of the corresponding function blocks 150 and 160. Pass the test data entered with].

The plurality of function blocks 150 and 160 have circuit logic for performing their respective functions within the system-on-chip 100. For example, the first functional block 150 may include pulse width modulation (PWM) logic (not shown). For convenience, although only two functional blocks are shown in FIG. 2, it may be further added as necessary.

Each of the plurality of functional blocks 150 and 160 has a bus interface 153 and 163, a multiplexer 155 and 165, and a temporary storage unit 157 and 167 connected to the processor core unit 110 by a bus.

The temporary storage units 157 and 167 are configured of a plurality of flip-flop elements to temporarily store test data transmitted from the test data switching unit 140.

The multiplexers 155 and 165 are test data stored in the temporary storage units 157 and 167 using the input of the test mode pin of the mode determination unit 130 as a control signal. 123). This can include special function register (SFR) address decoders as needed. That is, when the value of the test mode pin is "1" and the test mode of the system on chip 100 is set, the predetermined special function registers 123 and SFR are set as test data stored in the temporary storage units 157 and 167. In addition, when the test mode pin has a value of "0" and is in a normal mode, the processor core unit 110 may access the internal memory 140.

Accordingly, in the test mode, when setting the special function register (SFR, 123), it is possible to directly set the SFR without passing through the processor core unit 110, thereby reducing the test time.

Hereinafter, an operation process related to the test of the system on chip 100 according to the present invention will be briefly described.

For the functional test of the PWM logic of the first functional block 150, an SFR setting such as a high cycle value (or a low cycle value), a prescale value, and an enable is required. The ATE (not shown) applies a signal corresponding to the PWM logic function test mode to the test mode pin and the OM [3: 0] pin of the system-on-chip 100. In addition, a signal corresponding to the test data required for SFR setting is applied to the data pins [31: 0] in the functional test mode of the PWM logic. Then, the ROM program necessary for the test is loaded into the internal memory 120 to perform a functional test of the PWM logic.

The test time for the SFR setting is conventionally created by writing test vectors in software and processing them in the processor core unit 110. However, according to the system-on-chip 100 of the present invention, it is possible to physically set the SFR by applying a predetermined signal to the test mode pin, the OM [3: 0] pin, and the data pin [31: 0]. It can shorten.

The test method of the system on a chip 100 according to the present invention is based on the order shown in FIG.

It is determined whether the test mode is a test mode from the signal input to the test mode pin (S10). If it is determined that the test mode, it is determined whether or not the test mode requires the SFR setting (S20). In particular, the SFR setting is necessary for the functional testing of the functional blocks. If it is determined that the test mode requires the SFR setting, the test data is received from the data pins [31: 0] (S30). The received test data is transmitted to a function block that is a test target of the test mode (S40). The function block temporarily stores the transmitted test data (S50). The special function register is set by storing the temporarily stored test data in a predetermined special function register (SFR) necessary for the test of the test mode (S60). Then, the test is performed (S60).

As described above, the system-on-chip and the test method thereof according to the present invention have the following effects.

First, the SFR settings required for the test can be physically processed, which reduces test vector creation time and overall test time.

Second, since the SFR setting is possible even without the processor core part being intervened, the processor core part can be prevented from being overloaded, and the overall test time can be shortened by reducing the time consumed by passing through the processor core part.

Claims (5)

In a System on Chip (SoC) having a plurality of functional blocks, A plurality of mode pins; A plurality of data pins; A mode determination unit determining whether a test mode corresponds to a predetermined test mode by a combination of input signals input to the mode pins; And a test data switching unit configured to receive test data input from the data pin and transmit the test data to the functional block corresponding to the test mode. The method of claim 1, The function block may further include a multiplexer for setting a predetermined special function register (SFR) with the test data transmitted from the test data switching unit when the test mode corresponds to the predetermined test mode. System-on-chip. In the test method of a System on Chip (SoC) having a plurality of mode pins, a plurality of data pins, a special function register (SFR) and a plurality of functional blocks, (a) determining whether the special function register setting corresponds to a required test mode by a combination of input signals input to the mode pins; (b) receiving predetermined test data input from said data pin; (c) transmitting the received test data to the functional block corresponding to the test mode. The method of claim 3, And temporarily storing the transmitted test data. The method of claim 4, wherein Setting the special function register (SFR) with the temporarily stored test data.

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