KR20080036463A - Semiconductor memory device and test system thereof - Google Patents

Abstract

The test system of the semiconductor memory device of the present invention generates a boosted voltage internally by receiving an external power supply voltage, and receives a reference voltage from the outside to compare the level of the boosted voltage and the reference voltage to output a comparison result output signal. And test equipment for generating a reference voltage and receiving an output signal as a result of the comparison to monitor whether an excessive test voltage is applied in a package test process of the semiconductor memory device, and the semiconductor memory device of the present invention applies an external power supply voltage. A booster voltage generator for generating a boost voltage required internally, a mode setting unit for generating a test mode setting signal for deciding whether to perform a test mode operation after receiving and decoding a mode setting signal from the outside, and a positive input terminal The negative mouth It characterized in that the receiving application via an input pin a reference voltage to the terminal compares a voltage level having a comparator for outputting a comparison result through the output pin of the output signal. Therefore, according to the present invention, it is possible to prevent the latch-up phenomenon due to excessive stress and rapid overcurrent during burn-in test, and to stably reduce the boost voltage distribution to accurately analyze and recover the test failure early. have.

Description

Semiconductor memory device and test system of semiconductor device

1 is a schematic circuit diagram of a test system for directly monitoring a boosted voltage of a conventional semiconductor memory device.

2 is a schematic circuit diagram of a test system for monitoring a boosted voltage in comparison with a reference voltage at a package level of a semiconductor memory device according to a first embodiment of the present invention.

3 is a schematic circuit diagram of a test system for monitoring a boosted voltage in comparison with a reference voltage at a package level of a semiconductor memory device according to a second embodiment of the present invention.

4 is a schematic circuit diagram of a test system for self-adjusting a boosted voltage level at a package level of a semiconductor memory device compared to a reference voltage according to a third embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of a test system for self-adjusting a boosted voltage in comparison with a reference voltage at a package level of a semiconductor memory device according to a fourth embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a test system for monitoring a level of a boosted voltage during a burn-in test in a package state to determine whether bad chips are caused by excessive stress. It is about.

Generally, a test of a semiconductor memory device may be classified into a wafer test performed in a wafer state before assembly and a package test performed in a package state after the assembly process. The wafer test is further divided into a pre-laser test before the laser repair process and an electronic die sorting (EDS) test after the laser repair.

The semiconductor memory device converted into a package form undergoes a burn-in test after performing a DC test to determine whether there is an abnormality in an assembly process.

 That is, assembling the good chips selected by the wafer test into a package, and screening the defective chips in which the defects occur during the assembly process by using an automatic test equipment (ATE) for the assembled semiconductor memory device, and the semiconductor memory In order to detect early defects in the device, burn-in tests are performed on the entire semiconductor memory device by stressing the voltage and the ambient temperature to more severe conditions than actual use conditions.

In the above process, a certain number of samples are extracted from the semiconductor memory device Lot (unit of the silicon wafer to be processed in batches) selected as a good product, and the use conditions are further severed to confirm long-term reliability. In this way, a lot determined to be a problem is judged to be defective, and the whole semiconductor memory device of the target lot becomes a defective product, and only a lot that turns out to be a problem is shipped as a product.

In order to verify the reliability of the package, a plurality of packaged semiconductor memory devices are set in sockets on a burn-in board, and the entire board is kept in a monitoring burn-in test system for a predetermined time. The test for verifying the reliability of the semiconductor memory device function by applying an extreme environment, that is, an electrical signal and heat to each semiconductor memory device, is referred to as an "MBT test".

However, even when there is no EDS split when the MBT test is completed, there is a case in which the yield variation varies by lot, and the defective chips after the MBT test are caused by normal burn-in stress or excessive voltage It is often controversial whether it is an overkill phenomenon caused by over stress. However, current analytical methods do not have a way to confirm this, which often leads to burn-in degradation under the assumption that normal stress is applied to the failed chip. The situation is going on burn-in.

1 is a schematic circuit diagram of a test system for directly monitoring a boosted voltage of a conventional semiconductor memory device, and includes a semiconductor memory device 10 and an automatic test equipment 20. The semiconductor memory device 10 includes a boosted voltage generator 11, a mode setting unit 12, an inverter INV, a transfer gate 13, a power supply voltage pin 10-1, an address pin 10-2, and a voltage booster. The voltage output pin 10-3 is provided, and the transfer gate 13 is composed of one PMOS transistor P1 and one NMOS transistor N1. The boosted voltage output pin 10-3 is a pin that does not play a large role in normal operation. In the present embodiment, the data mask DM pin is exemplified.

In FIG. 1, the source and bulk of the PMOS transistor P1 in the transfer gate 13 and the drain of the NMOS transistor N1 are connected to each other so that a boosted voltage VPP is applied, and the drain of the PMOS transistor P1 and the NMOS transistor N1 are connected to each other. Source is connected and connected to the boosted voltage output pin 10-3. The test mode setting signal / TMRS inverted by the inverter INV is applied to the gate of the PMOS transistor P1 as a control signal, and the test mode setting signal TMRS is applied as a control signal to the gate of the NMOS transistor N1. do.

The function of each block of the test system for directly monitoring the boost voltage in the conventional semiconductor memory device illustrated in FIG. 1 will be described below.

The boosted voltage generator 11 receives the external power supply voltage VDD through the power supply voltage pin 10-1 and is higher than the external power supply voltage VDD to compensate for the threshold voltage loss of the transistor in the semiconductor memory device 10. Generate a boosted voltage VPP.

The mode setting unit 12 receives the mode setting signal applied through the address pin 10-2 and decodes in response to the internal clock signal to generate the test mode setting signal TMRS.

The transfer gate 13 receives the boosted voltage VPP and performs a switching operation under the control of the test mode setting signal TMRS to transfer to the boosted voltage output pin 10-3.

The automatic test equipment 20 handles the package so that the semiconductor memory devices can be automatically tested and provides a required temperature environment when a special temperature is required according to the purpose of the test item.

Referring to the operation of the test system for directly monitoring the boosted voltage inside the conventional semiconductor memory device shown in FIG.

In order to enter the burn-in test mode, the boosted voltage generator 11 receives the external power supply voltage VDD to boost the voltage above a predetermined voltage level.

If the test mode setting signal TMRS applied to the gates of the PMOS transistor P1 and the NMOS transistor N1 in the transfer gate 13 is at a high level, both the PMOS transistor P1 and the NMOS transistor N1 are turned on. When the boosted voltage VPP is turned on and is applied to the boosted voltage output pin 10-3, and the test mode setting signal TMRS is at a low level, both the PMOS transistor P1 and the NMOS transistor N1 are turned on. The boosted voltage VPP that is turned off is not transmitted to the boosted voltage output pin 10-3.

The automatic test equipment 20 continuously measures and monitors the voltage level of the boosted voltage VPP delivered through the boosted voltage output pin 10-3 to prevent excessive stress voltage from being applied through the external power supply voltage VDD. At the same time, it provides the high temperature environment required for the purpose of burn-in test items.

However, in the case where the boost voltage is used as the bulk voltage of the PMOS transistor P1 in the transfer gate 13, during power-up of applying an external power supply voltage VDD to operate the semiconductor memory device 10. The bulk voltage becomes lower than the external power supply voltage VDD applied to the boosted voltage output pin 10-3 so that a leakage current occurs from the drain side of the PMOS transistor P1 to the source side.

That is, when using a conventional semiconductor memory device for a portable electronic device that requires a low power save mode, when the boosted voltage VPP level, which is the source side, decreases in the power save mode, the source side of the source side is more than the drain side to which the external power supply voltage VDD is applied. The bulk side connected to is at a lower voltage level, and thus a PN junction diode is formed from the drain side to the bulk side, causing a leakage current of DC to flow.

As a result, the voltage between the gate and the drain of the PMOS transistor P1 is reduced to a voltage level lower than the threshold voltage of the PMOS transistor, thereby causing a malfunction in which the PMOS transistor P1, which should be turned off, may be abnormally turned on. there was.

If the external power supply voltage VDD is used as the bulk voltage of the PMOS transistor P1, the boosted voltage VPP is applied to the source side of the PMOS transistor P1, so that the high voltage applied during the burn-in test is a word line driver. In the same circuit as above, when the internal voltage is further increased by double bootstrapping, and an excessive stress voltage is applied, an overcurrent flows from the source side of the PMOS transistor P1 to the gate side, thereby causing latch-up of the semiconductor memory device 10. The phenomenon was likely to occur.

An object of the present invention is to monitor the level of the boosted voltage more stably during the burn-in test in the package state of the semiconductor memory device, to accurately determine whether the bad chips are due to excessive stress, and to test the stable reference voltage applied from the outside. The present invention provides a semiconductor memory device and a test system for the device, which self-adjust the boosted voltage level.

The test system of the semiconductor memory device of the present invention for achieving the above object is to generate a boosted voltage internally by receiving an external power supply voltage and to compare the level of the boosted voltage and the reference voltage by receiving a reference voltage from the outside to compare the output signal. And a test equipment for generating a reference voltage and a reference voltage and receiving an output signal as a result of the comparison to monitor whether an excessive test voltage is applied in a package test process of the semiconductor memory device.

The semiconductor memory device of the present invention for achieving the above object is a boosted voltage generator for generating a boost voltage required internally by receiving an external power supply voltage, whether the test mode operation is performed after receiving and decoding a mode setting signal from the outside. A mode setting unit for generating a test mode setting signal for determining a voltage, by applying a boosted voltage to a positive input terminal and applying a reference voltage to a negative input terminal through an input pin, comparing the voltage levels, and outputting a comparison result output signal. It characterized in that it comprises a comparator for outputting through.

The semiconductor memory device of the present invention for achieving the above object is composed of a plurality of series resistors, one side of which is connected to the output terminal of the boosted voltage generator and the other side of which is grounded, so that any two of the plurality of series resistors are selected. A voltage divider may be further generated at the contact point between the voltage divider and the voltage divider applied to the positive input terminal of the comparator.

The comparator of the semiconductor memory device of the present invention for achieving the above object generates an output signal as a result of a high level comparison when the level of the boosted voltage is higher than the level of the reference voltage, and low level if the level of the boosted voltage is lower than the level of the reference voltage. The result of the comparison is characterized in that the output signal is generated.

In order to achieve the above object, the test voltage of the test system of the semiconductor memory device of the present invention is set so that the external power supply voltage is worse than the actual use condition in order to detect an early defect early in the burn-in test process of the semiconductor memory device. Characterized in that the stress voltage to be applied.

The semiconductor memory device of the present invention for achieving the above object is characterized in that it further comprises a boosting voltage adjusting control unit for controlling whether or not the boosting voltage of the boosted voltage in the boosted voltage generator according to the control of the output signal as a result of the comparison.

In order to achieve the above object, the boosted voltage adjusting control unit of the semiconductor memory device of the present invention outputs a first control signal to be output after reducing the boosted voltage of the boosted voltage generator when the comparison result output signal is at a high level, and outputs the comparison result. If the signal value is a low level, it is characterized in that for outputting the second control signal to be output after boosting the boosted voltage.

Hereinafter, a test system of a semiconductor memory device, a semiconductor memory device using the same, and a test system of the device will be described with reference to the accompanying drawings.

FIG. 2 is a schematic circuit diagram of a test system for monitoring a boosted voltage in comparison with a reference voltage at a package level of a semiconductor memory device according to a first embodiment of the present invention. The semiconductor memory device 100 and the automatic test equipment 200 are illustrated in FIG. It is provided. The semiconductor memory device 100 includes a boosted voltage generator 11, a mode setting unit 12, a comparator 130, a power supply voltage pin 100-1, an address pin 100-2, and a reference voltage input pin 100-. 3), the pins having a comparison result output pin (100-4), and the reference voltage input pin (100-3) and the comparison result output pin (100-4) does not play a large role in normal operation In the present embodiment, the clock enable pin CLE and the data mask DM pin will be described.

The function of each block of the test system for monitoring the boost voltage at the package level according to the first embodiment of the present invention shown in FIG.

The boosted voltage generator 11 receives the external power supply voltage VDD through the power supply voltage pin 100-1 to compensate for the threshold voltage loss of the transistor in the semiconductor memory device. VPP).

The mode setting unit 12 receives the mode setting signal A [14: 0] applied through the address pin 100-2 and decodes in response to the internal clock signal to generate the test mode setting signal TMRS. do.

The comparator 130 receives the boosted voltage VPP from the boosted voltage generator 11 at the positive input terminal and the stable reference voltage Vref from the automatic test equipment 200 at the negative input terminal. The flag output signal flag is generated by comparing the voltage levels according to the control of the set signal TMRS.

The automatic test equipment 200 applies the reference voltage Vref through the reference voltage input pin 100-3 of the semiconductor memory device 100, and compares the comparator 130 through the output pin 100-4 with the comparison result. The flag output signal flag is applied to monitor whether an excessive stress voltage is applied through the external power supply voltage VDD in the package test process of the semiconductor memory device 100.

Referring to Figure 2 describes the operation of the test system for monitoring the boosted voltage at the package level according to the first embodiment of the present invention.

The mode setting unit 12 receives the mode setting signal A [14: 0] through the address pin 100-2, decodes the clock signal applied from the outside in response to the buffered internal clock signal, and then tests the test mode. Generates a test mode setting signal TMRS that determines whether to perform an operation.

In the code combination in which the test mode setting signal TMRS is the normal mode operation, the test system of the present invention operates only in the code combination in the test mode operation.

Hereinafter, the test mode setting signal TMRS is set and applied as a code combination that requires the test mode operation to be performed.

In order to enter the burn-in test mode, the boosted voltage generator 11 receives an external power supply voltage (VDD) and boosts the voltage to a predetermined voltage level or more, and the automatic test equipment 200 outputs the semiconductor memory device 100. A stable reference voltage Vref having a dispersion within 50 mV is applied through the reference voltage input pin 100-3.

The comparator 130 receives the boosted voltage VPP from the boosted voltage generator 11 and the reference voltage Vref from the automatic test equipment 200, and compares the voltage levels according to the control of the test mode setting signal TMRS. To generate a flag output signal flag. When the boosted voltage VPP level is higher than the reference voltage Vref level, a flag output signal flag of a high level is generated and the boosted voltage VPP level is a reference voltage Vref. If it is lower than the level, a low level flag output signal is generated.

For example, the automatic test equipment 200 is set to 2V as the reference voltage Vref through the reference voltage input pin 100-3, and the boosted voltage generator VPP outputs 4V from the boosted voltage generator 11. Assume that

The test mode setting signal TMRS is applied to the control terminal of the comparator 130 as a code combination requesting the test mode operation to be performed, a 2 V reference voltage Vref is applied to the negative input terminal, and a positive input terminal to the positive input terminal. A boosted voltage VPP of 4V is applied to compare the magnitudes and output a high level flag output signal flag. Since the automatic test equipment 200 receives the flag output signal of the high level through the output pin 100-4 again as a result of the comparison, it is determined that excessive stress voltage is applied through the external power supply voltage VDD. .

As a result, semiconductor memory test engineers drop the stress voltage during the package burn-in test process to apply an external power supply voltage (VDD) to test the semiconductor memory device at an appropriate stress voltage to prevent unnecessary overkill of the chip. do.

3 is a schematic circuit diagram of a test system for monitoring a boosted voltage in comparison with a reference voltage at a package level of a semiconductor memory device according to a second embodiment of the present invention. In the example configuration, a voltage divider 140 is further provided between the boosted voltage generator 11 and the comparator 130.

The voltage divider 140 is composed of two or more series resistors, one side of which is connected to the output terminal of the boosted voltage generator 11, the other side of which is grounded, and an output voltage is generated at a contact point between two predetermined resistors. It is applied to the (+) terminal of 130). In FIG. 3, for convenience of understanding, the voltage divider 140 divides the boosted voltage VPP into two by using two resistors R1 and R2 having the same resistance value.

The function of each block of the test system for monitoring the boosted voltage at the package level according to the second embodiment of the present invention shown in FIG. 3 is as follows.

Generation of boosted voltage VPP of boosted voltage generator 11, Generation of test mode set signal TMRS of mode setter 12, Comparison of boosted voltage VPP and reference voltage Vref of comparator 130, and Flag output signal (flag) generation, the reference voltage (Vref) application of the automatic test equipment 200 and whether the monitoring operation of the excessive stress voltage is the same as the first embodiment of the present invention shown in FIG. Omit.

The difference is that since a high voltage is applied to the input terminal of the comparator 130, a comparator 130 is inserted between the output terminal of the boost voltage generator 11 and the input terminal of the comparator 130 by dividing the voltage divider 140 that divides the boost voltage VPP. The boost voltage VPP to be applied) is lowered to 1/2 to apply the divided voltage Vdiv.

Therefore, in a circuit such as a word line driver, a high voltage applied during burn-in test is further increased internally to provide an excessive stress voltage and a voltage drop means as described above and a stable reference voltage are applied from the outside. Continuous monitoring of the boosted voltage prevents latching up due to excessive stress and rapid overcurrent.

In the present embodiment, for convenience of understanding, the voltage divider divides the boosted voltage by two resistors by using two resistors. However, the voltage divider divides the boosted voltage of the high voltage into three or more low voltages by using three or more resistors. Of course it can be implemented.

In the above, the test system for monitoring the boosted voltage of the boosted voltage generator at the package level of the semiconductor memory device has been described as an embodiment. However, the DC voltage of the DC voltage generator other than the boosted voltage generator in the semiconductor memory device or the DC current of the DC current generator, etc. Obviously, you can implement a test system to monitor this.

4 is a schematic circuit diagram of a test system for self-adjusting a boosted voltage level at a package level of a semiconductor memory device compared to a reference voltage according to a third embodiment of the present invention. Equipment 200 is provided.

The semiconductor memory device 100 includes a boosted voltage generator 110, a mode setting unit 12, a comparator 130, a boosted voltage adjusting controller 150, a power supply voltage pin 100-1, and an address pin 100-2. And a reference voltage input pin (100-3) and a comparison result output pin (100-4), the reference voltage input pin (100-3) and the comparison result output pin (100-4) during normal operation In the present embodiment, the clock enable (CLE) pin and the data mask (DM) pin are exemplarily described.

The function of each block of the test system for self-adjusting the boosted voltage level at the package level according to the third embodiment of the present invention shown in FIG. 4 is as follows.

In FIG. 4, the functions of the mode setting unit 12, the comparator 130, and the automatic test equipment 200 are functions of the test system for monitoring the boosted voltage at the package level according to the first embodiment of the present invention illustrated in FIG. 2. Since it is the same as, detailed description is omitted here.

The difference is that the booster voltage generator 110 is boosted to the optimum booster voltage VPP so that the booster voltage generator 110 does not generate excessive stress under the control of the flag output signal from the comparator 130. Alternatively, the controller further includes a boosted voltage adjusting controller 150 for outputting a control signal to reduce the pressure and outputs the boosted voltage generator 110. The boosted voltage generator 110 receives the control signals CON1 and CON2 from the boosted voltage adjusting controller 150. The voltage of the boosted voltage VPP is adjusted to the level of the boosted voltage VPP itself.

Referring to FIG. 4, the operation of the test system for self-adjusting the boosted voltage level at the package level according to the third embodiment of the present invention will be described below.

In general, the DC generators (not shown) in the semiconductor memory device 100 have a process voltage temperature dispersion (PVT dispersion). In the case of the boosted voltage generator 110, the process spread is +/- 0.1. It has a V ~ 0.2V degree. As a result, the boosted voltage VPP during the burn-in test has a possibility of generating over stress or under stress due to dispersion to a target level.

In order to solve such a problem, conventionally, laser recovery using a fuse for measuring and recovering a boosted voltage (VPP) is typically applied in a wafer test step, but a test system for monitoring a boosted voltage (VPP) level at a package level of the present invention. Application can be more stable recovery.

Because when the reference voltage (Vref) is input from the automatic test equipment 200, since the voltage distribution is stable within 50 mV, if it is applied from the outside of the semiconductor memory device 100 using the reference voltage (Vref) as in the present invention It is possible to implement a test system that self-adjusts the boosted voltage (VPP) level at the package level.

In FIG. 4, the test mode setting signal TMRS output of the mode setting unit 12, the boosting voltage VPP output of the boosting voltage generator 110 to enter the burn-in test mode, and the reference of the automatic test equipment 200. The voltage Vref input, the voltage level comparison between the boosted voltage VPP of the comparator 130 and the reference voltage Vref, and the flag output signal generation operation according to the first embodiment of the present invention shown in FIG. The description is the same as the operation of the test system for monitoring the boosted voltage (VPP) at the package level, and thus detailed description is omitted here.

The boosted voltage adjustment controller 150 receives the flag output signal flag from the comparator 130 and causes the boosted voltage generator 110 to reduce the boosted voltage VPP when the flag output signal flag value is high. The first control signal CON1 to be outputted is output. When the flag output signal flag value is low, the second control signal CON2 is outputted after the boosted voltage VPP is boosted.

The boosted voltage generator 110 receives the first control signal CON1 from the boosted voltage regulating controller 150 to reduce the boosted voltage VPP and outputs the reduced voltage to prevent excessive stress voltage from being applied. The voltage of the boosted voltage VPP is self-adjusted so as to prevent the stress voltage below a predetermined level from being applied after the boosted voltage VPP is boosted by the output of CON2.

For example, as in the first exemplary embodiment of the present invention, the automatic test equipment 200 is set to 2 V as the reference voltage Vref through the reference voltage input pin 100-3, and the boosted voltage generator 110 is applied. Assume that a boosted voltage (VPP) of 4V is output at.

The test mode setting signal TMRS is applied to the control terminal of the comparator 130 as a code combination requesting the test mode operation to be performed, the 2V reference voltage Vref is applied to the (-) input terminal, and the (+) input terminal. A boosted voltage VPP of 4V is applied to the flag to output a high level flag output signal in comparison with the magnitude.

Since the boosted voltage adjustment controller 150 receives the flag output signal flag having a high level from the comparator 130, the boosted voltage generator 110 outputs the boosted voltage generator 110 after reducing the boosted voltage VPP. Outputs (CON1).

The boosted voltage generator 110 receives the first control signal CON1 from the boosted voltage regulating controller 150 and outputs the reduced voltage of the boosted voltage VPP after outputting itself, thereby ultimately increasing the boosted voltage VPP during the burn-in test. Decreases dispersion.

If the automatic test equipment 200 is applied with the reference voltage Vref set to 2V and the boosted voltage generator 110 outputs the boosted voltage VPP of 1.5V, the comparator 130 may level both voltages. Are compared to output a low level flag output signal.

The boosted voltage adjustment controller 150 receives a low level flag output signal from the comparator 130, so that the boosted voltage generator 110 outputs the boosted voltage VPP after boosting the boosted voltage VPP. Outputs (CON2).

When the boosted voltage generator 110 receives the second control signal CON2 from the boosted voltage regulating controller 150 and boosts the boosted voltage VPP by itself, the boosted voltage generator 110 outputs the boosted voltage VPP. Likewise, it ultimately reduces the boost voltage (VPP) distribution during burn-in tests.

At this time, the voltage booster voltage generator 110 includes an electric fuse or a resistor to permanently fix the voltage level of the boosted or decompressed voltage boosted voltage VPP to permanently fix and store the voltage boosted voltage VPP during burn-in test. Naturally, it can be reduced stably.

Next, FIG. 5 is a schematic circuit diagram of a test system for self-adjusting a boosted voltage at a package level of a semiconductor memory device in comparison with a reference voltage according to a fourth embodiment of the present invention. In the configuration of the embodiment, a voltage divider 140 is further provided between the boosted voltage generator 110 and the comparator 130.

The voltage divider 140 is composed of two or more series resistors, one side of which is connected to the output terminal of the boosted voltage generator 110, the other side of which is grounded, and an output voltage is generated at a contact between two predetermined resistors. It is applied to the (+) terminal of 130). In FIG. 5, for convenience of understanding, the voltage divider 140 divides the boosted voltage VPP into two by using two resistors R1 and R2 having the same resistance value.

The function of each block of the test system for self-adjusting the boosted voltage level at the package level according to the fourth embodiment of the present invention shown in FIG. 5 is as follows.

Generation of the boosted voltage VPP of the boosted voltage generator 110, output of the test mode setting signal TMRS of the mode setting unit 12, comparison of the level of the boosted voltage VPP and the reference voltage Vref of the comparator 130, and Flag output signal (flag) generation, the reference voltage (Vref) of the automatic test equipment 200 and the operation of monitoring whether the excessive stress voltage is applied is the same as the third embodiment of the present invention shown in FIG. Omit.

The difference is that since a high voltage is applied to the input terminal of the comparator 130, the comparator 130 is inserted between the output terminal of the boost voltage generator 110 and the input terminal of the comparator 130 by dividing the voltage divider 140 that divides the boost voltage VPP. The boost voltage VPP to be applied) is lowered to 1/2 to apply the divided voltage Vdiv.

In the present embodiment, like the second embodiment, for convenience of understanding, the voltage divider divides the boosted voltage by two using two resistors. For example, the voltage divider of the high voltage boosted voltage using three or more resistors is divided into three or more divisions. Naturally, a voltage divider can be implemented that distributes to low voltages.

Therefore, the voltage drop control circuit as described above is separately provided for the risk of excessive stress voltage being applied internally during the burn-in test, and the voltage boosted by a stable reference voltage from the outside is continuously monitored. By adjusting the boost voltage level, the boost voltage distribution during the burn-in test can be stably reduced. This allows more accurate testing at package level and more reliable recovery of bad chips at the package level by applying the appropriate voltage stress without excessive or minor voltage stress during burn-in tests.

In the above description, the test system for self-adjusting the boosted voltage of the boosted voltage generator at the package level of the semiconductor memory device has been described as an embodiment. However, the DC voltage of the DC voltage generator other than the boosted voltage generator in the semiconductor memory device or the DC current of the DC current generator is described. It's no surprise that you can implement a test system that self-adjusts your back.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

The semiconductor memory device of the present invention and the test system of the device are provided with a separate means for lowering the boost voltage of the high voltage during burn-in test, and the excessive stress is maintained while continuously monitoring the boosted voltage in comparison with the stable reference voltage applied from the outside. By preventing latch-up due to application and rapid overcurrent, and self-adjusting the boost voltage level, the boost voltage distribution can be reliably reduced to accurately interpret and fail the test early.

Claims (13)

A semiconductor memory device configured to generate a boosted voltage internally by receiving an external power supply voltage and to receive a reference voltage from an external source to compare the level of the boosted voltage with the reference voltage to output a comparison result; And And a test device configured to generate the reference voltage and receive the output signal as a result of the comparison, and to monitor whether an excessive test voltage is applied in a package test process of the semiconductor memory device. The method of claim 1, The semiconductor memory device A boosted voltage generator configured to receive the external power supply voltage and generate a boosted voltage necessary therein; A mode setting unit generating a test mode setting signal in response to a signal applied from the outside; And a comparator configured to apply the boosted voltage to a positive input terminal and the reference voltage to a negative input terminal to compare voltage levels, and to output the comparison result output signal through an output pin. A test system for a semiconductor memory device. The method of claim 2, The semiconductor memory device One side is composed of a plurality of series resistors connected to the output terminal of the boost voltage generator and the other side is grounded, And a voltage divider which generates a voltage for dividing the boosted voltage at a contact between two predetermined resistors of the plurality of series resistors and is applied to a positive input terminal of the comparator. Test system of memory devices. The method of claim 2, The comparator Generating the comparison result output signal of a high level when the level of the boosted voltage is higher than the level of the reference voltage; and generating the comparison result output signal of a low level if the level of the boosted voltage is lower than the level of the reference voltage. A test system for semiconductor memory devices. The method of claim 1, The test voltage is And a stress voltage for applying the external power supply voltage to a condition worse than an actual use condition in order to detect an early defect early in the burn-in test process of the semiconductor memory device. The method of claim 2, The semiconductor memory device And a boosting voltage adjusting control unit configured to control whether the boosting voltage is reduced or boosted by the boosted voltage generator according to the comparison result control of the output signal. The method of claim 6, The boosted voltage adjustment control unit Outputting a first control signal for reducing the boosted voltage of the boosted voltage generator after the comparison result output signal is high level; outputting the boosted voltage after boosting the boosted voltage if the comparison result output signal value is low level; And a second control signal is outputted. A boosted voltage generator configured to receive an external power supply voltage and generate a boosted voltage necessary therein; A mode setting unit generating a test mode setting signal in response to a signal applied from the outside; And a comparator configured to receive the boosted voltage and the reference voltage and compare the level of the boosted voltage and the reference voltage to generate an output signal as a result of the comparison under the control of the test mode setting signal. . The method of claim 8, The comparator When the boosted voltage is applied to the positive input terminal and the reference voltage is applied to the negative input terminal, when the test mode setting signal is high level, the voltage level is compared to output the comparison result output signal. Semiconductor memory device. The method of claim 9, The comparator Generating the comparison result output signal of a high level when the level of the boosted voltage is higher than the level of the reference voltage; and generating the comparison result output signal of a low level if the level of the boosted voltage is lower than the level of the reference voltage. A semiconductor memory device characterized by the above-mentioned. The method of claim 9, The semiconductor memory device One side is composed of a plurality of series resistors connected to the output terminal of the boost voltage generator and the other side is grounded, And a voltage divider which generates a voltage for dividing the boosted voltage at a contact between two predetermined resistors of the plurality of series resistors and is applied to a positive input terminal of the comparator. Memory device. The method of claim 9, The semiconductor memory device And a boosting voltage adjusting control unit configured to control whether the boosting voltage is reduced or boosted by the boosted voltage generator according to the comparison result. The method of claim 12, The boosted voltage adjustment control unit Outputting a first control signal for reducing the boosted voltage of the boosted voltage generator after the comparison result output signal is high level; outputting the boosted voltage after boosting the boosted voltage if the comparison result output signal value is low level; And outputting a second control signal.

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