KR20080035266A - Shift register - Google Patents

Abstract

The present invention relates to a shift register capable of preventing deterioration of a pull-down switching element, comprising a plurality of stages connected dependently to each other; A pull-up switching device in which the nth stage (n is a natural number) outputs a scan pulse through an output terminal according to the logic state of the first node provided in the nth stage; A pull-down switching device configured to output a discharge voltage source through the output terminal according to the logic state of the second node provided in the nth stage; In addition to controlling the logic states of the first and second nodes of the nth stage, the nth stage according to the logic state of the second node included in the n + m stage (m is a natural number larger than n). A node controller for controlling a logic state of the first node of the node; And a discharge unit for discharging the output terminal of the nth stage to the discharge voltage source in response to a scan pulse from an n + kth stage (k is a natural number greater than n).

Description

A shift register

1 is a diagram illustrating one stage provided in a conventional shift register.

2 illustrates a shift register according to a first embodiment of the present invention.

3 is a timing diagram of various signals supplied to each stage of FIG.

4 is a diagram illustrating a circuit configuration of the third stage of FIG. 2.

FIG. 5 is a diagram illustrating first to third stages having the circuit configuration of FIG. 4. FIG.

6 illustrates a shift register according to a second embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

CLK: Clock pulse # 266: Output terminal

ST: Stage Vst: Start pulse

Vac: AC voltage source Vdc2: Voltage source for discharge

205: node control unit Q, QB: node

Tru: Pull-Up Switching Device Trd: Pull-Down Switching Device

Vout: Scan pulse

The present invention relates to a shift register, and more particularly, to a shift register that can prevent degradation of a pull-down switching device.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driving circuit for driving the gate lines, a data driving circuit for driving the data lines, a timing controller for supplying a control signal for controlling the gate driving circuit and the data driving circuit; And a power supply unit supplying various driving voltages used in the liquid crystal display.

The gate driving circuit sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driving circuit supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driving circuit includes a shift register so as to sequentially output the scan pulse as described above. This shift register has a plurality of stages that sequentially output scan pulses.

1 is a view showing one stage provided in a conventional shift register.

As shown in FIG. 1, a stage provided in a conventional shift register includes a node controller 100 for controlling charge and discharge states of first and second nodes Q and QB, and the first node ( A pull-up switching device Tru having a gate terminal connected to Q) and a pull-down switching device QB having a gate terminal connected to the second node QB.

Here, the first node Q and the second node QB are alternately charged and discharged. Specifically, when the first node Q is in a charged state, the second node QB is discharged. The first node Q is discharged when the second node QB is in a charged state. At this time, each stage outputs a scan pulse in only one horizontal period (1H) of one frame, and outputs a discharge voltage source for the remaining period. Accordingly, the pull-up switching device Tru is turned on only one horizontal period, and the pull-down switching device Trd remains turned on for the remaining periods except the period. In other words, the pull-down switching device Trd remains turned on for most of one frame period. As a result, deterioration of the pull-down switching device Trd is accelerated.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a shift register which can prevent deterioration of the pull-down switching device by discharging the node to which the pull-down switching device is connected every cycle.

The shift register according to the present invention for achieving the above object comprises a plurality of stages connected dependently to each other; A pull-up switching device in which the nth stage (n is a natural number) outputs a scan pulse through an output terminal according to the logic state of the first node provided in the nth stage; A pull-down switching device configured to output a discharge voltage source through the output terminal according to the logic state of the second node provided in the nth stage; In addition to controlling the logic states of the first and second nodes of the nth stage, the nth stage according to the logic state of the second node included in the n + m stage (m is a natural number larger than n). A node controller for controlling a logic state of the first node of the node; And a discharge unit for discharging the output terminal of the nth stage to the discharge voltage source in response to a scan pulse from the n + kth stage (k is a natural number greater than n).

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register according to a first exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating a timing diagram of various signals supplied to each stage of FIG. 2.

The shift register according to the first embodiment of the present invention includes a plurality of stages connected dependently to each other, as shown in FIG.

The shift register includes the first to fourth clock pulses CLK1 to CLK4, the charging voltage source Vdc1, the discharge voltage source Vdc2, the first and second AC voltage sources Vac1 and Vac2, and the start pulse Vst. It outputs scan pulse in order.

The charging voltage source Vdc1 is a positive voltage source, and the discharge voltage source Vdc2 is a negative voltage source. This charging voltage source Vdc1 is a voltage which turns on a switching element, and the discharge voltage source Vdc2 is a voltage which turns off a switching element.

The first AC voltage source Vac1 and the second AC voltage source Vac2 have phases inverted with each other for each frame period. That is, the first and second AC voltage sources Vac1 and Vac2 represent different logic states in units of p frame periods (p is a natural number). That is, if the first AC voltage source Vac1 remains high for the odd frame period and low for the even frame period, the second AC voltage source Vac2 remains low for the odd frame period. And remain high for the even-th frame period. The high state of each of the AC voltage sources Vac1 and Vac2 is at the same level as the charging voltage source Vdc1, and the low state of each of the AC voltage sources Vac1 and Vac2 is at the same level as the discharge voltage source Vdc2.

Each clock pulse CLK1 to CLK4 has the same pulse width and duty rate. In addition, the clock pulses output in the adjacent period are kept high at the same time for a predetermined period. For example, the pulse width (high pulse width) of the first clock pulse CLK1 and the pulse width (high pulse width) of the second clock pulse CLK2 are the same, and the first clock pulse CLK1 is the same. The second half of s) overlaps the first half of the second clock pulse CLK2. In this case, an overlapping section between the pulse width of the first clock pulse CLK1 and the pulse width of the second clock pulse CLK2 corresponds to about 1/2 pulse width section.

The start pulse Vst has a pulse width corresponding to one half of the clock pulses CLK1 to CLK4. This start pulse Vst has one high state for one frame period.

Each stage ST1, ST2, ST3, ..., STn is turned on or off according to the logic state (charge or discharge state) of the first node Q, and outputs a scan pulse at turn-on time. A pull-down switching device Trd which is turned on or turned off according to the pull-up switching device Tru and the logic state of the second node QB, and outputs a discharge voltage source Vdc2 at turn-on time, and And a node controller 205 for controlling the logic states of the first and second nodes n1 and n2, and a discharge unit 400 for bringing the output terminal 266 of the stage into a discharge state.

The discharge unit 400 substantially represents a switching element for discharging, and the discharge unit 400 provided in the k-th stage has a discharge voltage source Vdc2 in response to the scan pulse from the k + 2th stage. To discharge.

Each stage ST1, ST2, ST3, ..., STn receives one of the first to fourth clock pulses CLK1 to CLK4, and outputs it as a scan pulse. Here, the first clock pulse CLK1 is supplied to the 4k + 1 stage, the second clock pulse CLK2 is supplied to the 4k + 2 stage, and the third clock pulse CLK3 is the 4k + 3 stage. The fourth clock pulse CLK4 is supplied to the 4k + 4 stage. At this time, each clock pulse CLK1 to CLK4 is supplied to the pull-up switching device Tru of each of the stages ST1, ST2, ST3, ..., STn.

Of the stages ST1, ST2, ST3,..., And STn, the odd-numbered stages ST1, ST3, ST5,..., STn-1, that is, the second k-1 stages are the first AC voltage sources Vac1. To be supplied. The even-numbered stages ST2, ST4, ST6,..., STn-1, that is, the second k stages of the stages are supplied with the second AC voltage source Vac2.

Here, the connection relation between the stages ST1, ST2, ST3, ..., STn will be described in more detail as follows.

The kth stage discharges its second node QB to the discharge voltage source Vdc2 in response to the scan pulse from the k-2th stage.

The k-th stage charges its first node Q with the charging voltage source Vdc1 in response to the scan pulse from the k-th stage, and charges its second node QB with a discharge voltage source. Discharge at (Vdc2).

The k-th stage discharges its first node Q to the discharge voltage source Vdc2 in response to the scan pulse from the k + 2th stage, and also its own second node QB to the first alternating current. Charged to voltage source Vac1 (or second AC voltage source Vac2). That is, the second k-1 stage discharges its first node Q to the discharge voltage source Vdc2 in response to the scan pulse from the second k + 1 stage, and also discharges its second node QB. The first AC voltage source Vac1 is charged. The second k stage discharges its first node Q to the discharge voltage source Vdc2 in response to the scan pulse from the second k + 2 stage, and the second node QB to the second node QB. Charge with an AC voltage source (Vac2).

When the first node Q of the k-th stage is charged, the pull-up switching device Tru connected to the first node Q is turned on, and the turned-on pull-up switching device Tru is itself turned on. The clock pulse supplied to the drain terminal of is output as a scan pulse. The scan pulse is supplied to a k-th gate line, a k + 1th stage, a k + 2th stage, and a k-2th stage.

On the other hand, the second node QB of the k-th stage is connected to the node controller 205 of the k-th stage. Specifically, the second node QB of the k-th stage is connected to the gate terminal of the switching element provided in the k-th stage. The switching device controls the logic state of the first node Q provided in the k-1 stage. Accordingly, the node control unit 205 of the k-th stage performs the logic state of the first node Q provided in the k-th stage according to the logic state of the second node QB of the k-th stage. To control.

Here, the circuit configuration of each stage is as follows.

4 is a diagram illustrating a circuit configuration of the third stage of FIG. 2.

The node control unit 205 of each stage ST1, ST2, ST3, ..., STn includes first to eleventh switching elements Tr1 to Tr11.

The first switching element Tr1 provided in the node controller 205 of the kth stage responds to the k-1th scan pulse from the output terminal of the k-1st stage to supply the charging voltage source Vdc1 to the kth stage. It supplies to the 1st node Q of a stage. To this end, a gate terminal of the first switching element Tr1 provided in the kth stage is connected to an output terminal of the k-1st stage, and a drain terminal of the first direct current that transmits the charging voltage source Vdc1. It is connected to the power line, and the source terminal is connected to the first node Q of the kth stage. For example, the first switching device Tr1 included in the third stage ST3 of FIG. 4 may be configured to respond to the second scan pulse Vout2 from the second stage ST2 of the third stage ST3. The first node Q is charged with the charging voltage source Vdc1.

The second switching element Tr2 included in the node controller 205 of the kth stage supplies the discharge voltage source Vdc2 to the kth stage in response to the k-1th scan pulse from the k-1st stage. Supply to 2 nodes (QB). To this end, the gate terminal of the second switching element Tr2 provided in the k-th stage is connected to the output terminal of the k-th stage, and the drain terminal is connected to the second node QB of the k-th stage. And, the source terminal is connected to the second DC power line for transmitting the discharge voltage source (Vdc2). For example, the second switching device Tr2 included in the third stage ST3 of FIG. 4 may be configured to respond to the second scan pulse Vout2 from the second stage ST2 of the third stage ST3. The second node Q is discharged to the discharge voltage source Vdc2.

The third switching device Tr3 included in the node controller 205 of the k-th stage outputs the first AC voltage source Vac1 in response to the first AC voltage source Vac1 and outputs the first AC voltage source Vac1 to the k-th stage. 6 is supplied to the gate terminal of the switching element Tr6. To this end, the gate terminal and the drain terminal of the third switching device Tr3 provided in the k-th stage are connected to a first AC power line for transmitting the first AC voltage source Vac1, and the source terminal is k-th. It is connected to the gate terminal of the sixth switching element Tr6 provided in the stage. For example, the third switching device Tr3 included in the third stage ST3 of FIG. 4 outputs the first AC voltage source Vac1 in response to the first AC voltage source Vac1, and this is the third stage. The gate terminal of the sixth switching device Tr6 provided in ST3 is supplied.

The fourth switching device Tr4 included in the node controller 205 of the kth stage outputs the discharge voltage source Vdc2 in response to the charging voltage source Vdc1 supplied to the first node Q of the kth stage. Then, it is supplied to the gate terminal of the sixth switching device Tr6 provided in the kth stage. For this purpose, the gate terminal of the fourth switching element Tr4 provided in the kth stage is connected to the first node Q of the kth stage, the drain terminal is connected to the second DC power line, and The source terminal is connected to the gate terminal of the sixth switching device Tr6 provided in the kth stage. For example, the fourth switching device Tr4 provided in the third stage ST3 of FIG. 4 may be in response to the charging voltage source Vdc1 supplied to the first node Q of the fourth stage ST4. A dedicated voltage source Vdc2 is output and supplied to the gate terminal of the sixth switching device Tr6 provided in the third stage ST3.

The fifth switching device Tr5 provided in the node controller 205 of the kth stage outputs the discharge voltage source Vdc2 in response to the k-2th scan pulse from the k-2th stage, and outputs the discharge voltage source Vdc2. The gate terminal of the sixth switching device Tr6 provided in the stage is supplied. To this end, the gate terminal of the fifth switching device Tr5 provided in the k-th stage is connected to the output terminal 266 of the k-th stage, and the drain terminal of the sixth switching provided in the k-th stage. It is connected to the gate terminal of the element Tr6, and the source terminal is connected to the said 2nd DC power supply line. For example, the fifth switching device Tr5 provided in the third stage ST3 of FIG. 4 outputs the discharge voltage source Vdc2 in response to the first scan pulse Vout1 from the first stage ST1. Then, it is supplied to the gate terminal of the sixth switching device provided in the third stage (ST3).

The sixth switching device Tr6 included in the node controller 205 of the kth stage is configured to respond to the output from the third, fourth, and fifth switching devices Tr3, Tr4, and Tr5. Vac1 (or a second AC voltage source Vac2) is supplied to the second node QB of the k-th stage. To this end, the gate terminal of the sixth switching device Tr6 provided in the kth stage is the source terminal of the third switching device Tr3 and the drain terminals of the fourth and fifth switching devices Tr4 and Tr5. Is connected to. The drain terminal of the sixth switching element Tr6 is connected to the first AC power line, and the source terminal is connected to the second node QB of the kth stage. For example, the sixth switching device Tr6 included in the third stage ST3 of FIG. 4 may be configured to respond to outputs from the third, fourth, and fifth switching devices Tr3, Tr4, and Tr5. The first AC voltage source Vac1 is supplied to the second node QB of the third stage ST3.

The seventh switching element Tr7 included in the node controller 205 of the kth stage is the first AC voltage source Vac1 (or the second AC voltage source Vac2) supplied to the first node Q of the kth stage. In response, the discharge voltage source Vdc2 is supplied to the first node Q of the k-th stage. To this end, the gate terminal of the seventh switching element Tr7 provided in the kth stage is connected to the second node QB of the kth stage, and the drain terminal of the first node Q of the kth stage. Is connected to the second DC power line. For example, the seventh switching device Tr7 included in the third stage ST3 of FIG. 4 may include the first AC voltage source Vac1 (or the first voltage supplied to the second node QB of the third stage ST3). In response to the second AC voltage source Vac2, the first node Q of the third stage ST3 is discharged to the discharge voltage source Vdc2.

The eighth switching element Tr8 included in the node control unit 205 of the kth stage is the first AC voltage source Vac1 (or the second AC voltage source supplied to the second node QB from the k + 1th stage). In response to Vac2), the discharge voltage source Vdc2 is supplied to the first node Q of the k-th stage. To this end, the gate terminal of the eighth switching device Tr8 provided in the kth stage is connected to the second node QB of the k + 1th stage, and the drain terminal of the first node of the kth stage ( Q), and the source terminal is connected to the second DC power line. For example, the eighth switching device Tr8 included in the third stage ST3 of FIG. 4 may include the first AC voltage source Vac1 (or the second node QB of the fourth stage ST4). In response to the second AC voltage source Vac2, the first node Q of the third stage ST3 is discharged to the discharge voltage source Vdc2.

The ninth switching element Tr9 included in the node control unit 205 of the kth stage receives the discharge voltage source Vdc2 in response to the charging voltage source Vdc1 supplied to the first node Q of the kth stage. It supplies to the 2nd node QB of the kth stage. To this end, the gate terminal of the ninth switching element Tr9 provided in the k-th stage is connected to the first node Q of the k-th stage, and the drain terminal of the second node QB of the k-th stage. Is connected to the second DC power line. For example, the ninth switching device Tr9 provided in the third stage ST3 of FIG. 4 responds to the charging voltage source Vdc1 supplied to the first node Q of the third stage ST3. The second node QB of the third stage ST3 is discharged to the discharge voltage source Vdc2.

The tenth switching element Tr10 included in the node control unit 205 of the kth stage supplies the discharge voltage source Vdc2 to the kth stage of the kth stage in response to the k-2th scan pulse from the k-2th stage. Supply to 2 nodes (QB). To this end, the gate terminal of the tenth switching element Tr10 provided in the k-th stage is connected to the output terminal of the k-th stage, and the drain terminal is connected to the second node QB of the k-th stage. And the source terminal is connected to the second DC power line. For example, the tenth switching device Tr10 of the third stage ST3 of FIG. 4 may be configured to respond to the first scan pulse Vout1 from the first stage ST1 of the third stage ST3. The second node QB is discharged to the discharge voltage source Vdc2.

The eleventh switching element Tr11 provided in the node controller 205 of the kth stage responds to the k + 2th scan pulse from the k + 2th stage to supply the discharge voltage source Vdc2 to the kth stage of the kth stage. Supply to one node (Q). To this end, the gate terminal of the eleventh switching element Tr11 provided in the kth stage is connected to the output terminal of the k + 2th stage, and the drain terminal is connected to the first node Q of the kth stage. And the source terminal is connected to the second DC power line. For example, the eleventh switching element Tr11 of the third stage ST3 of FIG. 4 may be configured to respond to the fifth scan pulse Vout5 from the fifth stage ST5 of the third stage ST3. The first node Q is discharged to the discharge voltage source Vdc2.

The operation of the shift register according to the embodiment of the present invention configured as described above is as follows.

FIG. 5 is a diagram illustrating first to third stages having the circuit configuration of FIG. 4.

First, the operation during the initial period T0 will be described. On the other hand, assuming that the first AC voltage source Vac1 remains high and the second AC voltage source Vac2 remains low for one frame period including the initial period to the nth period, the odd stage ( The third switching devices Tr3 of ST1, ST3, ST5, ..., STn-1 remain turned on for the one frame period, and the even-numbered stages ST2, ST4, ST6, ..., The third switching element Tr3 of STn remains turned off for the one frame period.

During the initial period TO, as shown in FIG. 3, only the start pulse Vst remains high and the remaining clock pulses CLK1 to CLK4 remain low.

The start pulse Vst is input to the first stage ST1. Specifically, as shown in FIG. 5, the start pulse Vst includes first, second, fifth, and tenth switching elements Tr1, Tr2, Tr5, and Tr10 provided in the first stage ST1. Is supplied to the gate terminal. Thus, the first, second, fifth, and tenth switching elements Tr1, Tr2, Tr5, and Tr10 are turned on.

The charging voltage source Vdc1 is supplied to the first node Q of the first stage ST1 through the turned-on first switching device Tr1. Accordingly, the first node Q of the first stage ST1 is charged by the charging voltage source Vdc1 and the pull-up switching device Trpu having a gate terminal connected to the charged first node Q. ), The fourth switching element Tr4 and the ninth switching element Tr9 are turned on.

The discharge voltage source Vdc2 is supplied to the second node QB of the first stage ST1 through the turned-on second switching element Tr2. In addition, a discharge voltage source Vdc2 is supplied to the second node QB through the turned-on ninth and tenth switching elements Tr9 and Tr10. Accordingly, the second node QB of the first stage ST1 is discharged by the discharge voltage source Vdc2, and the pull-up switching device Trpu having a gate terminal connected to the discharged second node QB. ) And the seventh switching element Tr7 are turned off.

The discharge voltage source Vdc2 output through the turned-on fourth and fifth switching devices Tr4 and Tr5 is supplied to the gate terminal of the sixth switching device Tr6. In addition, the first AC voltage source Vac1 of the high state is supplied to the gate terminal of the sixth switching element Tr6 through the third switching element Tr3 that is turned on for one frame period. Accordingly, the discharge voltage source Vdc2 is supplied to the gate terminal of the sixth switching element Tr6 through two switching elements, and the first AC voltage source Vac1 of the high state is supplied through one switching element. . Since the number of switching elements for supplying the discharge voltage source Vdc2 is greater than the number of switching elements for supplying the first AC voltage source Vac1 in the high state, the gate terminal of the sixth switching element Tr6 is in a low state. Is maintained. Therefore, the sixth switching device Tr6 maintains the turn-off state.

On the other hand, the start pulse Vst is also input to the second stage ST2. Specifically, as shown in FIG. 5, the start pulse Vst is supplied to the gate terminals of the fifth and tenth switching elements Tr5 and Tr10 provided in the second stage ST2. Accordingly, the fifth and tenth switching elements Tr5 and Tr10 of the second stage ST2 are turned on.

The discharge voltage source Vdc2 is supplied to the gate terminal of the sixth switching device Tr6 provided in the second stage ST2 through the turned-on fifth switching device Tr1. Accordingly, the sixth switching device Tr6 is turned off.

The discharge voltage source Vdc2 is supplied to the second node QB of the second stage through the turned-on tenth switching element Tr10. As a result, the second node QB is discharged, and the seventh switching element Tr7 of the discharged second stage ST2 is turned off. In addition, since the second node QB of the second stage ST2 is connected to the gate terminal of the eighth switching element Tr8 provided in the first stage ST1, the eighth switching element Tr8. ) Is also turned off. As the eighth switching device Tr8 is turned off, the discharge of the first node Q of the first stage ST1 is prevented.

Next, the operation during the first period T1 will be described.

During the first period T1, as shown in FIG. 3, only the first clock pulse CLK1 remains high, and the remaining clock pulses CLK2, CLK3, and CLK4 including the start pulse Vst are maintained. It remains low.

Therefore, the first switching device Tr1 and the fifth switching device Tr5 of the first stage ST1 are turned off in response to the start pulse Vst in the low state.

At this time, as the first switching device Tr1 is turned off, the first node Q of the first stage ST1 is maintained in a floating state.

As the first node Q of the first stage ST1 is kept charged by the charging voltage source Vdc1 that has been applied during the initial period T0, a gate terminal of the first node Q1 is maintained. The pull-up switching device Tru of the first stage ST1 to which is connected is maintained in the turn-on state.

In this case, the first clock pulse CLK1 is supplied to the drain terminal of the turned-on pull-up switching device Tru. Then, the charging voltage source Vdc1 charged in the first node Q of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping). This amplification occurs because the first node Q is in a floating state.

Therefore, the first clock pulse CLK1 supplied to the drain terminal of the pull-up switching device Tru provided in the first stage ST1 is stably output through the source terminal of the pull-up switching device Tru. The first clock pulse CLK1 output from the pull-up switching device Tru is the first scan pulse Vout1.

The output first scan pulse Vout1 is supplied to the first gate line GL1 to drive the first gate line GL1.

Meanwhile, the first scan pulse Vout1 output from the pull-up switching device Tru of the first stage ST1 is supplied to the second stage ST2 to provide the first node Q of the second stage ST2. ) Is charged and serves as a start pulse Vst for discharging the second node QB. That is, the first scan pulse Vout1 is supplied to the gate terminals of the first and second switching devices Tr1 and Tr2 provided in the second stage ST2, so that the first scan pulse Vout1 is supplied to the first stage of the second stage ST2. The node Q is charged and the second node QB is discharged.

In addition, the first scan pulse Vout1 is supplied to the gate terminals of the fifth and tenth switching elements Tr5 and Tr10 provided in the third stage ST3, and the fifth and tenth switching elements Tr5, Turn on Tr10). The tenth switching device Tr10 provided in the third stage ST3 is turned on, thereby preventing the eighth switching device provided in the second stage ST2 from being turned on. That is, in the first period T1, the second stage ST2 should have the enabled state (that is, the first node Q should be kept in the charged state), but the third stage ST3 will not be able to operate. The ten switching element Tr10 prevents the first node Q of the second stage ST2 from being discharged by turning off the eighth switching element Tr8.

In detail, the discharge voltage source Vdc2 is supplied to the second node QB of the third stage ST3 through the turned-on tenth switching element Tr10. Accordingly, the second node QB is in a discharged state. Since the second node QB is connected to the gate terminal of the eighth switching device Tr8 provided in the second stage QB, the eighth switching device Tr8 is turned off.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, the first and second clock pulses CLK1 and CLK2 remain high. On the other hand, the clock pulses CLK3 and CLK4 including the start pulse Vst remain low.

Therefore, the first stage ST1 operates in the same manner as the first period T1. That is, the first stage ST1 outputs the first scan pulse Vout1. In this second period, the first gate line is completely charged by the first scan pulse Vout1.

In addition, the second stage ST2 is enabled by the first scan pulse Vout1 in the same manner as the first period T1 described above. In this second period T2, the first node Q of the second stage ST2 is fully charged. At the same time, as the second clock pulse CLK2 is supplied to the pull-up switching device Tru provided in the second stage ST2, the second stage ST2 is in a state as described above. The second scan pulse Vout2 is output in the state of the first stage ST1 in one period T1.

The second scan pulse Vout2 is supplied to the second gate line, the third stage ST3, and the fourth stage ST4. Then, the first node Q of the third stage ST3 is charged, and the eighth switching device Tr8 included in the third stage ST3 is the tenth switching provided in the fourth stage ST4. It is turned off by the element Tr10.

Next, the operation during the third period T3 will be described.

During the third period T3, as shown in FIG. 3, the second and third clock pulses CLK2 and CLK3 remain high. On the other hand, the remaining clock pulses CLK1 and CLK4 including the start pulse Vst remain low.

In the third period T3, the second stage ST2 continuously outputs the second scan pulse Vout2 to completely charge the second gate line. The first node Q of the third stage ST3 is completely charged by the second scan pulse Vout2, and at the same time, the third stage ST3 receives the third clock pulse CLK3 as the third scan pulse. Output as (Vout3).

The third scan pulse Vout3 is supplied to the third gate line, the fourth stage ST4, the fifth stage ST5, and the first stage ST1. Then, the first node Q of the fourth stage ST4 is charged, and the eighth switching device Tr8 included in the fourth stage ST4 is the tenth switching provided in the fifth stage ST5. It is turned off by the element Tr10.

Meanwhile, the first stage ST1 is disabled by the third scan pulse Vout3. The disable operation of the first stage ST1 is as follows.

That is, the third scan pulse Vout3 is supplied to the eleventh switching element Tr11 and the discharge unit 400 provided in the first stage ST1. As a result, the eleventh switching element Tr11 and the discharge part 400 are turned on. Then, the discharge voltage source Vdc2 is supplied to the first node Q of the first stage ST1 through the turned-on eleventh switching element Tr11. Accordingly, the first node Q is discharged, and the fourth, ninth, and pull-up switching devices Tr4, Tr9, and Tru with the gate terminal connected to the discharged first node Q are turned off. do.

On the other hand, since the start pulse Vst is in the low state during the third period T3, the fifth and tenth switching elements Tr5, of the first stage ST1, which are supplied with the start pulse Vst in this low state, Tr10) is turned off. In addition, the third switching device Tr3 of the first stage ST1 supplied with the first AC voltage source Vac1 is turned on.

As described above, since the fourth and fifth switching devices Tr4 and Tr5 of the first stage ST1 are turned off and the third switching device Tr3 is turned on, the first stage ST1. The sixth switching element Tr6 included in the) is turned on.

The first AC voltage source Vac1 having a high state is supplied to the second node QB of the first stage ST1 through the turned-on sixth switching device Tr6. Accordingly, the seventh switching element Tr7 and the pull-down switching element Trd of the first stage ST1 having the second node QB charged and the gate terminal connected to the charged second node QB. Is turned on. The discharge voltage source Vdc2 is supplied to the first node Q of the first stage ST1 through the turned-on seventh switching element Tr7. In addition, a discharge voltage source Vdc2 is supplied to the first gate line through the turned-on pull-down switching device Trd. As a result, the first gate line is discharged.

In addition, as the discharge voltage source Vdc2 is supplied to the first gate line through the discharge unit 400, the discharge speed of the first gate line is accelerated.

On the other hand, even-numbered stages ST2, ST4, ST6, ..., STn, that is, second stage ST2, are disabled by the fourth scan pulse Vout4 from the fourth stage ST4. Since the second AC voltage source Vac2 in the low state is supplied to the second stage ST2, the second node QB of the second stage ST2 is not charged but remains in a discharged state.

When the stages ST1, ST2, ST3, ..., STn are disabled as described above, the second node (1) of the odd stages ST1, ST3, ST5, ..., STn-1 in one frame period is disabled. QB) is charged, and the second node QB of even-numbered stages ST2, ST4, ST6, ..., STn is charged in the next frame period. Accordingly, the pull-down switching device Trd of the odd stages ST1, ST3, ST5, ..., STn-1 and the pull-down switching device of the even-numbered stages ST2, ST4, ST6, ..., STn ( Trd) operates for each frame period. Therefore, deterioration of the pull-down switching device Trd can be prevented.

However, even when the pull-down switching devices Trd of the odd stages ST1, ST3, ST5, ..., STn-1 operate in one frame period, the even-numbered stages ST2, ST4, ST6, ..., STn Since the pull-down switching device Trd of Fig. 1 does not operate, the discharge voltage source Vdc2 is not supplied to the gate line connected to the even-numbered stages ST2, ST4, ST6, ..., STn. In order to prevent this, the discharge unit 400 of each stage ST1, ST2, ST3,..., STn supplies a discharge voltage source Vdc2 to the corresponding gate line in a period in which each stage is disabled.

For example, since the pull-down switching device Trd provided in the second stage ST2 supplied with the second AC voltage source Vac2 in the low state is turned off during the disable period, the pull-down switching device ( The discharge voltage source Vdc2 is not output from the Trd. However, the discharge unit 400 provided in the second stage ST2 receives the fourth scan pulse Vout4 from the fourth stage ST4 and outputs the discharge voltage source Vdc2, which is then discharged to the second gate. The second gate line is maintained in a discharge state by supplying the line.

During the next frame period, as the first AC voltage source Vac1 is kept low and the second AC voltage source Vac2 is kept high, the odd stage ST1 receiving the first AC voltage source Vac1 is supplied. Pull-down switching devices Trd of ST3, ST5, ..., STn-1 operate, and even-numbered stages ST2, ST4, ST6, ..., STn supplied with the second AC voltage source Vac2. The pull-down switching device Trd of does not operate.

The shift register configured in this way is formed on the liquid crystal panel. Specifically, the liquid crystal panel has a display portion having a plurality of pixel regions surrounded by the gate lines and data lines, and a non-display portion formed around the display portion, wherein the shift register is formed on the non-display portion.

The non-display unit may be divided into a first non-display unit positioned on the left side of the display unit and a second non-display unit positioned on the right side of the display unit. In general, the first non-display unit is larger than an area of the second non-display unit.

The shift register is formed in the first non-display portion, and the area of the non-display portion can be efficiently used by placing the discharge unit 400 included in the shift register in the second non-display portion.

6 is a diagram illustrating a shift register according to a second embodiment of the present invention.

As shown in FIG. 6, a first non-display unit, that is, a first to transmit first to fourth clock pulses CLK1 to CLK4 on one side of the gate lines GL1, GL2, GL3,..., GLn. To fourth clock transmission lines, a start pulse transmission line for transmitting the start pulse Vst, a first DC power line for transmitting the charging voltage source Vdc1, and a transmission voltage source Vdc2. 2 DC power lines are formed.

On the other side of the second non-display unit, that is, the gate lines GL1, GL2, GL3,..., GLn, a second DC power line for transmitting the discharge unit 400 and the discharge voltage source Vdc2 is provided. Is formed.

The nth discharge part 400 corresponding to the nth stage operates by receiving a scan pulse output through the n + 2th gate line.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register according to the present invention as described above has the following effects.

The present invention can prevent deterioration of the pull-down switching device by discharging the node to which the pull-down switching device is connected every cycle.

Claims (10)

A plurality of stages connected dependently to each other; The nth stage (n is a natural number), A pull-up switching device configured to output a scan pulse through an output terminal according to a logic state of the first node provided in the nth stage; A pull-down switching device configured to output a discharge voltage source through the output terminal according to the logic state of the second node provided in the nth stage; In addition to controlling the logic states of the first and second nodes of the nth stage, the nth stage according to the logic state of the second node included in the n + m stage (m is a natural number larger than n). A node controller for controlling a logic state of the first node of the node; And, And a discharge unit for discharging an output terminal of the nth stage to the discharge voltage source in response to a scan pulse from an n + kth stage (k is a natural number greater than n). The method of claim 1, The pull-up switching element of each stage receives one of at least two clock pulses having different phase differences and outputs it as a scan pulse; And, The shift register, characterized in that the active period of each clock pulse overlap each other for a certain period. The method of claim 2, The first half active period of the p th clock pulse (p is a natural number) overlaps the second half active period of the p + 1 th clock pulse; And, And a second half active section of the p th clock pulse overlaps with a first half active section of a p-1 clock pulse. The method of claim 2, The node controller of the nth stage is Put a second node of the nth stage in a discharge state in response to a scan pulse from the n-2th stage; Put a first node of the nth stage in a charged state in response to a scan pulse from the n-1th stage, and put a second node of the nth stage in a discharged state; And, In response to a scan pulse from the n + 2th stage, the first node of the nth stage is discharged, and the second node of the nth stage is placed in any one of a charged state and a discharged state. Shift register. The method of claim 4, wherein In the 2t-1 frame period (t is a natural number), The node controller of the 2n-1 stage makes the second node of the 2n-1 stage charged in response to a scan pulse from the 2n + 1 stage; The node control unit of the second nn stage puts the second node of the second nn stage in a charged state in response to a scan pulse from the second n + 2th stage; And, In the 2t frame period, The node controller of the second n-1 stage makes the second node of the second n-1 stage discharge in response to a scan pulse from the second n + 1 stage; And the node control unit of the second n-th stage puts the second node of the second n-th stage into a charging state in response to a scan pulse from the second n + 2 stage. The method of claim 5, wherein The node controller provided in the 2n-1 stage is A first switching device configured to supply a charging voltage source to a first node of the second n-1 stage in response to a start pulse from an external source or a scan pulse from a second n-2 stage; A second switching element configured to supply a discharge voltage source to a second node of the second n-1 stage in response to the start pulse or the scan pulse of the second n-2 stage rotor; A third switching element configured to output the first AC voltage source in response to a first AC voltage source; A fourth switching device configured to output a discharge voltage source in response to the charging voltage source supplied to the first node of the 2n-1 stage; A fifth switching device configured to output the discharge voltage source in response to a scan pulse from a 2n-3 stage; A turn-on or turn-off in response to a voltage source supplied from the third, fourth, and fifth switching elements, and supplying a first alternating voltage source to a second node of the second n-1 stage at turn-on; 6 switching elements; A seventh switching device for supplying a discharge voltage source to the node control unit of the first node and the 2n-2 stage of the 2n-1 stage in response to the first AC voltage source supplied to the second node of the 2n-1 stage. ; An eighth switching device configured to supply a discharge voltage source to a first node of the second n-1 stage in response to a second AC voltage source supplied to a second node of a second nn stage; A ninth switching element configured to supply a discharge voltage source to a second node of the 2n-1 stage in response to a charging voltage source supplied to the first node of a 2n-1 stage; A tenth switching element configured to supply a discharge voltage source to a second node of the second n-1 stage in response to a scan pulse from the second n-3 stage; And, And an eleventh switching device for supplying a discharge voltage source to the first node of the 2n-1 stage in response to the scan pulse from the 2n + 1 stage. The method of claim 6, The node controller provided in the 2n stage is A first switching device for supplying a charging voltage source to the first node of the second n-th stage in response to a second start pulse from the outside or a scan pulse from the 2n-1th stage; A second switching device configured to supply a discharge voltage source to a second node of the second n stage in response to the first start pulse or the scan pulse of the second n-1 stage rotor; A third switching device configured to supply the second AC voltage source to a common node of the second n stage in response to a second AC voltage source; A fourth switching element configured to output a discharge voltage source in response to the charging voltage source supplied to the first node of the second nn stage; A fifth switching device configured to output the discharge voltage source in response to a scan pulse from a 2n-2 stage; A sixth switching that is turned on or off in response to a voltage source supplied from the third, fourth, and fifth switching elements, and supplies a second alternating voltage source to the second node of the second n-stage at turn-on; device; A seventh switching device configured to supply a discharge voltage source to a node controller of the first node and the 2n-1 stage of the second n-th stage in response to a second AC voltage source supplied to the second node of the second n-th stage; An eighth switching device configured to supply a discharge voltage source to the first node of the second nn stage in response to a second AC voltage source supplied to the second node of the second nn + 1 stage; A ninth switching element configured to supply a discharge voltage source to the second node of the second nn stage in response to the charging voltage source supplied to the first node of the second nn stage; A tenth switching device configured to supply a discharge voltage source to a second node of the second n-th stage in response to a scan pulse from the second n-n-2th stage; And, And an eleventh switching element for supplying a discharge voltage source to the first node of the second nth stage in response to a scan pulse from the second n + 2th stage. The method of claim 1, The discharge unit provided in the nth stage, And a discharge switching element for supplying a discharge voltage source to the output terminal in response to a scan pulse from the n + 2th stage. The method of claim 1, Node control unit, pull-up switching device, pull-down switching device of each stage. And a first node and a second node located at one side of the gate lines, and the discharge unit is located at the other side of the gate lines. The method of claim 9, The nth discharge unit corresponding to the nth stage is operated by receiving a scan pulse output through the n + 2th gate line.

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