KR20080033768A - Display substrate and manufacturing method thereof - Google Patents

Abstract

A display substrate and a method of manufacturing the same for preventing protrusion of an active layer are disclosed. A method of manufacturing a display substrate includes forming a first metal pattern including gate wirings and a gate electrode of a thin film transistor on a substrate, and forming a gate insulating layer, an active layer, and a photoresist film on the substrate on which the first metal pattern is formed. Forming a photoresist film sequentially; forming a photoresist pattern overlapping the first metal pattern by patterning the photoresist film with a back exposure; etching the active layer using the photoresist pattern as an etching mask; Removing a pattern, forming a second metal pattern including data lines crossing the gate lines, a source electrode of the thin film transistor, and a drain electrode on the substrate from which the photoresist pattern is removed; Forming a pixel electrode electrically connected to the drain electrode on the formed substrate; . By forming the active layer overlapping the first metal pattern through the back exposure, it is possible to prevent the formation of the active protrusions generated in the conventional four to three mask process.

Description

DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME}

1 is a plan view of a display substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 to 9 are process diagrams illustrating a method of manufacturing a display substrate according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: display substrate 110: base substrate

120: gate insulating layer 131; Semiconductor layer

132: ohmic contact layer 150: passivation layer

TFT: thin film transistor PE: pixel electrode

PR1, PR2, PR3, PR4: first, second, third and fourth photoresist patterns

The present invention relates to a display substrate and a method for manufacturing the same, and more particularly, to a display substrate for improving the afterimage and a method for manufacturing the same.

In general, the liquid crystal display device includes a liquid crystal layer injected between the display substrate and the counter substrate. The liquid crystal layer is anisotropic dielectric constant, and the image is displayed by adjusting the amount of light transmitted by changing the arrangement according to the intensity of the electric field.

A plurality of gate lines parallel to each other and a plurality of data lines insulated from and intersecting with the gate lines are formed on the display substrate, and a pixel is formed in each area surrounded by the gate lines and the data lines. Each pixel is provided with a pixel electrode and a switching element for applying a pixel voltage to the pixel electrode.

The switching element is a gate electrode extending from the gate lines, an active layer insulated from the gate electrode and overlapping the gate electrode, a source electrode formed from the data line and electrically connected to the active layer and spaced apart from the source electrode and electrically connected to the active layer. And a drain electrode. These wirings and electrodes are patterned by a photolithography process using an exposure mask, and recently, a method of manufacturing a display substrate using four to three exposure masks has been proposed to reduce manufacturing costs.

 In the method for manufacturing a display substrate using four to three masks, the source / drain layer including the data line, the source electrode, and the drain electrode and the active layer are patterned using the same exposure mask.

That is, after the source / drain layer is patterned using one mask, the lower active layer is etched using the source / drain layer as an etching mask. In this case, the active layer is mainly etched by a dry etching process, and the dry etching process is anisotropic etching in which etching is performed only in a direction perpendicular to the substrate plane, and thus the active layer is more than a source / drain layer used as an etching mask. Etched to a wider width.

When the back light is irradiated on the active layer of the protruding portion rather than the side of the source / drain layer, the electron molecules are formed by breaking the bond between the silicon molecules in the active layer due to light energy, thereby forming an electron hole pair (eh pair). Photo leakage current flows even when the light is turned off, resulting in an afterimage on the display screen. In addition, since the active layer is formed wider than the source / drain layer, there is a problem that the aperture ratio in the pixel is reduced.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a method of manufacturing a display substrate for improving an afterimage and improving an aperture ratio.

Another object of the present invention is to provide a display substrate manufactured by the above-described method for manufacturing a display substrate.

According to an aspect of the present invention, there is provided a method of manufacturing a display substrate, including forming a first metal pattern including gate wirings and a gate electrode of a thin film transistor on the substrate; Sequentially forming a gate insulating layer, an active layer, and a photoresist film on the patterned substrate; patterning the photoresist film with a back exposure to form a photoresist pattern overlapping the first metal pattern; Etching the active layer using a photoresist pattern as an etch mask, removing the photoresist pattern, data wires crossing the gate lines on the substrate from which the photoresist pattern is removed, and Forming a second metal pattern including a source electrode and a drain electrode of the thin film transistor; Forming a pixel electrode electrically connected to the drain electrode on the substrate on which the second metal pattern is formed.

In accordance with another aspect of the present invention, a display substrate includes a first metal pattern, a gate insulating layer, a semiconductor layer, a second metal pattern, and a pixel electrode. The first metal pattern is formed on a substrate, and includes gate lines and a gate electrode of the thin film transistor. The gate insulating layer is formed on a substrate on which the first metal pattern is formed. The semiconductor layer overlaps the first metal pattern on the gate insulating layer. The second metal pattern is formed on a substrate on which the semiconductor layer is formed, and includes data lines crossing the gate lines and a source electrode and a drain electrode of the thin film transistor. The pixel electrode is electrically connected to the drain electrode.

According to such a display substrate and a manufacturing method thereof, it is possible to prevent the light leakage current due to the protrusion of the active layer and to improve the aperture ratio.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view of a display substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, the display substrate 100 includes a base substrate 110, a gate wiring, a data wiring, a storage wiring, a thin film transistor, a passivation layer, and a pixel electrode.

The base substrate 110 is formed of a material that can transmit light. In one example, the base substrate 110 is a glass substrate.

A first metal pattern is formed on the base substrate 110 including gate lines GL extending in parallel to each other and a gate electrode G of a thin film transistor TFT connected to the gate line GL.

The gate insulating layer 120 is formed on the base substrate 110 on which the first metal pattern is formed. The gate insulating layer 120 may be formed of, for example, silicon nitride (SiNx) or silicon oxide (SiOx). A second metal pattern including the data lines DL, the storage line STL, the source electrode S, and the drain electrode D of the thin film transistor TFT is formed on the gate insulating layer 120.

The data lines DL intersect the gate lines GL to define a plurality of unit pixels P. The storage line STL extends in a direction parallel to the gate lines GL between the gate lines GL.

The source electrode S protrudes from the data line DL and partially overlaps the gate electrode G. The drain electrode D is formed spaced apart from the source electrode S by a predetermined interval, and partially overlaps the gate electrode G.

Meanwhile, a semiconductor layer 131 patterned in the same manner as the first metal pattern is formed between the gate insulating layer 120 and the second metal pattern. In addition, an ohmic contact layer 132 is formed between the semiconductor layer 131 and the second metal pattern at an overlapping portion of the first metal pattern and the second metal pattern.

 The semiconductor layer 131 and the ohmic contact layer 132 stacked between the gate electrode G, the source electrode S, and the drain electrode D form an active layer A of a thin film transistor TFT. do.

The semiconductor layer 131 is made of, for example, amorphous silicon. In addition, the ohmic contact layer 132 is formed of, for example, amorphous silicon doped with a high concentration of n-type ions.

The passivation layer 150 is formed on the base substrate 110 on which the second metal pattern is formed. The passivation layer 150 may be formed of, for example, silicon nitride or silicon oxide.

In the passivation layer 150, a contact hole CH exposing one end of the drain electrode D is formed.

The pixel electrode PE is formed on the passivation layer 150 corresponding to each unit pixel P. The pixel electrode PE is formed of, for example, a transparent conductive material. As the transparent conductive material, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like may be used.

The pixel electrode PE is in electrical contact with the drain electrode D through the contact hole CH. Accordingly, the pixel electrode PE receives a pixel voltage from the thin film transistor TFT. The pixel electrode PE and the storage wiring STL form the storage capacitor Cst using the passivation layer 150 as a dielectric material. The storage capacitor Cst is charged with a pixel voltage for displaying an image for one frame.

Hereinafter, a method of manufacturing a display substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3 to 9.

1 and 3, a first metal layer (not shown) is coated on the base substrate 110. The first metal layer may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, or the like, and is deposited by a sputtering process. In addition, the first metal layer (not shown) may be formed of two or more layers having different physical properties.

Subsequently, a first photoresist film (not shown) is coated on the first metal layer. The first photoresist film is made of, for example, a positive photoresist in which an exposed region is dissolved by a developer. Next, a first mask MASK 1 including the light transmitting part 4 and the light blocking part 2 is disposed on the first photoresist film, and a photolithography using the first mask MASK 1 is performed. The first photoresist film is patterned by a photolithograph process to form a first photoresist pattern PR1.

Subsequently, the first metal pattern includes a gate line GL and a gate electrode G protruding from the gate line GL by etching the first metal layer by an etching process using the first photoresist pattern PR1. To form.

When the etching process for forming the first metal pattern is completed, the first photoresist pattern PR1 is removed by a strip process using a strip solution.

In FIG. 3, the first metal layer is patterned by using a positive photoresist in which the exposed region is dissolved by a developer. However, the first photoresist layer is a negative photoresist in which an unexposed region is dissolved by a developer. It may be done. In this case, the positions of the light transmitting portion and the light blocking portion of the first mask MASK1 are reversed.

Referring to FIG. 4, the gate insulating layer 120, the semiconductor layer 131, and the ohmic contact layer 132 are successively formed on the base substrate 110 on which the first metal pattern is formed. The gate insulating layer 120, the semiconductor layer 131, and the ohmic contact layer 132 may be formed by a chemical vapor deposition method.

For example, the gate insulating layer 120 may be formed of silicon nitride or silicon oxide. The semiconductor layer 131 may be formed of, for example, amorphous silicon. The ohmic contact layer 132 may be formed of, for example, amorphous silicon doped with a high concentration of n-type ions.

Next, a second photoresist film PL is formed on the ohmic contact layer 132.

Subsequently, the second photoresist film PL is exposed using light irradiated from the rear surface of the base substrate 110. In this case, the first metal pattern formed on the base substrate 110 functions as an exposure mask. Accordingly, when the exposed second photoresist film PL is developed, a second photoresist pattern PR2 patterned in the same shape as the first metal pattern is formed as illustrated in FIG. 5.

Referring to FIG. 5, the ohmic contact layer 132 and the semiconductor layer 131 are sequentially etched using the second photoresist pattern PR2. Etching of the ohmic contact layer 132 and the semiconductor layer 131 may be a dry etching process.

Accordingly, the active layer A including the resistive contact layer 132 and the semiconductor layer 131 patterned in the same manner as the first metal pattern is formed on the gate insulating layer 120. When the etching process for forming the active layer A is finished, a strip process for removing the second photoresist pattern PR2 is performed.

1 and 6, a second metal layer (not shown) is formed on the base substrate 110 on which the active layer A is formed. The second metal layer may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, an alloy thereof, or the like, and is deposited by a sputtering process. In addition, the second metal layer (not shown) may be formed of two or more layers having different physical properties.

Subsequently, after forming a third photoresist film (not shown) on the second metal layer, the third photoresist film (not shown) is patterned by a photolithography process using a third mask MASK3 to form a third photoresist film. The resist pattern PR3 is formed.

Next, the second metal layer is etched by an etching process using the third photoresist pattern PR3 to include a data line DL, a source electrode S, a drain electrode D, and a storage line STL. A second metal pattern is formed.

Referring to FIG. 7, the ohmic contact layer 132 of the active layer A exposed on the base substrate 110 is etched using the second metal pattern as an etching mask. The etching of the ohmic contact layer 132 may be performed by, for example, a dry etching process.

Accordingly, in the region where the first metal pattern and the second metal pattern overlap, the active layer A having the structure in which the semiconductor layer 131 and the ohmic contact layer 132 are stacked remains, and the first except Only the semiconductor layer 131 remains on the metal pattern.

Therefore, the semiconductor layer 131 is exposed at the spaced portion between the source electrode S and the drain electrode D. FIG. The semiconductor layer 131 exposed from the source electrode S and the drain electrode D forms an electrical channel portion CH between the source electrode S and the drain electrode D. FIG.

Accordingly, the thin film transistor TFT including the gate electrode G, the source electrode S, the drain electrode D, and the active layer A is formed on the base substrate 110.

In the conventional four-sheet mask process, since the second metal pattern and the active layer are patterned using the same photoresist pattern, a slit (SLIT) exposure is used to form the channel. However, according to the embodiment of the present invention, since the second metal pattern and the active layer A are patterned by using a separate photoresist pattern, a channel portion between the source electrode S and the drain electrode D is compared with the conventional art. It is easy to form (CH).

Referring to FIG. 8, a passivation layer 150 is formed on the base substrate 110 on which the thin film transistor TFT is formed. The passivation layer 150 may be formed of, for example, silicon nitride or silicon oxide, and may be formed by a chemical vapor deposition method.

Subsequently, a third photoresist film (not shown) is coated on the base substrate 110 on which the passivation layer 150 is formed, and the third photoresist film is patterned by a photolithography process using a third mask MASK3. 3 Photoresist pattern PR3 is formed. Next, the passivation layer 150 is patterned by an etching process using the third photoresist pattern PR3 to form a contact hole CH exposing one end of the drain electrode D. FIG.

When the etching process for forming the contact hole CH is completed, the strip process of removing the third photoresist pattern PR3 is performed.

1 and 9, a transparent electrode layer (not shown) is formed on the passivation layer 150 in which the contact hole CH is formed. The transparent electrode layer may be formed of, for example, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like, and may be deposited by a sputtering method.

Subsequently, the fourth photoresist layer is coated on the transparent electrode layer, and the fourth photoresist layer is patterned by a photolithography process using a fourth mask MASK4 to form a fourth photoresist pattern PR4.

Next, the transparent electrode layer is patterned by an etching process using the fourth photoresist pattern PR4 to form the pixel electrode PE corresponding to the unit pixel P.

The pixel electrode PE contacts the drain electrode D through the contact hole CH, and overlaps the storage wiring STL with the passivation layer 150 therebetween to form a storage capacitor Cst. Form. As a result, the display substrate 100 according to the exemplary embodiment of the present invention is completed.

As described above, according to the present invention, an active layer overlapping the first metal pattern is formed through the back exposure. Therefore, it is possible to prevent the formation of active layer protrusions caused by anisotropic etching using the source / drain layer as an etching mask in a conventional four to three mask process. As a result, the light leakage current generated by the irradiation of light to the protrusions can be suppressed, and the aperture ratio in the unit pixel can be improved.

As described above, according to the present invention, by forming the active layer overlapping the first metal pattern through the back exposure, it is possible to prevent the formation of the active protrusion generated in the conventional four to three mask process. As a result, the light leakage current generated by the irradiation of light to the protrusions can be suppressed, and the aperture ratio in the unit pixel can be improved. In addition, since the second metal pattern including the source / drain electrodes and the active layer are formed using separate exposure masks, it is possible to facilitate formation of a channel portion between the source electrode and the drain electrode.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (9)

Forming a first metal pattern including gate wirings and a gate electrode of the thin film transistor on the substrate; Sequentially forming a gate insulating layer, an active layer, and a photoresist film on the substrate on which the first metal pattern is formed; Patterning the photoresist film with a back exposure to form a photoresist pattern overlapping the first metal pattern; Etching the active layer using the photoresist pattern as an etching mask; Removing the photoresist pattern; Forming a second metal pattern including data lines crossing the gate lines and a source electrode and a drain electrode of the thin film transistor on the substrate from which the photoresist pattern is removed; And Forming a pixel electrode electrically connected to the drain electrode on the substrate on which the second metal pattern is formed. The method of claim 1, wherein the active layer is formed by sequentially stacking a semiconductor layer and an ohmic contact layer. The method of claim 2, further comprising etching the ohmic contact layer using the second metal pattern as an etching mask. The method of claim 1, further comprising forming a passivation layer between the second metal pattern and the pixel electrode. The display substrate of claim 4, wherein the forming of the second metal pattern further comprises forming a storage line between the gate lines and extending in a direction parallel to the gate lines. Manufacturing method. A first metal pattern formed on the substrate, the first metal pattern including gate lines and a gate electrode of the thin film transistor; A gate insulating layer formed on the substrate on which the first metal pattern is formed; A semiconductor layer overlapping the first metal pattern on the gate insulating layer; A second metal pattern formed on the substrate on which the semiconductor layer is formed and including data lines crossing the gate lines and a source electrode and a drain electrode of the thin film transistor; And And a pixel electrode electrically connected to the drain electrode. The display substrate of claim 6, further comprising an ohmic contact layer formed between the semiconductor layer and the second metal pattern and formed on an overlapping portion of the semiconductor layer and the second metal pattern. The display substrate of claim 6, wherein the second metal pattern further comprises a storage line extending in parallel with the gate lines between the gate lines. The display substrate of claim 6, further comprising a passivation layer formed between the second metal pattern and the pixel electrode.

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