KR20080006887A - Method of driving discharge display panel whose potential of display-data pulses is changed - Google Patents

Abstract

The present invention provides a method of driving a discharge display panel in which a unit frame is divided into a plurality of subfields, each of which is divided into a reset period, an addressing period, and a sustain period, wherein steps (a) to (d) are performed. It includes.

In step (a), a main reset discharge occurs in the reset period of at least one subfield among the plurality of subfields. In step (b), an auxiliary reset discharge, which is weaker than the main reset discharge, occurs in each of the reset periods of the subfields other than the subfield in which the main reset discharge occurs. In step (c), display-data pulses of the first address potential are applied to the selected display cells in the addressing period of the subfield causing the main reset discharge. In step (d), display-data pulses of a second address potential higher than the first address potential in the addressing period of the subfield causing the auxiliary reset discharge are applied to the selected display cells.

Description

Method for driving discharge display panel where electric-potential of display-data pulses varies

1 is an internal perspective view showing a structure of a three-electrode surface discharge plasma display panel as a discharge display panel driven by an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating an example of one display cell of the plasma display panel of FIG. 1.

3 is a block diagram illustrating an apparatus for driving the plasma display panel of FIG. 2 according to an exemplary embodiment of the present invention.

4 is a timing diagram illustrating a method of driving the plasma display panel of FIG. 1 by the driving apparatus of FIG. 3.

FIG. 5 is a waveform diagram illustrating driving signals applied to the plasma display panel of FIG. 1 in at least one subfield SF _A among the subfields of FIG. 4.

FIG. 6 is a waveform diagram illustrating another driving signals applied to the plasma display panel of FIG. 1 in at least one subfield SF _B of the subfields of FIG. 4.

FIG. 7 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t ₅ of FIG. 5.

8 is a cross-sectional view showing the wall charge distribution of any of the display cells at the time point t ₈ in FIG.

FIG. 9 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t ₄ of FIG. 6.

FIG. 10 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t ₇ of FIG. 6.

FIG. 11 is a diagram illustrating an example in which the subfield type SF _A of FIG. 5 or the subfield type SF _B of FIG. 6 is applied to each subfield of the unit frame of FIG. 4.

<Explanation of symbols for the main parts of the drawings>

1 ... discharge display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., Xn ... X electrode-line, Y ₁ , ..., Yn ... Y electrode-line,

A _R1 , ..., A _Bm ... address electrode-line, X _na , Y _na ... transparent electrode-line,

X _nb , Y _nb ... metal electrode-line, SF ₁ , ... SF ₈ ... subfield,

S _Y ... Y drive control signal, V _G ... ground potential,

S _X ... X drive control signal, S _A ... address drive control signal,

62 control unit, 63 address drive unit,

64 ... X drive, 65 ... Y drive,

66 ... Image processing unit, A ₁ , ..., A ₈ ... addressing cycle.

The present invention relates to a method of driving a discharge display panel, and more particularly, to a discharge display in which a unit frame is divided into a plurality of subfields, each of which is divided into a reset period, an addressing period, and a sustain period. It relates to a driving method of the panel.

In a typical discharge display device, for example, the plasma display device of US Pat. No. 5,541,618, a unit frame is divided into a plurality of subfields for time division gray scale display, and each of the subfields is a reset period, an addressing period, and a sustain period. It includes. Each of the subfields has a unique gray scale weight value, and a maintenance period is set in proportion to the gray scale weight value.

In the reset period, a continuous and strong discharge is used to make the charge state of all display cells uniform. Therefore, the reset period may be a factor that degrades the contrast performance of the discharge display apparatus.

In this regard, when the unit frame is divided into first to n-th subfields according to the order of low gray scale weight values, only the second and / or third subfields of the unit frame may be used to improve contrast performance of the discharge display apparatus. There is a way to apply a strong reset discharge.

Here, the reason for applying the main reset discharge which is the strong discharge only to the second and / or third subfields having the low gray scale weight value is that the number of sustain pulses in the first or second subfield, which is the previous subfield, is small. This is because a weak addressing discharge may occur due to the lack of space charges in the next or second subfield.

However, in each of the other subfields, as the weak reset discharge is applied, as the unstable address discharge occurs in the selected display cells, reproducibility of the display image may be deteriorated.

An object of the present invention is to provide a method of driving a discharge display panel which can improve contrast performance and also improve reproducibility of display images.

In order to achieve the above object, the present invention provides a method of driving a discharge display panel in which a unit frame is divided into a plurality of subfields, and each of the subfields is divided into a reset period, an addressing period, and a sustain period. ) To (d).

In the step (a), a main reset discharge occurs in a reset period of at least one subfield among the plurality of subfields. In the step (b), the auxiliary reset discharge which is weaker than the main reset discharge occurs in each of the reset periods of the subfields other than the subfield in which the main reset discharge occurs. In the step (c), display-data pulses of the first address potential are applied to the selected display cells in the addressing period of the subfield causing the main reset discharge. In step (d), display-data pulses of a second address potential higher than the first address potential are applied to the selected display cells in the addressing period of the subfield causing the auxiliary reset discharge.

According to the driving method of the discharge display panel of the present invention, as the auxiliary reset discharge is employed together with the main reset discharge, the contrast performance of the discharge display apparatus can be increased. In addition, since the potential of the display-data pulses increases in the addressing period of the subfield causing the auxiliary reset discharge, a more stable address discharge may occur despite the weak reset discharge. That is, the reproducibility of the display image may be increased.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

1 shows a structure of a three-electrode surface discharge plasma display panel 1 as a discharge display panel driven by one embodiment of the present invention. FIG. 2 shows an example of one display cell of the plasma display panel 1 of FIG. 1.

1 and 2, between the front and rear glass substrates 10 and 13 of the three-electrode surface discharge plasma display panel 1 according to an embodiment of the present invention, the address electrode lines A _{R1 are described.} To A _Bm ), dielectric layers 11 and 15, X electrode-lines X ₁ to X _n as sustain electrode-lines, Y electrode-lines as scan electrode-lines (Y ₁₎ To Y _n ), the phosphor 16, the partition 17, and the magnesium monoxide (MgO) layer 12 as a protective layer are provided.

Address electrode-lines A _R1 To A _Bm ) are formed in a predetermined pattern on the front side of the rear glass substrate 13. Lower dielectric layer 15 has address electrode lines A _R1. To A _Bm ) in front of the entire surface. In front of the lower dielectric layer 15, barrier ribs 17 are formed on the address electrode lines A _R1. To A _Bm ). These partitions 17 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The fluorescent layer 16 is applied between the partition walls 17.

X electrode-lines (X ₁₎ as sustain electrode-lines To X _n ) and Y electrode-lines Y ₁ as scan electrode-lines To Y _n are the address electrode-lines A _R1 To A _Bm ) are formed alternately and side by side at the rear of the front glass substrate 10 in a direction intersecting with. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ To Xn) and each Y electrode line (Y _1). To Y _n ) is a transparent electrode-line (X _na , Y _na of FIG. 3) of a transparent conductive material such as indium tin oxide (ITO), etc. and a metal electrode-line (X _nb , Y _nb of FIG. 3) to increase conductivity. Is formed by combining. The front dielectric layer 11 has X electrode-lines X ₁ To X _n ) and Y pole-lines (Y ₁₎ To Y _n ), the entire surface is applied and formed. A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

In the driving method applied to such a discharge display panel, reset, addressing, and discharge-sustaining cycles are sequentially performed in the unit subfield. In the reset period, the charge states of all display cells are uniform. In the addressing period, a predetermined wall potential is generated in the selected display cells. In the sustain period, a predetermined alternating voltage is applied to all the XY electrode-line pairs so that the display cells in which the wall potential is formed in the addressing period cause sustain discharge. In this sustain period, plasma is formed in the discharge space 14 of the selected display cells, that is, the gas layer, which causes the sustain discharge, and the fluorescent layer 16 is excited by the ultraviolet radiation to generate light.

Referring to FIG. 3, an apparatus for driving the plasma display panel 1 of FIG. 1 according to an exemplary embodiment of the present invention may include an image processor 66, a controller 62, an address driver 63, and an X driver 64. , And the Y driver 65.

The image processing unit 66 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals.

The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 66.

The address driver 63 processes the address signals S _A among the drive control signals S _A , S _Y , and S _X from the controller 62 to generate display data signals, and generates the generated display signals. Data signals to address electrode-lines (A _R1 of FIG. 2). To A _Bm ). The X driver 64, an X driving signal from the driving control signal from the control unit (62) (S _A, S _Y, S _X) maintained in accordance with the (S _X) electrode - of as line X electrode lines ( X ₁ to X _n ) of FIG. 2 are driven. The Y driver 65 is connected to the Y electrode lines as scan electrode lines according to the Y drive control signal S _Y among the drive control signals S _A , S _Y , and S _X from the controller 62 (FIG. 2, Y ₁ To Y _n ).

4 illustrates a method in which the plasma display panel 1 of FIG. 1 is driven by the driving apparatus of FIG. 3.

Referring to FIG. 4, each of the unit frames has eight subfields SF ₁ according to the order in which the gray scale weights are low in order to realize time division gray scale display. To SF ₈ ). In addition, each subfield SF ₁ To SF ₈ ) is a reset period R _1. To R ₈ ), the addressing period A ₁ to A ₈ , and the sustaining period S ₁ To S ₈ ).

The discharge conditions of all display cells are each reset period R_One To R₈) And at the same time it is suitable for addressing to be performed in the next cycle.

In each addressing period A ₁ to A ₈ , the address electrode-lines (A _{R1 in} FIG. 1) To A _Bm ) and a display-data signal is applied to each Y electrode line Y _1. To Y _n ) are sequentially applied. Accordingly, when a high level display-data pulse is applied while the scan pulse is applied, wall charges are formed by the addressing discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

Each maintenance cycle (S ₁ To S ₈ , all Y electrode-lines Y ₁ To Y _n ) and all X electrode-lines (X ₁₎ To X _n ), a sustain pulse is alternately applied, causing sustain discharge in the discharge cells in which wall charges were formed in the corresponding addressing periods A ₁ to A ₈ . Therefore, the sustain period (S ₁₎ of the output luminance of one display cell occupies a unit frame. To S ₈ ). In the present embodiment, the maintenance period occupies in the unit frame (S ₁ To S ₈ ) has a length of 255T (T is a unit period). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, the first sustain period of a subfield (SF ₁₎ (S ₁₎ is equivalent to include two ^first sustain period (S ₂₎ of a period (1T) which corresponds to ^20, the second sub-field (SF ₂₎ In the sustain period S ₃ of the third subfield SF ₃ , a period 4T corresponding to 2 ² is included in the sustain period S ₄ of the fourth subfield SF ₄ . The period 8T corresponding to 2 ³ has a period 16T corresponding to 2 ⁴ in the sustain period S ₅ of the fifth subfield SF ₅ , and the sustain period of the sixth subfield SF ₆ . S ₆ ) includes a period 32T corresponding to 2 ⁵ , a sustain period S ₇ of the seventh subfield SF ₇ includes a period 64T corresponding to 2 ⁶ , and an eighth subfield SF _8. The period 128T corresponding to 2 ⁷ is set in each of the sustain periods S ₈ ).

Accordingly, eight subfields SF ₁ From SF ₈ ), if a subfield to be displayed is appropriately selected, display of 256 gray levels may be performed including all zero (zero) gray levels that are not displayed in any subfields.

On the other hand, the main reset discharge occurs in the reset period of at least one subfield (see Fig. 5). Further, in each of the reset periods of the subfields in which the main reset discharge does not occur, the auxiliary reset discharge weaker than the main reset discharge occurs (see FIG. 6). The potential of the display-data pulses is lowered in the addressing period of the subfield causing this auxiliary reset discharge (see FIGS. 5 and 6).

Therefore, since the auxiliary reset discharge is employed together with the main reset discharge, the contrast performance of the plasma display device can be increased. In addition, since the potential of the display-data pulses is high in the addressing period of the subfield causing the auxiliary reset discharge, a more stable addressing discharge may occur despite the weak reset discharge. That is, the reproducibility of the display image may be increased. This is described in detail below.

FIG. 5 shows the subfields SF ₁ of FIG. To SF ₈ ) show driving signals used in at least one subfield SF _A.

In FIG. 5, reference numeral S _{AR1 .. ABm} denotes each address electrode-line (A _R1 of FIG. 1). To A _Bm ). S _{X1 .. Xn} is X electrode-lines (X ₁ of FIG. ₁₎ To X _n ). S _Y1 To S _Yn is each Y electrode-line (Y ₁ of FIG. 1). To Y _n ).

FIG. 7 illustrates a wall charge distribution of one display cell at time t ₅ of FIG. 5. Figure 8 shows the wall charge distribution of any of the display cells at the time point t ₈ in FIG. 7 and 8, the same reference numerals as used in FIG. 2 indicate the objects of the same function.

Referring to FIG. 5, the subfields SF ₁ of FIG. 4. To SF ₈₎ in at least one of sub-fields (in the reset period (R _A) of the SF _A), the wall charge accumulating period (t1 ~ t5) among, Y electrode lines (Y ₁ To Y _n ), the potential applied from the ground potential V _G to the third potential | V _SCL The first positive potential V _SET as the highest potential higher by the sixth potential V _SET than V _SCH | + | V _SCL -V _SCH |) For example, it is raised to 355 volts (V). Positive third potential (| V _SCL V _SCH | is generated by the difference between the negative second potential V _SCL and the negative fourth potential V _SCH .

X electrode-lines (X ₁ To X _n ) and address electrode-lines A _R1 To A _Bm ), the ground potential V _G is applied.

Accordingly, Y electrode-lines Y ₁ To Y _n ) and the X electrode-lines (X ₁₎ To X _n ), while discharge occurs between Y electrode-lines Y _1. To Y _n ) and address electrode-lines A _R1 To A _Bm ). Accordingly, all Y electrode-lines Y ₁ To Y _n ), negative wall charges are formed and all X electrode-lines (X ₁ ) are formed. To X _n ), positive wall charges are formed, and all address electrode-lines A _R1. To A _Bm ), positive wall charges are formed (see FIG. 7).

Next, the subfields SF ₁ of FIG. X SF electrode-lines X _{1 in the} wall charge distribution period t5 to t8 in the reset period R _A of at least one subfield SF _A from SF ₈ ). To Y _n , the Y electrode-lines Y ₁ in the state where the potential applied to the fifth potential V _E1 is maintained at the fifth potential V _E1 . To potential applied to Y _n is the first potential V _SET. + ｜ V _SCL From V _SCH | to the second negative potential V _SCL . Here, address electrode-lines A _R1 To A _Bm ), the ground potential V _G is applied. Accordingly, X electrode-lines X ₁ To X _n ) and the Y electrode-lines Y ₁ To due to the discharge between the Y _n), Y electrode lines (Y ₁ To Y _n , some of the negative wall charges around the X electrode-lines (X _1). To X _n ), as appropriate (see FIG. 8). In addition, address electrode-lines A _R1 To A _Bm , the ground potential V _G is applied, and therefore, the address electrode lines A _R1 To A _Bm ), the positive wall charges around them are appropriately reduced (see FIG. 8).

Accordingly, in the following addressing period A _A , the address electrode-lines A _R1 To A _Bm ), the Y-electrode lines Y ₁ , to which display-data signals S _{AR1 .. ABm} are applied and biased to the negative fourth potential V _SCH . To Y _n ), as the scan pulses of the negative second potential V _SCL are sequentially applied, smooth addressing may be performed.

Each address electrode line (A _R1) To A _Bm ), the first address potential V _AA of positive polarity is applied when the display cell is selected, and the ground potential V _G is applied otherwise. Accordingly, when the display-data pulses of the first polarity of the first address potential V _AA are applied while the scan pulse of the second polarity of the negative potential V _SCL is applied, the set potential is caused by addressing discharge in the corresponding display cells. The above wall potential is formed, and in other display cells, no wall potential above the set potential is formed. Here, X electrode-lines X ₁ so that the X electrodes of selected display cells are not affected by the addressing discharge. To X _n ), the positive fifth potential V _E1 is applied.

In the sustain period S, all Y electrode-lines Y ₁ To Y _n ) and the X electrode-lines (X ₁₎ To X _n ), sustain pulses of positive seventh potential V _S are alternately applied, causing sustain discharge in display cells in which wall potentials above the set potential were formed in the corresponding addressing period A _A.

6 is a view of the figures, the four sub-fields 5 sub-fields different sub-field other than the (SF _A) (SF _B) That is, the drive signal used in the sub-reset period (R _B) sub-field (SF _B) applying the Show them.

In FIG. 6, the same reference numerals as used in FIG. 5 indicate objects of the same function. 9 illustrates a wall charge distribution of one display cell at time t ₄ of FIG. 6. FIG. 10 illustrates a wall charge distribution of one display cell at time t ₇ of FIG. 6. 9 and 10, the same reference numerals as used in FIG. 2 indicate objects of the same function.

Referring to FIG. 6, in the auxiliary reset period R _B of the subfield SF _B other than the subfield SF _A of FIG. 5, in the wall charge accumulation period t1 to t4, the Y electrode-line (Y ₁ To Y _n ) is raised from the ground potential V _G to the seventh potential V _S of the positive polarity. Also, X electrode-lines (X ₁₎ To X _n ) and address electrode-lines A _R1 To A _Bm ), the ground potential V _G is applied.

Accordingly, in the display cells selected in the previous subfield to perform sustain discharge, a discharge occurs between the Y electrodes and the X electrodes, while a discharge occurs between the Y electrodes and the address electrodes. Accordingly, negative wall charges are formed around the Y electrodes, positive wall charges are formed around the X electrodes, and positive wall charges are formed around the address electrodes (see FIG. 9).

Next, in the auxiliary reset period R _B of the subfield SF _B other than the subfield SF _A of FIG. 5, in the wall charge distribution period t4 to t7, the X electrode-lines X _One To X _n ), the positive fifth potential V _E is applied, and the address electrode lines A _R1. To from a ground potential (V _G) applied to the state A _Bm), Y electrode lines (Y ₁ To Y _n ) is lowered from the seventh potential V _S to the second negative potential V _SCL of the negative polarity.

Accordingly, in the display cells selected in the previous subfield to perform sustain discharge, the Y electrode-lines Y ₁ due to the discharge between the X electrodes and the Y electrodes. To Y _n ) some of the negative wall charges around move properly around the X electrode-lines X ₁ to X _n (see FIG. 11). In addition, address electrode-lines A _R1 To A _Bm ), since the ground potential V _G is applied, the address electrode lines A _R1. To A _Bm ), the positive wall charges around them are appropriately reduced (see FIG. 10).

In the following addressing period A _B , the address electrode-lines A _R1 To A _Bm ), the Y-electrode lines Y ₁ , to which display-data signals S _{AR1 .. ABm} are applied and biased to the negative fourth potential V _SCH . To Y _n ), as the scan pulses of the negative second potential V _SCL are sequentially applied, smooth addressing may be performed.

Each address electrode line (A _R1) To A _Bm ), the second address potential V _AB having a higher polarity than the first address potential V _AA (see FIG. 5) when the display cell is selected is selected. Otherwise, the ground potential V _G is applied.

Accordingly, when the display-data pulses of the positive second address potential V _AB are applied while the scan pulse of the second negative potential V _SCL is applied, the set potential is set by addressing discharge in the corresponding display cells. The above wall potential is formed, and in other display cells, no wall potential above the set potential is formed. Here, X electrode-lines X ₁ so that the X electrodes of selected display cells are not affected by the addressing discharge. To X _n ), the positive fifth potential V _E1 is applied.

The maintenance period S is as described with reference to FIG. 5.

Since the above description, the main reset discharge (see R _B of FIG. 6) (see R in Fig. 5 _A), the auxiliary reset discharge with the adopted as described, can increase the contrast performance of the plasma display device. In addition, since the address potential becomes high in the addressing period A _B of the subfield SF _B causing the auxiliary reset discharge, a more stable addressing discharge may occur despite the weak reset discharge. That is, the reproducibility of the display image may be increased.

FIG. 11 shows an example in which the subfield type SF _A of FIG. 5 or the subfield type SF _B of FIG. 6 is applied to each subfield of the unit frame of FIG. 4. Referring to FIG. 11, the subfield type SF _A of FIG. 5 is applied to the second subfield SF ₂ and the third subfield SF ₃ of the unit frame of FIG. 4, and the remaining subfields of FIG. The subfield type SF _B of 6 is applied.

As described above, according to the driving method of the discharge display panel according to the present invention, as the secondary reset discharge is employed together with the main reset discharge, the contrast performance of the discharge display apparatus can be increased. In addition, since the potential of the display-data pulses increases in the addressing period of the subfield causing the auxiliary reset discharge, a more stable address discharge may occur despite the weak reset discharge. That is, the reproducibility of the display image may be increased.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (7)

A method of driving a discharge display panel in which a unit frame is divided into a plurality of subfields, and each of the subfields is divided into a reset period, an addressing period, and a sustain period. (a) causing a main reset discharge in a reset period of at least one of the plurality of subfields; (b) causing an auxiliary reset discharge weaker than the main reset discharge in each of the reset periods of the subfields other than the subfield in which the main reset discharge occurs; (c) applying display-data pulses of a first address potential to selected display cells in an addressing period of a subfield causing said main reset discharge; And and (d) applying display-data pulses of a second address potential higher than the first address potential to selected display cells in an addressing period of the subfield causing the auxiliary reset discharge. The method of claim 1, In the discharge display panel, Between the front and rear substrates spaced apart from each other, the sustain electrode lines and the scan electrode lines are formed alternately and side by side, and the address electrode lines are formed to intersect with respect to the sustain and scan electrode lines. , In steps (c) and (d) above, And the display data pulses are applied to the selected address electrode lines while the scan pulses are sequentially applied to each of the scan electrode lines. The method of claim 2, And a reset period of the subfields causing the main reset discharge in the step (a) includes a wall charge accumulation period and a wall charge distribution period. The method of claim 3, In the wall charge accumulation period included in the reset period in the step (a), the potential applied to the scan electrode-lines is raised to the first potential of positive polarity, In the wall charge distribution period included in the reset period in the step (a), the potential applied to the scan electrode lines decreases from the first positive potential to the second negative potential of the discharge display panel. Driving method. The method of claim 4, wherein in the holding period And sustain pulses having a positive seventh potential lower than the first positive potential are alternately applied to the sustain electrode lines and the scan electrode lines. The method of claim 5, And the reset period of the subfield causing the auxiliary reset discharge in the step (b) includes a wall charge accumulation period and a wall charge distribution period. The method of claim 6, In the wall charge accumulation period included in the reset period in the step (b), the potential applied to the scan electrode-lines is raised to the seventh potential of the positive polarity, In the wall charge distribution period included in the reset period in the step (b), the discharge display panel in which the potential applied to the scan electrode lines falls from the seventh potential of the positive electrode to the second potential of the negative electrode Method of driving.

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