KR20070121112A - Liquid crystal display - Google Patents

Abstract

An LCD is provided to improve the response speed by suppressing an instant afterimage, and regulate the areas of respective sub-pixel electrodes easily by improving the side visibility effectively. A first sub-pixel electrode(191a) includes a first segment(191a1) having a first oblique side, a second segment(191a2) having a second oblique side, and a third segment(191a3) having first, second, and third oblique sides. A second sub-pixel electrode(191b) is disposed among the first, second, and third segments. The first sub-pixel electrode and the second sub-pixel electrode constitute a pixel electrode(191). A common electrode faces the pixel electrode, wherein the common electrode has a first cut-out portion. The third segment of the first sub-pixel electrode is divided into two regions by the first cut-out portion of the common electrode.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a lower panel for a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a layout view of an upper panel for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a layout view of a liquid crystal display including the lower panel of FIG. 3 and the upper panel of FIG. 4.

6 and 7 are cross-sectional views of the liquid crystal display shown in FIG. 5 taken along the lines VI-VI and VIII-VIII, respectively.

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which an electric field generating electrode such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode.

Among such liquid crystal display devices, a liquid crystal display device having a vertically aligned mode in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the liquid crystal display device is gaining attention due to its large contrast ratio and wide reference viewing angle. . Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Specific methods for implementing a wide reference viewing angle in a vertical alignment liquid crystal display include a method of forming an incision in the field generating electrode and a method of forming protrusions on or under the field generating electrode. Since the cutout and the protrusion determine the tilt direction of the liquid crystal molecules, the reference viewing angle can be widened by appropriately arranging them to disperse the inclined directions of the liquid crystal molecules in various directions.

In the liquid crystal display, since portions having protrusions or cutouts are difficult to transmit light, the larger the number, the lower the aperture ratio. In order to increase the aperture ratio, an ultra-high opening ratio structure in which a pixel electrode is widened is proposed. However, in this case, the distance between the pixel electrodes is close and the distance between the pixel electrode and the data line is also close, so that a strong lateral field is formed near the edge of the pixel electrode. Due to this lateral electric field, the alignment of the liquid crystal molecules is disturbed, resulting in texture or light leakage and a long response time.

In addition, the liquid crystal display of the vertical alignment mode is less lateral visibility than the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in severe cases, the luminance difference between the high grays is disappeared, and the picture may be clumped.

The technical problem to be achieved by the present invention is to improve the response speed of the liquid crystal display device and to improve the side visibility.

A liquid crystal display device according to an exemplary embodiment of the present invention is a liquid crystal display device including a plurality of pixels, the first piece including a first hypotenuse, the second piece including a second hypotenuse, and the first side and the second. A first subpixel electrode including a third piece of a triangular shape including sides and a third side, and a second part disposed between the first to third pieces and forming a pixel electrode together with the first subpixel electrode And a common electrode facing the pixel electrode, the pixel electrode, and including a first cutout, wherein the third piece is divided into two regions by the first cutout.

The first piece, the second piece and the third piece may be electrically connected to each other.

The common electrode may further include a second cutout overlapping the first hypotenuse and a third cutout overlapping the second hypotenuse.

The first subpixel electrode and the second subpixel electrode may be capacitively coupled.

The thin film transistor may further include a thin film transistor connected to the first subpixel electrode, a gate line connected to the thin film transistor, and a data line connected to the thin film transistor and intersecting the gate line.

Each of the first hypotenuse and the second hypotenuse may form an angle of 45 degrees with the gate line, and the first hypotenuse and the second hypotenuse may form an angle of 90 degrees with each other.

The first hypotenuse and the first side may be parallel to each other, the second hypotenuse may be parallel to the second side, and the third side may be parallel to the data line.

The pixel may be divided into eight sub-regions.

The common electrode may further include a fourth cutout dividing the second subpixel electrode into two regions.

An area ratio of the area of the first subpixel electrode and the second subpixel electrode may be 1: 1 to 1: 3.

The voltage difference ratio between the first subpixel electrode and the common electrode and the voltage difference between the second subpixel electrode and the common electrode may be 1: 0.5 to 1: 0.9.

DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a pair of subpixels PEa and PEb. Each of the subpixels PEa and PEb includes a switching element Q connected to signal lines GL and DL, first and second liquid crystal capacitors Clca and Clcb, and a storage capacitor connected thereto. Cst) and a coupling capacitor Ccp connected between the two subpixels PEa and PEb. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100. The control terminal is connected to the gate line GL, and the input terminal is connected to the data line DL. The output terminal is connected to the first and second liquid crystal capacitors Clca and Clcb, the storage capacitor Cst, and the storage capacitor Ccp.

The switching element Q applies the data voltage from the data line DL to the first liquid crystal capacitor Clca and the coupling capacitor Ccp according to the gate signal from the gate line GL, and the coupling capacitor Ccp This voltage is changed in magnitude to pass to the second liquid crystal capacitor Clcb.

The liquid crystal capacitor Clca / Clcb has two terminals of the subpixel electrode PEa / PEb of the lower panel 100 and the common electrode CE of the upper panel 200, and the subpixel electrodes PEa / PEb and the common electrode. The liquid crystal layer 3 between (CE) functions as a dielectric. The pair of subpixel electrodes PEa and PEb are separated from each other and form one pixel electrode PE. The common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom. The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

The storage capacitor Cst, which serves as an auxiliary role of the liquid crystal capacitor Clc, is formed by overlapping a separate storage electrode line SL and a pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the signal line of. However, the storage capacitor Cst may be formed such that the pixel electrode PE overlaps the front gate line directly above the insulator.

If the common voltage Vcom is applied to the storage capacitor Cst, and the capacitors Clca, Clcb, Cst, and Ccp are represented by the same reference numerals, the voltage Va charged in the first liquid crystal capacitor Clca is applied. And the voltage Vb charged in the second liquid crystal capacitor Clcb have the following relationship.

Vb = Va ㅧ [Ccp / (Ccp + Clcb)]

Since the value of Ccp / (Ccp + Clcb) is less than 1, the voltage Vb charged in the second liquid crystal capacitor Clcb is always smaller than the voltage Va charged in the first liquid crystal capacitor Clca. This relationship holds true even when the voltage applied to the holding capacitor Cst is not the common voltage Vcom.

An appropriate ratio of the first liquid crystal capacitor Clca voltage Va and the second liquid crystal capacitor Clcb voltage Vb can be obtained by adjusting the capacitance of the coupling capacitor Ccp.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. 2 illustrates that each pixel PX includes a color filter CF representing one of the primary colors in an area of the upper panel 200 as an example of spatial division. Unlike FIG. 2, the color filter CF may be formed above or below the subpixel electrodes PEa and PEb of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed of a combination of the gate on voltage Von and the gate off voltage Voff. ₁ -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the structure of the liquid crystal panel assembly will be described in detail with reference to FIGS. 3 to 7, and FIGS. 1 and 2 described above.

3 is a layout view of a lower panel for a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 4 is a layout view of an upper panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a lower panel of FIG. 3. And a top view of the liquid crystal display device including the upper display panel of FIG. 4, and FIGS. 6 and 7 are cross-sectional views illustrating the liquid crystal display device shown in FIG. 5 along the VI-VI and VIII-V lines, respectively.

3 to 7, a liquid crystal display according to an exemplary embodiment of the present invention includes a lower panel 100, an upper panel 200, and a liquid crystal layer 3 interposed between the two panels 100 and 200. ).

First, the lower panel 100 will be described in detail with reference to FIGS. 3, 5, 6, and 7.

A plurality of gate conductors including a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding upward and end portions 129 having a large area for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110. , May be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage and almost extends in parallel with the gate line 121. Each storage electrode line 131 is positioned between two adjacent gate lines 121. The storage electrode line 131 includes storage electrodes 137a and 137b extending up and down. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate conductors 121 and 131 may be formed of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum (Mo), It may be made of molybdenum-based metals such as molybdenum alloys, chromium (Cr), tantalum (Ta), and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 121 and 131 may be made of various other metals or conductors.

Side surfaces of the gate conductors 121 and 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 121 and 131.

On the gate insulating layer 140, a plurality of island semiconductors 154 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated as a-Si), polycrystalline silicon, or the like are formed. The semiconductor 154 is positioned over the gate electrode 124.

A plurality of island type ohmic contacts 163 and 165 are formed on the semiconductor 154. The ohmic contacts 163 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The ohmic contacts 163 and 165 are paired and disposed on the semiconductor 154.

Side surfaces of the semiconductor 154 and the ohmic contacts 163 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A data conductor including a plurality of data lines 171 and a plurality of drain electrodes 175 is formed on the ohmic contacts 163 and 165 and the gate insulating layer 140.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121 and the storage electrode line 131. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and an end portion 179 having a large area for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and includes a rod-shaped end portion facing the source electrode 173 around the gate electrode 124. The rod end is partially surrounded by the bent source electrode 173.

The other end of the drain electrode 175 is divided into two branches and extends substantially parallel to the data line 171, and then extends in parallel to the data line 171 and then bent again. This portion is referred to as a coupling electrode 176 in the future.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the semiconductor 154 form one thin film transistor (TFT), and a channel of the thin film transistor. ) Is formed in the semiconductor 154 between the source electrode 173 and the drain electrode 175.

The data conductors 171 and 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum and titanium, or an alloy thereof, and a refractory metal film (not shown) and a low resistance conductive film (not shown). It may have a multi-layer structure including). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data conductors 171 and 175 may be made of various other metals or conductors.

In addition, the data conductors 171 and 175 may be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 163 and 165 exist only between the semiconductor 154 below and the data conductors 171 and 175 thereon, and lower the contact resistance therebetween. An extension of the semiconductor 154 positioned on the gate line 121 may soften the profile of the surface to prevent the data line 171 from being disconnected. The semiconductor 154 may be exposed between the source electrode 173 and the drain electrode 175 without being blocked by the data conductors 171 and 175.

A passivation layer 180 is formed on the data conductors 171 and 175 and the exposed portion of the semiconductor 154. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and the dielectric constant is preferably about 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 154 while maintaining excellent insulating properties of the organic layer.

In the passivation layer 180, a plurality of contact holes 182 exposing the end portions 179 of the data line 171 and a plurality of contact holes 185 exposing portions of the drain electrode 175 are formed. have. In the passivation layer 180 and the gate insulating layer 140, a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 are formed.

A plurality of pixel electrodes 191, a plurality of shielding electrodes (not shown), and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

Each pixel electrode 191 includes first and second subpixel electrodes 191a and 191b. The first and second subpixel electrodes 191a and 191b are engaged with each other with a gap 94 interposed therebetween, and the second subpixel electrode 191b is inserted at the center of the first subpixel electrode 191a. It is.

The first subpixel electrode 191a includes a first piece 191a1, a second piece 191a2, and a third piece 191a3. The first and second pieces 191a1 and 191a2 are in the form of a trapezoid comprising two parallel hypotenuses, and the third piece 191a3 is a first parallel to the two hypotenuses of the first and second pieces 191a and 191b. And a third side parallel to the second side and the data line 171. The first to third pieces 191a1, 191a2, and 191a3 are connected to each other by narrow and thin connections along the second subpixel electrode 191b. In some cases, the first to third pieces 191a1, 191a2, and 191a3 may be connected to each other through a data conductor.

The hypotenuse of the first and second pieces 191a1 and 191a2 and the first and second sides of the third piece 191a3 form an angle of about 45 ° with respect to the gate line 121.

By taking such a structure, the area of the first subpixel electrode 191a and the second subpixel electrode 191b can be easily adjusted. Therefore, the area of the first subpixel electrode 191a may be smaller than that of the second subpixel electrode 191b. The ratio of the area of the first subpixel electrode 191a and the area of the second subpixel electrode 191b may be 1: 1 to 1: 3.

The first subpixel electrode 191a is connected to the drain electrode 175 through the contact hole 185. In addition, the coupling electrode 176 that forms part of the drain electrode 175 overlaps the second subpixel electrode 191b to form a coupling capacitor Ccp.

The first and second subpixel electrodes 191a and 191b include the common electrode 270 of the upper panel 200 and the first and second liquid crystal capacitors Clca / Clcb together with portions of the liquid crystal layer 3 therebetween. Thus, the applied voltage is maintained even after the thin film transistor Q is turned off.

The first and second subpixel electrodes 191a and 191b overlap the storage electrodes 137a and 137b to form the storage capacitor Cst, and enhance the voltage holding capability of the storage capacitors Clca and Clcb.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 and the external device.

Next, the common electrode display panel 200 will be described with reference to FIGS. 4, 5, and 6.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass or plastic. The light blocking member 220 is also called a black matrix and prevents light leakage. The light blocking member 220 includes a linear portion corresponding to the data line 171 of the thin film transistor array panel 100 and a widened portion corresponding to the thin film transistor. Alternatively, the light blocking member 220 may have a plurality of openings facing the pixel electrode 191 and having substantially the same shape as the pixel electrode 191.

A plurality of color filters 230 are also formed on the substrate 210 and are disposed so as to almost fit within the area surrounded by the light blocking member 230. The color filter 230 may extend in the vertical direction along the pixel electrode 191 to form a band. The color filter 230 may display one of primary colors such as three primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be made of an (organic) insulator, protects the color filter 230, prevents the color filter 230 from being exposed, and provides a flat surface.

The common electrode 270 is formed on the overcoat 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO and has a plurality of cutouts 71, 72, 73a, and 73b.

One set of cutouts 71, 72, 73a, and 73b faces one pixel electrode 191 and includes first and second center cutouts 71 and 72, an upper cutout 73a, and a lower cutout ( 73b). The first central cutout 71 is positioned at the center of the third piece 191a3 of the first subpixel electrode 191a, and divides the third piece 191a3 into two regions.

The second central cutout 72 includes an oblique portion and a longitudinal portion and a pair of longitudinal longitudinal portions. An oblique line portion is formed at a central portion of the second subpixel electrode 191b along the shape of the second subpixel electrode 191b. In addition, a portion of the second central cutout 72 overlaps the coupling electrode 176.

The upper cutout 73a overlaps the outer hypotenuse 193a of the hypotenuses of the first piece 191a1 of the first subpixel electrode, and the lower cutout 73b is the second piece 191a2 of the first subpixel electrode. ) Overlaps with the outer hypotenuse 193b. If the area of the subregion of the pixel, which is composed of the first and second pieces 191a1 and 191a2 of the first subpixel electrode 191a, becomes larger than the design value due to a misalignment process, an area not affected by the electric field increases. As a result, the response speed decreases and an afterimage phenomenon occurs. However, when the cutouts 73a and 73b are disposed on the edge hypotenuses 193a and 193b of the first and second pieces 191a1 and 191a2 as in the present invention, the area of the first and second pieces 191a1 and 191a2 is designed. Even if it is wider than the teeth, the area of the subregion can be prevented from growing.

The number of cutouts 71, 72, 73a, and 73b may also vary depending on the design element, and the light blocking member 220 overlaps the cutouts 71, 72, 73a, and 73b so that the cutouts 71, 72, and 73a overlap. , 73b) can block light leakage in the vicinity.

Alignment layers 11 and 21 are coated on inner surfaces of the display panels 100 and 200, and they may be vertical alignment layers. Polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, and the polarization axes of the two polarizers 12 and 22 are perpendicular to each other, and one of the polarization axes is parallel to the gate line 121. desirable. In the case of a reflective liquid crystal display, one of the two polarizers 12 and 22 may be omitted.

The liquid crystal display according to the present exemplary embodiment may further include a phase retardation film (not shown) for compensating for the delay value of the liquid crystal layer 3. The phase retardation film has birefringence and reversely compensates for the phase retardation of the liquid crystal layer 3.

The liquid crystal display may include a polarizer 12 and 22, a phase retardation film, display panels 100 and 200, and a backlight unit (not shown) for supplying light to the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field. Therefore, incident light does not pass through the quadrature polarizers 12 and 22 and is blocked.

Next, the operation of such a liquid crystal display will be described.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 applies the input image signals R, G, and B to the operating conditions of the liquid crystal panel assembly 300 and the data driver 500 based on the input image signals R, G, and B and the input control signal. After appropriately processing and generating the gate control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are processed. ) Is output to the data driver 500. The output video signal DAT has a predetermined number (or gradation) as a digital signal.

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of transmission of image data to a group of subpixels, a load signal LOAD and a data clock signal for applying a data signal to the liquid crystal panel assembly 300. (HCLK). The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " RVS) may be further included.

In response to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for a group of subpixels, and the gray level corresponding to each digital image signal DAT. By selecting the voltage, the digital image signal DAT is converted into an analog data signal and then applied to the corresponding data line.

The gate driver 400 applies a gate-on voltage Von to the gate line according to the gate control signal CONT1 from the signal controller 600 to turn on the switching element connected to the gate line. Then, the data signal applied to the data line is applied to the corresponding subpixel through the turned-on switching element.

As described above, only the first subpixel electrode 191a receives the data voltage Vd through the switching element Q, and the second subpixel electrode 191b changes the voltage of the first subpixel electrode 191a. It may have a voltage that changes accordingly. In this case, the voltage of the first subpixel electrode 191a having a relatively small area is higher than the voltage of the second subpixel electrode 191b having a relatively large area.

When the potential difference is generated at both ends of the liquid crystal capacitors Clcs and Clcm, a primary electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated in the liquid crystal layer 3. [Hereinafter, the pixel electrode 191 and the common electrode 270 will be referred to as "field generating electrodes." Then, the liquid crystal molecules of the liquid crystal layer 3 respond to the electric field, and its long axis is in the direction of the electric field. The angle of inclination is perpendicular, and the degree of change in polarization of incident light in the liquid crystal layer 3 varies according to the degree of inclination of the liquid crystal molecules. The change in polarization is represented by a change in transmittance by the polarizer, and the liquid crystal display displays an image represented by the image signal DAT.

The angle at which the liquid crystal molecules are inclined depends on the intensity of the electric field. Since the voltages of the two liquid crystal capacitors Clca and Clcb are different from each other, the angles at which the liquid crystal molecules are inclined are different and thus the luminance of the two subpixels is different. Therefore, by properly adjusting the voltages of the two liquid crystal capacitors (Clca, Clcb), the image viewed from the side can be as close as possible to the image viewed from the front, that is, the side gamma curve can be as close as possible to the front gamma curve. By this, side visibility can be improved.

The ratio of the first liquid crystal capacitor Clca voltage Va and the second liquid crystal capacitor Clcb voltage Vb can be adjusted by changing the capacitance of the coupling capacitor Ccp, and the capacitance of the coupling capacitor Ccp is This can be changed by adjusting the overlapping area and distance of the second subpixel electrode 191b, the capacitor electrode 136, and the coupling electrode 176. The ratio of the first liquid crystal capacitor Clca voltage Va and the second liquid crystal capacitor Clcb voltage Vb is preferably 1: 0.5 to 1: 0.9.

Alternatively, the voltage Vb of the second liquid crystal capacitor Clcb may be higher than the voltage Va of the first liquid crystal capacitor Clca, which may cause the second liquid crystal capacitor Clcb to be a predetermined voltage such as a common voltage. This is possible by precharging.

The direction in which the liquid crystal molecules are inclined is determined by the horizontal components of the cut portions 71, 72, 73a, and 73b of the field generating electrodes 191 and 270 and the hypotenuse of the pixel electrode 191 distorting the electric field. The horizontal component of the electric field is perpendicular to the hypotenuse of the cutouts 71, 72, 73a, 73b and the pixel electrode 191. Referring to FIG. 3, one set of cutouts 71, 72, 73a, and 73b may be a plurality of sub-areas having pixel electrodes 191 having two inclined major edges, respectively. Divide. Since the liquid crystal molecules on each subregion are inclined in a direction perpendicular to the periphery, the directions of inclination are approximately four directions. As described above, when the liquid crystal molecules are inclined in various directions, the reference viewing angle of the liquid crystal display is increased.

In addition, if the size of the region through which the light can pass through the four inclination directions are equal, it is possible to obtain uniform visibility at various viewing angles. As described above, since the opaque members are arranged in symmetry, it is easy to adjust the size of the transmission region.

The shape and arrangement of the cutouts 71, 72, 73a and 73b for determining the inclination direction of the liquid crystal molecules may be changed, and the at least one cutout 71, 72, 73a and 73b may have a protrusion (shown in FIG. Or depressions (not shown). The protrusions may be made of organic or inorganic materials and may be disposed above or below the field generating electrodes 191 and 270.

On the other hand, since the same common voltage is applied to the common electrode 270 and the shielding electrode 88, there is almost no electric field between the two. Therefore, since the liquid crystal molecules positioned between the common electrode 270 and the shielding electrode 88 maintain the initial vertical alignment state, light incident on the portion is not transmitted and is blocked.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied, and the data voltage is applied to all the pixels PX to display an image of one frame.

When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel PX is opposite to the polarity of the previous frame. (“Invert frame”). In this case, the polarities of the data voltages flowing through one data line may be changed (eg, row inversion and point inversion), or polarities of data voltages applied to one pixel row may be different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

According to the present invention, the response speed can be improved to suppress instantaneous afterimage, and the area of each subpixel electrode can be easily adjusted to more effectively improve side visibility.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (11)

A liquid crystal display device comprising a plurality of pixels, A first subpixel electrode comprising a first piece comprising a first hypotenuse, a second piece comprising a second hypotenuse, and a third piece of triangular form comprising the first, second and third sides; A second subpixel electrode disposed between the first to third pieces and forming a pixel electrode together with the first subpixel electrode; A common electrode facing the pixel electrode and including a first cutout Including; The third piece is divided into two regions by the first incision. Liquid crystal display. In claim 1, The first piece, the second piece and the third piece are electrically connected to each other. Liquid crystal display. In claim 1, The common electrode further includes a second cutout overlapping the first hypotenuse and a third cutout overlapping the second hypotenuse. In claim 1, The first subpixel electrode and the second subpixel electrode are capacitively coupled. In claim 1, A thin film transistor connected to the first subpixel electrode, A gate line connected to the thin film transistor, and A data line connected to the thin film transistor and crossing the gate line Liquid crystal display further comprising. In claim 5, The first hypotenuse and the second hypotenuse each have an angle of 45 degrees with the gate line, and the first hypotenuse and the second hypotenuse form an angle of 90 degrees with each other. In claim 6, Wherein the first hypotenuse and the first side are parallel to each other, the second hypotenuse is parallel to the second side, and the third side is parallel to the data line. In claim 1, The pixel is divided into eight sub-regions. In claim 1, The common electrode further includes a fourth cutout dividing the second subpixel electrode into two regions. In claim 1, The area ratio of the area of the first subpixel electrode and the area of the second subpixel electrode is 1: 1 to 1: 3. In claim 1, The voltage difference ratio between the voltage difference between the first subpixel electrode and the common electrode, and the voltage difference between the second subpixel electrode and the common electrode is 1: 0.5 to 1: 0.9.

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