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KR20070118865A - Non-volatile Memory, Manufacturing Method and Device Thereof - Google Patents

Non-volatile Memory, Manufacturing Method and Device Thereof Download PDF

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KR20070118865A
KR20070118865A KR1020060053106A KR20060053106A KR20070118865A KR 20070118865 A KR20070118865 A KR 20070118865A KR 1020060053106 A KR1020060053106 A KR 1020060053106A KR 20060053106 A KR20060053106 A KR 20060053106A KR 20070118865 A KR20070118865 A KR 20070118865A
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pressure
doped
memory device
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nonvolatile memory
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황현상
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광주과학기술원
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate

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Abstract

A non-volatile memory device, a manufacturing method of the same, and a manufacturing apparatus of the same are provided to obtain stable and uniform switching characteristics and operational characteristics by forming oxygen vacancy at a boundary of metal/oxide. A pressure control unit(1) controls pressure of gas. A gas inlet(2) is connected to a high-pressure annealing chamber(4) in order to receive the gas from the pressure control unit. A gas outlet(3) is connected to the high-pressure annealing chamber in order to control the internal pressure of the high-pressure annealing chamber by discharging the gas to the outside. The high-pressure annealing chamber is formed to perform a thermal process for a single crystalline oxide layer or a single crystalline oxide layer having upper and lower metal electrodes. A temperature controller(5) is connected to the high-pressure annealing chamber in order to adjust the temperature. A pressure monitor(6) is connected to the high-pressure annealing chamber in order to monitor the internal pressure of the high-pressure annealing chamber. A computer(7) is connected to a pressure monitor and a temperature controller in order to control the internal pressure and the internal temperature of the high-pressure annealing chamber.

Description

비휘발성 기억소자, 그 제조방법 및 그 제조장치{Non-volatile Memory Device And Manufacturing Method And Apparatus Therefor}Non-volatile memory device, method for manufacturing same, and manufacturing device therefor {Non-volatile Memory Device And Manufacturing Method And Apparatus Therefor}

도 1은 본 발명의 일 실시예에 따른 비휘발성 기억소자의 히스테리시스 곡선을 나타낸 그래프이다.1 is a graph showing a hysteresis curve of a nonvolatile memory device according to an embodiment of the present invention.

도 2는 본 발명의 일 실시예에 따른 비휘발성 기억소자의 제조장치의 개략도이다.2 is a schematic diagram of an apparatus for manufacturing a nonvolatile memory device according to an embodiment of the present invention.

도 3은 본 발명의 일 실시예에 따른 비휘발성 기억소자의 전압-저항비를 나타낸 그래프이다.3 is a graph illustrating a voltage-resistance ratio of a nonvolatile memory device according to an exemplary embodiment of the present invention.

도 4는 본 발명의 일 실시예에 따른 비휘발성 기억소자의 cycle stress에 따른 저항변화를 나타낸 그래프이다. 4 is a graph illustrating a resistance change according to cycle stress of a nonvolatile memory device according to an exemplary embodiment of the present invention.

{도면의 주요부분에 대한 부호의 설명}} Explanation of symbols for main part of drawing

1 : 가스압력조절 유닛 2 : 가스유입구1: gas pressure control unit 2: gas inlet

3 : 가스유출구 4 : 고압 어닐링 챔버3: gas outlet 4: high pressure annealing chamber

5 : 온도 조절기 6 : 압력 모니터5: thermostat 6: pressure monitor

7 : 공정제어 컴퓨터7: process control computer

본 발명은 비휘발성 기억소자에 관한 것으로서, 보다 상세하게는 상부와 하부에 전극을 형성하고, 상기 전극 사이에, 저항변화에 핵심적인 다량의 산소공공(oxygen vacancy)을 포함하는 산화막을 포함하는 비휘발성 반도체 기억소자와 그의 제조 공정기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to form an electrode at an upper portion and a lower portion, and between the electrodes, a non-volatile memory including an oxide film including a large amount of oxygen vacancy, which is essential for resistance change. A volatile semiconductor memory device and its manufacturing process technology.

현재 비휘발성 메모리로 상용화된 플래시 메모리(Flash memory)의 경우, 플로팅 폴리실리콘(floating polysilicon)이나 질화규소(silicon nitride)에 전자를 저장하거나 제거하여 문턱전압(Vth)을 변화시켜 기억소자로 이용한다. 이에 반해, 최근 연구되고 있는 상변화형 메모리(phase change memory, 'PRAM'), 자기 메모리(magnetic memory, 'MRAM') 등은 외부에서 인가한 열이나 자기장을 이용하여 저항변화를 발생시켜서 기억소자로 사용한다. Flash memory, which is currently commercially available as a nonvolatile memory, stores or removes electrons in floating polysilicon or silicon nitride, and changes the threshold voltage V th to be used as a storage device. On the other hand, recently studied phase change memory (PRAM), magnetic memory (MRAM), etc. generate a change in resistance by using externally applied heat or magnetic field. Used as.

또 다른 비휘발성 메모리로서 전압인가에 의해 산화막의 저항이 변화되는 특성을 이용하는 저항성 메모리(ReRAM)에 대한 지금까지 연구 결과를 종합하면, 기본적인 스위칭 특성은 다양한 산화물 재료에서 확인하였으나, 구체적인 스위칭 원리에 대해서는 원인 규명이 미흡한 실정이다. 제작된 기억소자의 전기적 특성이 불균일하여, 스위칭 횟수와 셋/리셋 전압, 리셋 전류 등이 차세대 기가/테라-비트급 메모리로 상용화하기에는 많은 문제가 있다. As a result of the previous research on resistive memory (ReRAM) using a characteristic of changing the resistance of an oxide film by applying voltage as another nonvolatile memory, basic switching characteristics have been confirmed in various oxide materials, The cause is insufficient. Since the electrical characteristics of the fabricated memory device are uneven, there are many problems in that the number of switching, set / reset voltage, reset current, etc. are commercialized as next generation giga / tera-bit memory.

본 발명의 목적은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로써, 인가된 전압에 따른 저항변화를 극대화하여 안정적인 메모리 동작이 가능한 비휘발성 기억소자를 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device capable of stable memory operation by maximizing a resistance change according to an applied voltage.

본 발명의 다른 목적은 저항 변화를 일으키는 핵심요소인 산소공공을 다량 함유하는 새로운 산화막 제조공정을 제공하여 신뢰성이 우수하고 상용화 가능성이 높은 비휘발성 기억소자를 제공하는 데 있다.Another object of the present invention is to provide a new oxide film manufacturing process containing a large amount of oxygen vacancies, which is a key element causing resistance change, to provide a nonvolatile memory device having high reliability and high commercial availability.

상기 목적을 달성하기 위하여 본 발명의 비휘발성 기억소자는, 비휘발성 기억소자에 있어서 상부와 하부에 전극을 형성하고, 상기 전극 사이에 다량의 산소공공(oxygen vacancy)을 포함하는 산화막을 형성하는 것을 특징으로 한다.In order to achieve the above object, the nonvolatile memory device of the present invention is to form an electrode on the upper and lower portions of the nonvolatile memory device, and to form an oxide film including a large amount of oxygen vacancy between the electrodes. It features.

본 발명에서, 상기 산화막은 단결정 산화막인 것을 포함한다.In the present invention, the oxide film includes a single crystal oxide film.

본 발명에서 바람직하게는 상기 단결정 산화막은 티탄산스트론튬(SrTiO3), 산화아연(ZnO2), 산화망간(MnO)으로 구성된 그룹에서 선택된 어느 하나의 산화물에 3족 내지 12족 금속원소로 구성된 그룹에서 선택된 1종 이상의 금속원소가 도핑된 것을 포함한다.In the present invention, the single crystal oxide film is preferably selected from the group consisting of Group 3 to Group 12 metal elements in any one oxide selected from the group consisting of strontium titanate (SrTiO 3 ), zinc oxide (ZnO 2 ), and manganese oxide (MnO). It includes doped with at least one selected metal element.

본 발명에서, 상기 단결정 산화막은 니오브가 도핑된 티탄산스트론튬(Nb- doped SrTiO3), 크롬이 도핑된 티탄산스트론튬(Cr-doped SrTiO3), 란탄이 도핑된 티탄산스트론튬(La-doped SrTiO3), 알루미늄이 도핑된 산화아연(Al-doped ZnO2) 및 Re0.7AE0.3MnO3(Re는 희토류원소, AE는 알칼리토류원소, Mn은 망간, O는 산소)로 구성된 그룹에서 선택하는 것을 포함한다.In the present invention, the single crystal oxide film is strontium titanate doped with niobium (Nb- doped SrTiO 3 ), chromium doped strontium titanate (Cr-doped SrTiO 3 ), lanthanum doped strontium titanate (La-doped SrTiO 3 ), Al-doped zinc oxide (Al-doped ZnO 2 ) and Re 0.7 AE 0.3 MnO 3 (Re is a rare earth element, AE is an alkaline earth element, Mn is manganese, O is selected from the group consisting of).

상기 목적을 달성하기 위하여 본 발명의 비휘발성 기억소자의 제조방법은, 비휘발성 기억소자의 제조방법에 있어서 금속 전극 위에 단결정 산화막을 증착하고 그 위에 다시 금속 전극을 증착하는 단계 및 수소, 질소 및 중수소로 구성된 그룹에서 선택한 1종 이상의 가스를 일정 농도 및 압력으로 하여 상기 소자에 가하고 일정 시간 및 온도로 열처리하는 단계를 포함한다.In order to achieve the above object, a method of manufacturing a nonvolatile memory device according to the present invention includes the steps of depositing a single crystal oxide film on a metal electrode and depositing a metal electrode on the metal electrode in the method of manufacturing a nonvolatile memory device and hydrogen, nitrogen, and deuterium. And applying the at least one gas selected from the group consisting of a predetermined concentration and pressure to the device and performing heat treatment at a predetermined time and temperature.

또한 본 발명의 비휘발성 기억소자의 제조방법은, 수소, 질소 및 중수소로 구성된 그룹에서 선택한 1종 이상의 가스를 일정 농도 및 압력으로 하여 단결정 산화막에 가하고 일정 시간 및 온도로 열처리하는 단계 및 금속 전극 위에 상기 단계의 단결정 산화막을 증착하고 그 위에 다시 금속 전극을 증착하는 단계를 포함한다.In addition, the method of manufacturing a nonvolatile memory device of the present invention, the step of applying at least one gas selected from the group consisting of hydrogen, nitrogen and deuterium at a constant concentration and pressure to a single crystal oxide film and heat-treated at a predetermined time and temperature and on the metal electrode Depositing a single crystal oxide film of the step and depositing a metal electrode thereon.

본 발명의 비휘발성 기억소자의 제조방법에 있어서, 상기 단결정 산화막은 티탄산스트론튬(Nb-doped SrTiO3), 산화아연(ZnO2), 산화망간(MnO)으로 구성된 그룹에서 선택된 어느 하나의 산화물에 3족 내지 12족 금속원소로 구성된 그룹에서 선택된 1종 이상의 원소가 도핑된 것을 특징으로 한다.In the method of manufacturing a nonvolatile memory device of the present invention, the single crystal oxide film is formed of one oxide selected from the group consisting of strontium titanate (Nb-doped SrTiO 3 ), zinc oxide (ZnO 2 ), and manganese oxide (MnO). At least one element selected from the group consisting of group 12 to 12 metal elements is characterized in that the doped.

본 발명의 비휘발성 기억소자의 제조방법에 있어서, 바람직하게는 상기 단결 정 산화막은 니오브가 도핑된 티탄산스트론튬(Nb-doped SrTiO3), 크롬이 도핑된 티탄산스트론튬(Cr-doped SrTiO3), 란탄이 도핑된 티탄산스트론튬(La-doped SrTiO3), 알루미늄이 도핑된 산화아연(Al-doped ZnO2) 및 Re0.7AE0.3MnO3(Re는 희토류원소, AE는 알칼리토류원소, Mn은 망간, O는 산소)로 구성된 그룹에서 선택하는 것을 포함한다.In the method of manufacturing a nonvolatile memory device of the present invention, preferably, the single crystal oxide film is formed of niobium-doped strontium titanate (Nb-doped SrTiO 3 ), chromium-doped strontium titanate (Cr-doped SrTiO 3 ), and lanthanum. Doped strontium titanate (La-doped SrTiO 3 ), aluminum-doped zinc oxide (Al-doped ZnO 2 ) and Re 0.7 AE 0.3 MnO 3 (Re is rare earth element, AE is alkaline earth element, Mn is manganese, O Is selected from the group consisting of oxygen).

본 발명의 비휘발성 기억소자의 제조방법에 있어서, 상기 가스의 농도는 전체 중량대비 10 내지 100중량%인 것이 바람직하다.In the manufacturing method of the nonvolatile memory device of the present invention, the concentration of the gas is preferably 10 to 100% by weight based on the total weight.

본 발명의 비휘발성 기억소자의 제조방법에 있어서, 상기 가스의 압력은 1 내지 100 기압인 것이 바람직하다.In the method for manufacturing a nonvolatile memory device of the present invention, the pressure of the gas is preferably 1 to 100 atm.

본 발명의 비휘발성 기억소자의 제조방법에 있어서, 상기 열처리는 300 내지 600℃에서 10 내지 100분간 수행하는 것이 바람직하다.In the manufacturing method of the nonvolatile memory device of the present invention, the heat treatment is preferably performed for 10 to 100 minutes at 300 to 600 ℃.

상기 목적을 달성하기 위한 본 발명의 비휘발성 기억소자의 제조장치는, 가스의 압력을 조절하는 압력조절 유닛(1)과, 고압 어닐링 챔버에 연결되어 상기 압력조절 유닛으로부터 가스가 유입되는 가스유입구(2)와, 고압 어닐링 챔버에 연결되어 챔버 내의 압력을 조절하기 위하여 가스를 유출하는 가스유출구(3)와, 단결정 산화막 또는 금속전극을 상부와 하부에 증착한 단결정 산화막에 고압 가스 처리 및 열처리를 가하는 고압 어닐링 챔버(4)와, 고압 어닐링 챔버에 연결되어 챔버 내의 온도를 조절하는 온도조절기(5)와, 고압 어닐링 챔버에 연결되어 챔버 내의 압력을 모니터링하는 압력모니터(6)와, 및 상기 압력모니터 및 온도조절기와 연결되어 챔 버 내의 온도와 압력을 제어하는 컴퓨터(7)로 구성된 것을 포함한다.The apparatus for manufacturing a nonvolatile memory device of the present invention for achieving the above object, the pressure control unit (1) for adjusting the pressure of the gas, and the gas inlet port is connected to the high-pressure annealing chamber and the gas flows from the pressure control unit ( 2) high pressure gas treatment and heat treatment to the gas outlet 3 connected to the high pressure annealing chamber to discharge the gas to control the pressure in the chamber, and to the single crystal oxide film having the single crystal oxide film or the metal electrode deposited on the upper and lower portions thereof. A high pressure annealing chamber 4, a temperature controller 5 connected to the high pressure annealing chamber to adjust the temperature in the chamber, a pressure monitor 6 connected to the high pressure annealing chamber to monitor the pressure in the chamber, and the pressure monitor And a computer 7 connected to the thermostat for controlling the temperature and pressure in the chamber.

본 발명은 종래 2개의 차세대 기억 소자인 PRAM과 MRAM과 유사하지만, 전압 펄스를 이용하여 절연막의 저항변화를 일으키는 것이 특징이고 기존의 다결정, 비정질구조의 산화물 대신 단결정 도핑된 산화물을 이용하는 비휘발성 저항변화 기억소자에 적용될 수 있다. The present invention is similar to the conventional two next-generation memory devices, PRAM and MRAM, but it is characterized by causing a change in resistance of the insulating film by using a voltage pulse, and nonvolatile resistance change using a single crystal doped oxide instead of a conventional polycrystalline and amorphous oxide. It can be applied to memory devices.

즉, 차세대 비휘발성 메모리 소자로서 본 발명의 저항변화 메모리(ReRAM)는 단결정 니오브가 도핑된 티탄산스트론튬(Nb-doped SrTiO3) 등과 금속 계면에 존재하는 쇼트키 장벽을 이용하여 인가하는 펄스(pulse) 전압에 따라 다른 저항 상태를 유지할 수 있어서 소자의 안정적인 스위칭 특성을 도모할 수 있다. 다만, 온/오프(On/Off)의 저항비가 상대적으로 낮아서 기가/테라-비트급 메모리 소자 응용시에 문제가 생길 수 있기 때문에 본 발명은 저항 변화를 일으키는 핵심 요소인 산소공공을 효과적으로 조절하여 다량으로 산화막에 형성될 수 있게 하는 것이다.That is, as a next-generation nonvolatile memory device, the resistance change memory (ReRAM) of the present invention is applied to a single crystal niobium-doped strontium titanate (Nb-doped SrTiO 3 ) or a schottky barrier present at a metal interface. It is possible to maintain different resistance states depending on the voltage, thereby achieving stable switching characteristics of the device. However, since the on / off resistance ratio is relatively low, problems may occur in a giga / tera-bit memory device application, and the present invention effectively controls the oxygen vacancy, which is a key factor causing resistance change, in a large amount. It can be formed in the oxide film.

이를 위하여 금속/단결정 산화막의 계면에 다량의 산소공공을 고압 가스 처리 및 열처리를 수행하여 형성한다. To this end, a large amount of oxygen vacancies are formed at the interface of the metal / monocrystalline oxide film by high pressure gas treatment and heat treatment.

본 발명의 일 실시예에서 산화막에 산소공공을 다량 포함하기 위하여 처리되는 고압 가스는 수소, 중수소, 질소 등이 가능하며 특히 수소처리가 바람직하다.In one embodiment of the present invention, the high-pressure gas treated to include a large amount of oxygen vacancies in the oxide film may be hydrogen, deuterium, nitrogen, and the like, and hydrogen treatment is particularly preferable.

본 발명의 일 실시예에서 비휘발성 기억소자의 금속전극은 일함수가 큰 것으로서 당해 분야에 당업자가 공지의 물질로 알 수 있는 것이면 어느 것이든 무방하 다.In one embodiment of the present invention, the metal electrode of the nonvolatile memory device has a large work function, as long as it is known to those skilled in the art.

본 발명의 일 실시예에서 비휘발성 기억소자의 산화막은 단결정 산화막이 바람직하며, 단결정 산화막은 니오브가 도핑된 티탄산스트론튬(Nb-doped SrTiO3), 크롬이 도핑된 티탄산스트론튬(Cr-doped SrTiO3), 란탄이 도핑된 티탄산스트론튬(La-doped SrTiO3), 알루미늄이 도핑된 산화아연(Al-doped ZnO2) 등에서 선택하는 것이 바람직하다.In one embodiment of the present invention, the oxide film of the nonvolatile memory device is preferably a single crystal oxide film, and the single crystal oxide film is niobium-doped strontium titanate (Nb-doped SrTiO 3 ) or chromium-doped strontium titanate (Cr-doped SrTiO 3 ). It is preferable to select from lanthanum-doped strontium titanate (La-doped SrTiO 3 ), aluminum-doped zinc oxide (Al-doped ZnO 2 ), and the like.

상기 금속과 단결정 산화막의 계면에 형성되는 산소공공을 고압 수소 열처리를 통해 다량으로 형성함으로써 저항 변화가 극대화되고 이에 따라 비휘발성 기억소자의 스위치특성이나 동작특성이 극대화될 수 있다.By forming a large amount of oxygen vacancy formed at the interface between the metal and the single crystal oxide layer through high pressure hydrogen heat treatment, the resistance change can be maximized, and thus the switch characteristic or operation characteristic of the nonvolatile memory device can be maximized.

이하 비휘발성 기억소자에 관한 구체적인 실시예와 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다. 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 공지 기능 및 구성에 대한 상세한 설명은 생략한다.Hereinafter, the present invention will be described in more detail with reference to specific embodiments and drawings related to nonvolatile memory devices. Detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention will be omitted.

(실시예 1)(Example 1)

본 발명의 일 실시예에 따른 ReRAM용 소자는 다음과 같은 공정 순서를 이용하여 제작한다.A device for ReRAM according to an embodiment of the present invention is manufactured using the following process sequence.

● 니오브가 도핑된 티탄산스트론튬(Nb-doped SrTiO3) 또는 알루미늄이 도핑 된 산화아연(Al-doped ZnO2) 단결정 위에 일함수가 큰 금속 전극을 증착하여 쇼트키 장벽(schottky barrier)을 형성한다.• A schottky barrier is formed by depositing a metal electrode having a high work function on a niobium-doped strontium titanate (Nb-doped SrTiO 3 ) or aluminum-doped zinc oxide (Al-doped ZnO 2 ) single crystal.

● 수소 또는 중수소 분위기에서 10 내지 100%의 고농도와 1 내지 100 기압의 고압 조건으로 10 내지 100분 동안 300 내지 600℃의 적정온도에서 열처리를 실시한다. • Heat treatment is performed at an appropriate temperature of 300 to 600 ° C. for 10 to 100 minutes at high concentration of 10 to 100% and high pressure of 1 to 100 atm in hydrogen or deuterium atmosphere.

● 금속/산화막 계면에 존재하는 산소공공에 전자가 충전/방전(charging/discharging) 되는 것을 이용하여 쇼트키 장벽을 조절하여, 흐르는 전류를 조절함으로써, 비휘발성 기억소자로 이용한다. ● It is used as a nonvolatile memory device by controlling the Schottky barrier and controlling the flowing current by using charging / discharging of electrons to oxygen vacancy at the metal / oxide film interface.

(실시예 2)(Example 2)

본 발명의 일 실시예에 따른 ReRAM용 소자는 다음과 같은 공정 순서를 이용하여 제작한다.A device for ReRAM according to an embodiment of the present invention is manufactured using the following process sequence.

● 니오브가 도핑된 티탄산스트론튬(Nb-doped SrTiO3) 또는 알루미늄이 도핑된 산화아연(Al-doped ZnO2) 단결정을 10 내지 100%의 고농도와 1 내지 100 기압의 고압 조건인 수소 및 중수소 분위기에서 10 내지 100분 동안 300 내지 600℃의 적정온도에서 열처리를 실시한다. • Niobium-doped strontium titanate (Nb-doped SrTiO 3 ) or aluminum-doped zinc oxide (Al-doped ZnO 2 ) single crystals in a high concentration of 10 to 100% and high pressure conditions of 1 to 100 atmospheres in hydrogen and deuterium atmosphere Heat treatment is performed at an appropriate temperature of 300 to 600 ° C. for 10 to 100 minutes.

● 일함수가 큰 금속 전극을 증착하여 쇼트키 장벽을 형성한다.A metal electrode with a large work function is deposited to form a Schottky barrier.

● 금속/산화막 계면에 존재하는 산소공공에 전자가 충전/방전(charging/discharging) 되는 것을 이용하여 쇼트키 장벽을 조절하여, 흐르는 전 류를 조절함으로써, 비휘발성 기억소자로 이용한다. ● It is used as a non-volatile memory device by controlling the Schottky barrier by controlling the Schottky barrier by charging / discharging electrons to oxygen vacancy at the metal / oxide film interface.

도 1은 본 발명의 일 실시예에 따른 비휘발성 기억소자의 고압 수소 처리구(High Pressure Hydrogen Anneal, 'HPHA') 시편 및 비교 시편(Control sample)의 전압-전류에 대한 히스테리시스 곡선을 나타낸 그래프이다.1 is a graph showing a hysteresis curve with respect to voltage-current of a High Pressure Hydrogen Anneal (HPHA) specimen and a Control sample of a nonvolatile memory device according to an embodiment of the present invention.

저항 차이는 전원이 인가된 온(on) 상태의 저항치에 대한 전원이 인가되지 않은 오프(off) 상태의 저항치에 대한 비(Roff/Ron)로서 나타낸다. The resistance difference is expressed as the ratio (R off / R on ) to the resistance value of the off state where the power is not applied to the resistance value of the on state where the power is applied.

도 1을 참조하면, 고온 고압의 수소처리 공정을 하지 아니한 기존의 비휘발성 기억소자와 비교할 때 저항 차이가 고압 수소 처리 후 현저하게 증가되어 개선됨을 알 수 있다.Referring to FIG. 1, it can be seen that the resistance difference is remarkably increased and improved after the high pressure hydrogen treatment as compared with the conventional nonvolatile memory device which does not undergo the high temperature and high pressure hydrogen treatment process.

도 2는 본 발명의 일 실시예에 따른 비휘발성 기억소자를 생산하기 위한 비휘발성 기억소자의 제조장치의 개략도로서, 고압 수소 처리 및 열처리 장비를 포함하고 있다.FIG. 2 is a schematic diagram of an apparatus for manufacturing a nonvolatile memory device for producing a nonvolatile memory device according to an embodiment of the present invention, and includes high pressure hydrogen treatment and heat treatment equipment.

도 2를 참조하면 본 발명의 일 실시예에 따른 비휘발성 기억소자의 제조장치는 크게 가스의 유입,유출구(2,3)와 가스의 압력, 온도 등을 제어하는 컴퓨터(7)의 제어부와, 비휘발성 기억소자를 처리하는 고압 어닐링 챔버(4)와 온도조절부(5) 및 압력모니터(6)로 구성되어 있다.Referring to FIG. 2, an apparatus for manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention includes a control unit of a computer 7 which largely controls inflow and outflow ports 2 and 3 of gas and pressure, temperature, and the like of gas, It consists of a high pressure annealing chamber 4 for processing a nonvolatile memory element, a temperature control part 5 and a pressure monitor 6.

도 2를 참조하면 압력조절 유닛(1)을 통하여 고압의 가스가 고압 어닐링 챔버(4)에 유입되면 비휘발성 기억소자가 일정 조건의 농도와 압력의 수소, 질소 또 는 중수소 분위기에서 일정시간 동안 처리된다. 압력을 모니터링 하면서 온도조절부는 제어된 일정 온도하에서 고압 어닐링 챔버의 온도를 조절함으로써 열처리과정을 수행한다.Referring to FIG. 2, when a high-pressure gas flows into the high-pressure annealing chamber 4 through the pressure regulating unit 1, the nonvolatile memory device is treated for a predetermined time in a hydrogen, nitrogen or deuterium atmosphere having a predetermined concentration and pressure. do. While monitoring the pressure, the temperature controller performs a heat treatment process by adjusting the temperature of the high pressure annealing chamber under a controlled constant temperature.

고압 어닐링 챔버 내의 온도는 온도조절기(5)에서 조절하며, 내부의 가스 압력은 컴퓨터의 제어를 받아 가스유출기를 통해 적정 압력을 조절한다.The temperature in the high pressure annealing chamber is controlled by the temperature controller 5, and the gas pressure inside is controlled by a computer to adjust the appropriate pressure through the gas outlet.

상기 비휘발성 기억소자의 제조장치를 통해 고압 가스 처리와 열처리된 기억소자는 그 산화막에 산소공공이 많이 형성되어 메모리 특성과 저항비가 극대화된다.In the memory device subjected to the high pressure gas treatment and heat treatment through the apparatus for manufacturing the nonvolatile memory device, oxygen vacancies are formed in the oxide film to maximize the memory characteristics and the resistance ratio.

도 3은 본 발명의 일 실시예에 따른 비휘발성 기억소자에 대한 고압 수소 처리시 인가전압에 따른 저항비를 어떠한 처리를 하지 않은 기존의 비휘발성 기억소자의 저항비와 비교한 것을 나타낸 그래프이다.FIG. 3 is a graph illustrating a comparison of a resistance ratio of an applied voltage to a resistance ratio of a conventional nonvolatile memory device which has not been subjected to any treatment during high pressure hydrogen treatment for the nonvolatile memory device according to an embodiment of the present invention.

도 3을 참조하면 인가된 전압이 동일하더라도 비교 시편에 비하여 고압 수소 처리한 본 발명의 시험구의 저항비의 값이 월등히 증가됨을 알 수 있다. Referring to Figure 3 it can be seen that even if the applied voltage is the same, the value of the resistance ratio of the test sphere of the present invention subjected to high-pressure hydrogen treatment compared to the comparison specimen is significantly increased.

고압 수소 처리한 본 발명의 시편들은 인가 전압이 클수록 저항비의 값이 증가하였다. 유사한 저항비의 경우 높이에 대한 펄스폭(pulse width/height)을 현저히 줄여줄 수 있다.In the specimens of the present invention subjected to high pressure hydrogen treatment, the resistance ratio increased as the applied voltage increased. Similar resistance ratios can significantly reduce the pulse width / height versus height.

도 4는 본 발명의 일 실시예에 따른 비휘발성 기억소자의 cycle stress에 따른 저항변화를 나타낸 그래프이다. 4 is a graph illustrating a resistance change according to cycle stress of a nonvolatile memory device according to an exemplary embodiment of the present invention.

도 4를 참조하면, cycle stress 시 저항 변화 특성을 어떠한 처리를 하지 않은 기존의 비휘발성 기억소자와 본 발명의 고압 수소 처리를 적용한 비휘발성 기억 소자에서 비교하였는데, 본 발명의 일 실시예에 따른 고압 수소 열처리 공정을 적용하면 안정적인 저항값을 형성한다는 것을 알 수 있다.Referring to FIG. 4, a resistance change characteristic during cycle stress was compared with a conventional nonvolatile memory device having no treatment and a nonvolatile memory device applying the high pressure hydrogen treatment of the present invention. It can be seen that applying the hydrogen heat treatment process forms a stable resistance value.

본 발명의 일 실시예에서 비휘발성 기억소자에 처리되는 가스는 산화막에 산소공공을 다량 형성시킬 정도로 충분한 환원반응을 일으켜야 하므로 수소나 중수소 또는 질소 등의 가스 농도와 압력은 10 내지 100중량%, 1 내지 100기압이 바람직하고, 온도처리는 10 내지 100분간, 300 내지 600℃가 적당하다.In an embodiment of the present invention, since the gas to be treated in the nonvolatile memory device must cause a sufficient reduction reaction to form a large amount of oxygen vacancies in the oxide film, the gas concentration and pressure of hydrogen, deuterium, or nitrogen are 10 to 100% by weight, 1 It is preferable that the pressure is in the range of 100 to 100 atm, and 300 to 600 ° C is appropriate for the temperature treatment for 10 to 100 minutes.

상술한 바와 같이, 본 발명의 바람직한 실시예를 참조하여 설명하였지만 해당 기술분야의 숙련된 당업자라면 하기의 특허등록청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art can vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that modifications and variations can be made.

상술한 바와 같이 본 발명에 의하면, 금속/산화물 계면에 다량의 산소공공을 형성함으로써 인가전압에 따른 저항비가 현저하게 증가되어 안정적이고 균일한 스위치 특성과 동작 특성을 가지는 비휘발성 기억소자를 제작할 수 있다.As described above, according to the present invention, by forming a large amount of oxygen vacancy at the metal / oxide interface, the resistance ratio according to the applied voltage is significantly increased, thereby making it possible to manufacture a nonvolatile memory device having stable and uniform switch characteristics and operating characteristics. .

또한, 새로운 산화막 제조공정을 통해서, 산화막에 존재하는 산소공공의 스위칭 매카니즘에서의 역할을 극대화시킬 수 있어 ReRAM을 상용화를 가능하게 하는 효과가 있다.In addition, through the new oxide film manufacturing process, it is possible to maximize the role in the switching mechanism of the oxygen vacancy present in the oxide film has the effect of enabling commercialization of ReRAM.

Claims (12)

비휘발성 기억소자에 있어서, 상부와 하부에 전극을 형성하고, 상기 전극 사이에 다량의 산소공공(oxygen vacancy)을 포함하는 산화막을 형성하는 것을 특징으로 하는 비휘발성 기억소자.A nonvolatile memory device, comprising: forming electrodes at upper and lower portions, and forming an oxide film containing a large amount of oxygen vacancy between the electrodes. 제 1항에 있어서, 상기 산화막은 단결정 산화막인 것을 특징으로 하는 비휘발성 기억소자.The nonvolatile memory device according to claim 1, wherein the oxide film is a single crystal oxide film. 제 2항에 있어서, 상기 단결정 산화막은 티탄산스트론튬(SrTiO3), 산화아연(ZnO2), 산화망간(MnO)으로 구성된 그룹에서 선택된 어느 하나의 산화물에 3족 내지 12족 금속원소로 구성된 그룹에서 선택된 1종 이상의 금속원소가 도핑된 것을 특징으로 하는 비휘발성 기억소자.The method of claim 2, wherein the single crystal oxide film is selected from the group consisting of Group 3 to Group 12 metal elements in any one oxide selected from the group consisting of strontium titanate (SrTiO 3 ), zinc oxide (ZnO 2 ), and manganese oxide (MnO). Non-volatile memory device, characterized in that the doped one or more selected metal elements. 제 2항에 있어서, 상기 단결정 산화막은 니오브가 도핑된 티탄산스트론튬(Nb-doped SrTiO3), 크롬이 도핑된 티탄산스트론튬(Cr-doped SrTiO3), 란탄이 도핑된 티탄산스트론튬(La-doped SrTiO3), 알루미늄이 도핑된 산화아연(Al-doped ZnO2) 및 Re0 .7AE0 .3MnO3(Re는 희토류원소, AE는 알칼리토류원소, Mn은 망간, O는 산 소)로 구성된 그룹에서 선택하는 것을 특징으로 하는 비휘발성 기억소자.The method of claim 2, wherein the single crystal oxide layer is formed of niobium-doped strontium titanate (Nb-doped SrTiO 3 ), chromium-doped strontium titanate (Cr-doped SrTiO 3 ), or lanthanum-doped strontium titanate (La-doped SrTiO 3). ), 0.7 aluminum doped zinc (Al-doped ZnO 2) and oxidation Re 0 AE 0 .3 MnO 3 (Re is a rare earth element, AE is an alkaline-earth element, Mn is manganese, O is oxygen) the group consisting of Nonvolatile memory device, characterized in that selected from. 비휘발성 기억소자의 제조방법에 있어서,In the method of manufacturing a nonvolatile memory device, 금속 전극 위에 단결정 산화막을 증착하고 그 위에 다시 금속 전극을 증착하는 단계; 및 Depositing a single crystal oxide film on the metal electrode and depositing the metal electrode thereon again; And 수소, 질소 및 중수소로 구성된 그룹에서 선택한 1종 이상의 가스를 일정 농도 및 압력으로 하여 상기 단계의 소자에 가하고 일정 시간 및 온도로 열처리하는 단계를 포함하는 것을 특징으로 하는 비휘발성 기억소자의 제조방법.A method of manufacturing a nonvolatile memory device comprising the step of adding at least one gas selected from the group consisting of hydrogen, nitrogen and deuterium to a device of the step at a constant concentration and pressure, and heat-treating at a predetermined time and temperature. 비휘발성 기억소자의 제조방법에 있어서,In the method of manufacturing a nonvolatile memory device, 수소, 질소 및 중수소로 구성된 그룹에서 선택한 1종 이상의 가스를 일정 농도 및 압력으로 하여 단결정 산화막에 가하고 일정 시간 및 온도로 열처리하는 단계; 및Adding at least one gas selected from the group consisting of hydrogen, nitrogen, and deuterium to a single crystal oxide film at a constant concentration and pressure, and performing heat treatment at a predetermined time and temperature; And 금속 전극 위에 상기 단계의 단결정 산화막을 증착하고 그 위에 다시 금속 전극을 증착하는 단계를 포함하는 것을 특징으로 하는 비휘발성 기억소자의 제조방법.And depositing a single crystal oxide film of the above step on the metal electrode and then depositing a metal electrode thereon. 제 5항 또는 제 6항에 있어서, 상기 단결정 산화막은 티탄산스트론튬(Nb-doped SrTiO3), 산화아연(ZnO2), 산화망간(MnO)으로 구성된 그룹에서 선택된 어느 하나의 산화물에 3족 내지 12족 금속원소로 구성된 그룹에서 선택된 1종 이상의 원소가 도핑된 것을 특징으로 하는 비휘발성 기억소자의 제조방법.The method of claim 5 or 6, wherein the single crystal oxide film is selected from the group consisting of Group 3 to 12 in any one oxide selected from the group consisting of strontium titanate (Nb-doped SrTiO 3 ), zinc oxide (ZnO 2 ), manganese oxide (MnO) A method of manufacturing a nonvolatile memory device, characterized in that one or more elements selected from the group consisting of group metal elements are doped. 제 5항 또는 제 6항에 있어서, 상기 단결정 산화막은 니오브가 도핑된 티탄산스트론튬(Nb-doped SrTiO3), 크롬이 도핑된 티탄산스트론튬(Cr-doped SrTiO3), 란탄이 도핑된 티탄산스트론튬(La-doped SrTiO3), 알루미늄이 도핑된 산화아연(Al-doped ZnO2) 및 Re0.7AE0.3MnO3(Re는 희토류원소, AE는 알칼리토류원소, Mn은 망간, O는 산소)로 구성된 그룹에서 선택하는 것을 특징으로 하는 비휘발성 기억소자의 제조방법.The method of claim 5 or 6, wherein the single crystal oxide film is Niobium-doped strontium titanate (Nb-doped SrTiO 3 ), chromium-doped strontium titanate (Cr-doped SrTiO 3 ), lanthanum-doped strontium titanate (La -doped SrTiO 3 ), aluminum-doped zinc oxide (Al-doped ZnO 2 ) and Re 0.7 AE 0.3 MnO 3 (Re is rare earth element, AE is alkaline earth element, Mn is manganese, O is oxygen) A method of manufacturing a nonvolatile memory device, characterized in that the selection. 제 5항 또는 제 6항에 있어서, 상기 가스의 농도는 전체 중량대비 10 내지 100중량%인 것을 특징으로 하는 비휘발성 기억소자의 제조방법.The method of claim 5 or 6, wherein the concentration of the gas is 10 to 100% by weight based on the total weight. 제 5항 또는 제 6항에 있어서, 상기 가스의 압력은 1 내지 100 기압인 것을 특징으로 하는 비휘발성 기억소자의 제조방법.The method of manufacturing a nonvolatile memory device according to claim 5 or 6, wherein the pressure of the gas is 1 to 100 atmospheres. 제 5항 또는 제 6항에 있어서, 상기 열처리는 300 내지 600℃에서 10 내지 100분간 수행하는 것을 특징으로 하는 비휘발성 기억소자의 제조방법.The method of claim 5, wherein the heat treatment is performed at 300 to 600 ° C. for 10 to 100 minutes. 가스의 압력을 조절하는 압력조절 유닛(1);A pressure regulating unit 1 for regulating the pressure of the gas; 고압 어닐링 챔버에 연결되어 상기 압력조절 유닛으로부터 가스가 유입되는 가스유입구(2);A gas inlet (2) connected to the high pressure annealing chamber and into which gas is introduced from the pressure regulating unit; 고압 어닐링 챔버에 연결되어 챔버 내의 압력을 조절하기 위하여 가스를 유출하는 가스유출구(3);A gas outlet 3 connected to the high pressure annealing chamber to discharge gas to regulate the pressure in the chamber; 단결정 산화막 또는 금속전극을 상부와 하부에 증착한 단결정 산화막에 고압 가스 처리 및 열처리를 가하는 고압 어닐링 챔버(4);A high pressure annealing chamber 4 for applying a high pressure gas treatment and heat treatment to the single crystal oxide film on which the single crystal oxide film or the metal electrode is deposited on the upper and lower portions; 고압 어닐링 챔버에 연결되어 챔버 내의 온도를 조절하는 온도조절기(5);A thermostat 5 connected to the high pressure annealing chamber to regulate the temperature in the chamber; 고압 어닐링 챔버에 연결되어 챔버 내의 압력을 모니터링하는 압력모니터(6); 및A pressure monitor 6 connected to the high pressure annealing chamber to monitor the pressure in the chamber; And 상기 압력모니터 및 온도조절기와 연결되어 챔버 내의 온도와 압력을 제어하는 컴퓨터(7)로 구성된 것을 포함하는 비휘발성 기억소자의 제조장치. And a computer (7) connected to the pressure monitor and the temperature controller to control the temperature and the pressure in the chamber.
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Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8034655B2 (en) 2008-04-08 2011-10-11 Micron Technology, Inc. Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays
US8039297B2 (en) 2008-08-29 2011-10-18 Samsung Electronics Co., Ltd. Plasma treating methods of fabricating phase change memory devices, and memory devices so fabricated
US8134137B2 (en) 2008-06-18 2012-03-13 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US8154906B2 (en) 2008-01-15 2012-04-10 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US8211743B2 (en) 2008-05-02 2012-07-03 Micron Technology, Inc. Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes
US8411477B2 (en) 2010-04-22 2013-04-02 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8427859B2 (en) 2010-04-22 2013-04-23 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8431458B2 (en) 2010-12-27 2013-04-30 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8488365B2 (en) 2011-02-24 2013-07-16 Micron Technology, Inc. Memory cells
US8537592B2 (en) 2011-04-15 2013-09-17 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8581224B2 (en) 2012-01-20 2013-11-12 Micron Technology, Inc. Memory cells
US8753949B2 (en) 2010-11-01 2014-06-17 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cells
US8759809B2 (en) 2010-10-21 2014-06-24 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer
US8791447B2 (en) 2011-01-20 2014-07-29 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8976566B2 (en) 2010-09-29 2015-03-10 Micron Technology, Inc. Electronic devices, memory devices and memory arrays
KR101522439B1 (en) * 2008-05-01 2015-05-21 인터몰레큘러 인코퍼레이티드 Non-volatile resistive-switching memories
US9343665B2 (en) 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US9379319B2 (en) 2013-07-29 2016-06-28 Samsung Electronics Co., Ltd. Nonvolatile memory transistor and device including the same
US9406878B2 (en) 2010-11-01 2016-08-02 Micron Technology, Inc. Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells, and methods of forming memory cells
US9412421B2 (en) 2010-06-07 2016-08-09 Micron Technology, Inc. Memory arrays
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7060586B2 (en) * 2004-04-30 2006-06-13 Sharp Laboratories Of America, Inc. PCMO thin film with resistance random access memory (RRAM) characteristics
DE102004041894B3 (en) * 2004-08-30 2006-03-09 Infineon Technologies Ag A memory device (CBRAM) having memory cells based on a resistance variable active solid electrolyte material and method of manufacturing the same
DE102004046804B4 (en) * 2004-09-27 2006-10-05 Infineon Technologies Ag Resistively switching semiconductor memory
DE102005005938B4 (en) * 2005-02-09 2009-04-30 Qimonda Ag Resistive memory element with shortened erase time, method of manufacture and memory cell arrangement

Cited By (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11393530B2 (en) 2008-01-15 2022-07-19 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US10790020B2 (en) 2008-01-15 2020-09-29 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US8154906B2 (en) 2008-01-15 2012-04-10 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US10262734B2 (en) 2008-01-15 2019-04-16 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US9805792B2 (en) 2008-01-15 2017-10-31 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US9343145B2 (en) 2008-01-15 2016-05-17 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US8674336B2 (en) 2008-04-08 2014-03-18 Micron Technology, Inc. Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays
US8034655B2 (en) 2008-04-08 2011-10-11 Micron Technology, Inc. Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays
KR101522439B1 (en) * 2008-05-01 2015-05-21 인터몰레큘러 인코퍼레이티드 Non-volatile resistive-switching memories
US8211743B2 (en) 2008-05-02 2012-07-03 Micron Technology, Inc. Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes
US9577186B2 (en) 2008-05-02 2017-02-21 Micron Technology, Inc. Non-volatile resistive oxide memory cells and methods of forming non-volatile resistive oxide memory cells
US9559301B2 (en) 2008-06-18 2017-01-31 Micron Technology, Inc. Methods of forming memory device constructions, methods of forming memory cells, and methods of forming semiconductor constructions
US9257430B2 (en) 2008-06-18 2016-02-09 Micron Technology, Inc. Semiconductor construction forming methods
US8134137B2 (en) 2008-06-18 2012-03-13 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US9111788B2 (en) 2008-06-18 2015-08-18 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US9343665B2 (en) 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US9666801B2 (en) 2008-07-02 2017-05-30 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US8039297B2 (en) 2008-08-29 2011-10-18 Samsung Electronics Co., Ltd. Plasma treating methods of fabricating phase change memory devices, and memory devices so fabricated
US9036402B2 (en) 2010-04-22 2015-05-19 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells
US8411477B2 (en) 2010-04-22 2013-04-02 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8743589B2 (en) 2010-04-22 2014-06-03 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8760910B2 (en) 2010-04-22 2014-06-24 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8427859B2 (en) 2010-04-22 2013-04-23 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8542513B2 (en) 2010-04-22 2013-09-24 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US9412421B2 (en) 2010-06-07 2016-08-09 Micron Technology, Inc. Memory arrays
US9887239B2 (en) 2010-06-07 2018-02-06 Micron Technology, Inc. Memory arrays
US10746835B1 (en) 2010-06-07 2020-08-18 Micron Technology, Inc. Memory arrays
US9989616B2 (en) 2010-06-07 2018-06-05 Micron Technology, Inc. Memory arrays
US10656231B1 (en) 2010-06-07 2020-05-19 Micron Technology, Inc. Memory Arrays
US10613184B2 (en) 2010-06-07 2020-04-07 Micron Technology, Inc. Memory arrays
US9697873B2 (en) 2010-06-07 2017-07-04 Micron Technology, Inc. Memory arrays
US10241185B2 (en) 2010-06-07 2019-03-26 Micron Technology, Inc. Memory arrays
US10859661B2 (en) 2010-06-07 2020-12-08 Micron Technology, Inc. Memory arrays
US8976566B2 (en) 2010-09-29 2015-03-10 Micron Technology, Inc. Electronic devices, memory devices and memory arrays
US8883604B2 (en) 2010-10-21 2014-11-11 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell
US8759809B2 (en) 2010-10-21 2014-06-24 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer
US8796661B2 (en) 2010-11-01 2014-08-05 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cell
US9406878B2 (en) 2010-11-01 2016-08-02 Micron Technology, Inc. Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells, and methods of forming memory cells
US9117998B2 (en) 2010-11-01 2015-08-25 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cells
US8753949B2 (en) 2010-11-01 2014-06-17 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cells
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
US8652909B2 (en) 2010-12-27 2014-02-18 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells array of nonvolatile memory cells
US9034710B2 (en) 2010-12-27 2015-05-19 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8431458B2 (en) 2010-12-27 2013-04-30 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US9093368B2 (en) 2011-01-20 2015-07-28 Micron Technology, Inc. Nonvolatile memory cells and arrays of nonvolatile memory cells
US8791447B2 (en) 2011-01-20 2014-07-29 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US9257648B2 (en) 2011-02-24 2016-02-09 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US8488365B2 (en) 2011-02-24 2013-07-16 Micron Technology, Inc. Memory cells
US9424920B2 (en) 2011-02-24 2016-08-23 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US8681531B2 (en) 2011-02-24 2014-03-25 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US8537592B2 (en) 2011-04-15 2013-09-17 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US9184385B2 (en) 2011-04-15 2015-11-10 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8854863B2 (en) 2011-04-15 2014-10-07 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US9142766B2 (en) 2012-01-20 2015-09-22 Micron Technology, Inc. Memory cells containing metal oxides
US8962387B2 (en) 2012-01-20 2015-02-24 Micron Technology, Inc. Methods of forming memory cells
US8581224B2 (en) 2012-01-20 2013-11-12 Micron Technology, Inc. Memory cells
US9379319B2 (en) 2013-07-29 2016-06-28 Samsung Electronics Co., Ltd. Nonvolatile memory transistor and device including the same

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