KR20070114952A - How to form a capacitor - Google Patents

Abstract

In the capacitor forming method for suppressing short circuit defects, a lower mold layer is formed on a substrate, and an upper mold layer is formed on a lower mold layer, the upper mold layer including a material having a lower etching rate than a material forming the lower mold layer with respect to the same etching solution. Partially anisotropically etch the lower mold layer and the upper mold layer to form a first mold layer pattern that exposes the substrate surface and has a first opening having a narrower width toward the bottom, and using an etching solution to form sidewalls of the first opening. Isotropically etching the first mold film exposed to the second mold film pattern to form a second opening having a lower width than the first opening, and forming a surface of the second mold film pattern exposed on the inner wall of the second opening. Thus forming a lower electrode. At least a portion of the upper mold layer is removed while leaving the lower mold layer to form a third mold layer pattern surrounding the lower portion of the lower electrode, and the dielectric layer and the upper electrode are sequentially formed along the surfaces of the third mold layer pattern and the lower electrode. .

Description

Method of forming a capacitor

1 to 13 are schematic cross-sectional views illustrating a method of forming a capacitor according to an embodiment of the present invention.

14 to 16 are schematic cross-sectional views illustrating a method of forming a capacitor according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 insulating film pattern

112: gate 114, 116: contact pad

122: storage node contact 124: etch stop film

126: lower mold film 128: upper mold film

130: first mold film pattern 132: first opening

134: second mold film pattern 136: second opening

138: conductive film 140: sacrificial film

142: lower electrode 144: dielectric film

The present invention relates to a method of forming a capacitor. More specifically, it relates to a method of forming a cylindrical capacitor.

In recent years, in order to secure the capacitance of the capacitor while decreasing the allowable area per unit cell as the degree of integration of the DRAM device increases to the giga level or more, the shape of the capacitor is initially made into a flat structure, and then gradually becomes a box shape or a cylinder. It is formed in a shape. However, in today's Giga-class or higher DRAM devices employing ultra-fine line width technology, the aspect ratio of the capacitor is inevitably increased to have the required capacitance within the allowable cell area.

As the aspect ratio of the cylindrical capacitor increases, defects frequently occur in forming the capacitor. Specifically, the lower width of the lower electrode of the capacitor is smaller than the upper width, so that it is very difficult to form a dielectric film along the lower electrode surface.

In addition, the lower electrode of the capacitor has an unstable structure in a shape where the width of the lower part is narrower than the width of the upper part. Accordingly, a phenomenon in which the lower electrode of the capacitor is inclined or collapses may occur, and thus a 2-bit fail may occur at an upper portion of adjacent capacitors.

In order to solve the problem, by increasing the lower width of the lower electrode compared to the upper width, a method for securing a line width for forming the dielectric film and having a more stable structure has been developed. However, the cylindrical shape is slightly bent at portions divided into upper and lower portions of the lower electrode, and the distance between neighboring lower electrodes becomes very close at the boundary portions of the upper and lower portions. Therefore, the capacitors having the above structure have a problem in that a 2-bit short circuit occurs at the center of the lower electrode.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a method of forming a capacitor having a stable structure and suppressed occurrence of 2-bit short circuit.

According to an aspect of the present invention for achieving the above object, in the capacitor forming method, forming a lower mold film on a substrate. On the lower mold layer, an upper mold layer formed of a material having an etching rate lower than that of the material forming the lower mold layer is formed with respect to the same etching solution. The lower mold layer and the upper mold layer are partially anisotropically etched to form a first mold layer pattern exposing a surface of the substrate and having a first opening having a narrower width toward the lower portion. The lower mold layer exposed to the sidewall of the first opening is isotropically etched using the etching solution to form a second mold layer pattern in which a second opening having a lower width is formed than the first opening. A lower electrode is formed along the surface of the second mold layer pattern exposed on the inner wall of the second opening. At least a portion of the upper mold layer is removed while leaving the lower mold layer to form a third mold layer pattern surrounding the lower portion of the lower electrode. A dielectric film and an upper electrode are sequentially formed along the surfaces of the third mold layer pattern and the lower electrode.

The lower mold layer may be made of BPSG (Boron Phosphorus Silicate Glass) or a dielectric material having a low dielectric constant, and the upper mold layer may be made of Plasma Enhanced-TetraEthyl OrthoSilicate (PE-TEOS). The lower mold layer may have a thickness substantially lower than that of the upper mold layer. The lower electrode forms a conductive film for the lower electrode along the surface of the second mold film pattern, and forms a sacrificial film on the mold film pattern to fill the inside of the first opening in which the conductive film is formed, and an upper surface of the conductive film The sacrificial layer is planarized to expose the sacrificial layer, and the node is removed by removing the exposed conductive layer so that the upper surface of the second mold layer pattern is exposed. Formed by complete removal. The sacrificial layer may be made of ALD oxide (Atomic Layer deposition Oxide).

According to the present invention as described above, the width of the lower end of the lower electrode can be widened to form a capacitor having a more stable structure, it is possible to easily form a dielectric film and the upper electrode on the lower electrode through the deposition process.

In addition, the mold layer pattern may be interposed between the outer walls of the lower end of the lower electrode, thereby preventing the adjacent lower electrodes from being shorted to each other.

Hereinafter, a method for forming a capacitor according to an embodiment of the present invention will be described in detail.

1 to 12 are schematic cross-sectional views illustrating a method of forming a capacitor according to an embodiment of the present invention.

Referring to FIG. 1, a pad oxide film (not shown) and a silicon nitride film (not shown) are sequentially formed on the semiconductor substrate 100. A photoresist pattern (not shown) is formed on the silicon nitride film to selectively expose the silicon nitride film.

A portion of the substrate 100 exposed by the photoresist pattern becomes a field region, and a portion of the substrate 100 masked by the photoresist pattern becomes an active region. The exposed silicon nitride layer and the pad oxide layer are sequentially etched using the photoresist pattern as an etching mask to form a first hard mask pattern (not shown) including the silicon nitride layer pattern and the pad oxide layer pattern.

The exposed semiconductor substrate 100 is etched using the first hard mask pattern as an etch mask to form a trench (not shown). To fill the trench, a silicon oxide film having excellent gap filling characteristics such as Undoped Silicate Glass (USG), O ₃ -TEOS USG (O ₃ -Tetra Ethyl Ortho Silicate Undoped Silicate Glass), or High Density Plasma (HDP) oxide It is formed by a chemical vapor deposition (CVD) method. If necessary, the silicon oxide film (not shown) may be annealed under a high temperature and inert gas atmosphere of about 800 to 1015 ° C. to densify the gap buried oxide film, thereby lowering the wet etch rate for subsequent cleaning processes.

The silicon oxide film is polished by an etch back or chemical mechanical polishing process to form an insulating film pattern 102 in the trench. As a result, the semiconductor substrate 100 is divided into a field region and an active region by the insulating film pattern 102.

Subsequently, a thin gate oxide film 104 is grown on the surface of the active region by thermal oxidation, and then a gate electrode film (not shown) and a hard mask film (not shown) made of a conductive material are formed. The hard mask layer and the gate electrode layer are patterned to form a gate 112 in which the gate electrode pattern 106 and the second hard mask pattern 108 are stacked.

In addition, first spacers 110 formed of silicon nitride are formed on both sides of the gate 112. By implanting impurities using the gate 112 and the first spacer 110 as a mask, a first impurity region to be provided as a source / drain under the substrate 100 on both sides of the gate 112 (not shown) And second impurity regions (not shown). In this case, the first impurity region is subsequently connected to the bit line, and the second impurity region is subsequently connected to the lower electrode of the capacitor.

Forming a first interlayer insulating film (not shown) that sufficiently fills the gate 112, and partially etching the first interlayer insulating film by a photolithography process to expose the first impurity region and the second impurity region, respectively. A self-aligned contact hole (not shown) is formed. The first interlayer insulating layer may be formed using silicon oxide.

After depositing the doped polysilicon in the contact hole, a first contact pad for connecting the first and second impurity regions by performing a planarization process so that the upper surface of the first interlayer insulating film is exposed ( 114 and second contact pads 116 are formed, respectively.

Referring to FIG. 2, a second interlayer insulating layer 118 is formed on the first interlayer insulating layer including the first contact pads 114 and the second contact pads 116.

Although not shown in detail, bit line contacts (not shown) and bit line structures (not shown) are formed in the second interlayer insulating layer 118. In more detail, first, a predetermined portion of the second interlayer insulating layer 118 is etched to form a bit line contact hole (not shown) for selectively exposing only the first contact pad 114. Subsequently, a barrier metal film (not shown) is formed on the bit line contact hole and the second interlayer insulating film 118. The barrier metal film is formed of a titanium, a titanium nitride film, a tantalum, a tantalum nitride film, or a film in which at least two of them are stacked.

Subsequently, a tungsten film (not shown) is formed on the barrier metal film. A silicon nitride film (not shown) is formed on the tungsten film as a capping film. The capping film serves as a hard mask when etching the tungsten film, and also serves to protect the tungsten film during the self-aligned contact forming process. Subsequently, the capping layer is etched to form a capping layer pattern (not shown). The tungsten film and the barrier metal film are etched anisotropically using the capping film pattern as an etching mask. Through the etching process, a bit line structure and a bit line contact including a barrier metal pattern, a tungsten pattern, and a capping layer pattern are simultaneously formed. The bit line structure is electrically connected to the first impurity region by being connected to the first contact pad 114 through the bit line contact.

Referring to FIG. 3, a third interlayer insulating layer 120 is formed to completely bury the bit line structure. The third interlayer insulating layer 120 may be formed by depositing silicon oxide by chemical vapor deposition.

The second interlayer insulating layer 118 and the third interlayer insulating layer 120 are partially removed to form storage node contact holes (not shown) that expose the top surface of the second contact pad 116.

Subsequently, a conductive material is embedded in the storage node contact hole and the conductive material is polished to form storage node contacts 122. The storage node contacts 122 are provided between the bit line structures to electrically connect with the second contact pads 116.

Referring to FIG. 4, an etch stop layer 124 is formed on the third interlayer insulating layer 120 and the storage node contact 122.

The etch stop layer 124 performs a function for identifying an end point of the etch in a process of etching a mold layer (not shown) formed thereafter. Therefore, the material includes an material having an etching selectivity with respect to the mold layer. As an example of the etch stop layer 124, a silicon nitride layer is used. In this case, the mold layer is preferably made of the silicon nitride and the oxide having an etching selectivity.

Referring to FIG. 5, a lower mold layer 126 is formed on the etch stop layer 124 to have a first thickness.

The lower mold layer 126 should have an etching selectivity with respect to the same etching solution as that of the upper mold layer formed thereafter. In the present exemplary embodiment, the lower mold layer 126 may be made of boron phosphorus silicate glass (BPSG) or a dielectric material having a low dielectric constant.

In a subsequent process, a portion of the lower mold layer 126 is interposed between outer walls of the lower electrode lower portion of the capacitor to support the lower portion of the lower electrode.

Referring to FIG. 6, an upper mold layer 128 formed of a material having a lower etching rate than a material forming the lower mold layer 126 may be formed on the lower mold layer 126.

When the lower mold layer 126 is BPSG, plasma-enhanced tetraethylene orthosilicate (PE-TEOS) is applied to the upper mold layer 128 having an etching rate lower than that of the lower mold layer 126 with respect to the hydrofluoric acid (HF) diluent. Can be used.

As the thickness of the upper mold layer 128 increases, the surface area of the lower electrode in contact with the dielectric layer increases. Therefore, the upper mold layer 128 preferably has a second thickness thicker than the first thickness. This will be described later in detail.

Referring to FIG. 7, a third hard mask pattern (not shown) is formed on the upper mold layer 128 to partially expose the upper mold layer 128.

Subsequently, the upper mold layer 128 and the lower mold layer 126 are anisotropically etched using the third hard mask pattern as an etch mask, thereby exposing the etch stop layer 124 and having a narrow width toward the bottom. The first mold layer pattern 130 in which the opening 132 is formed is formed.

As described above, when the lower portion of the first opening 132 has a narrow width, it is very difficult to form the dielectric layer and the upper electrode along the surface of the first mold layer pattern 130 exposed by the first opening 132. In order to overcome this, a process of increasing the width of the lower end of the first opening 132 is performed.

Referring to FIG. 8, a second opening having a lower width than that of the first opening 132 by isotropically etching the lower mold layer 126 exposed to the sidewall of the first opening 132 using the etching solution. A second mold film pattern 134 on which 136 is formed is formed.

Here, the lower mold layer 126 and the upper mold layer 128 have an etching selectivity with respect to the same etching solution. In more detail, the lower mold layer 126 is etched faster than the upper mold layer 128 with respect to the hydrofluoric acid diluent. Accordingly, the lower mold layer 126 exposed on the sidewall of the first opening 132 is isotropically etched to form a second opening 136 having a lower width than the first opening 132.

Here, as the isotropic etching time increases, the etching amount of the lower mold layer 126 increases, and the upper mold layer 128 is gradually etched. Therefore, by adjusting the isotropic etching process time, the lower mold layer 126 may be etched to form a second opening 136 having a lower width than the first opening 132.

Subsequently, the etch stop layer 124 exposed by the second opening 136 is removed to expose the top surface of the storage node contact 122. Here, the width of the bottom surface of the second opening 136 may be partially reduced while removing the etch stop layer 124.

9, a conductive film 138 is formed along the surface of the second mold film pattern 134.

The conductive film 138 is used as a lower electrode of the capacitor. The conductive layer 138 is formed using a conductive material such as polysilicon or metal doped with impurities.

In this case, the conductive layer 138 is formed along the surface profile of the second opening 136 without filling the second opening 136. Therefore, the lower width of the conductive film 138 is formed to have a shape wider than the upper width.

Referring to FIG. 10, a sacrificial layer 140 is formed on the second mold layer pattern 134 to completely fill the inside of the second opening 136 in which the conductive layer 138 is formed.

The sacrificial layer 140 then serves to protect the lower electrode during the storage node separation process and subsequent processes for forming the lower electrode. ALD oxide may be used as the sacrificial layer 140. At this time, the ALD oxide has a higher etching rate than the PE-TEOS for the LAL etching solution. Therefore, the sacrificial layer 140 is etched faster than the upper mold layer 128 with respect to the LAL etching solution.

Referring to FIG. 11, the sacrificial layer 140 is planarized to expose the top surface of the conductive layer 138.

Subsequently, the exposed conductive layer 138 is removed to form a node-separated lower electrode 142. At this time, the lower electrode 142 has a cylinder shape in which the width of the lower portion is wider than the width of the upper portion.

As described above, since the lower portion of the lower electrode 142 is wide, the dielectric layer and the upper electrode may be easily formed through a conventional deposition process. In addition, the width of the lower portion of the lower electrode 142 is widened to form a capacitor having a more stable structure.

Referring to FIG. 12, at least a portion of the upper mold layer 128 is removed while leaving the lower mold layer 126 to form a third mold layer pattern 144 surrounding the lower portion of the lower electrode 142. do.

The upper mold layer 128 is made of PE-TEOS and wet-etched by the LAL solution. In this case, only a part of the upper mold layer 128 is removed to prevent the lower mold layer 126 from being exposed.

During the removal of a portion of the upper mold layer 128, the sacrificial layer 140 made of ALD oxide is removed. The sacrificial layer 140 has a higher etching rate with respect to the LAL etching solution than the upper mold layer 128, and the sacrificial layer 140 is completely removed while a portion of the upper mold layer 128 is removed. The inner side of the lower electrode 142 is exposed.

In addition, the upper mold layer 128 is removed to expose the upper portion of the outer wall of the lower electrode 142. At this time, as the portion where the lower electrode 142 is exposed increases, the deposition area of the dielectric layer increases, thereby increasing the capacitance of the capacitor. Therefore, it is preferable to remove most of the upper mold layer 128.

As a result, a portion of the lower mold layer 126 and the upper mold layer 128 remain to form a third mold layer pattern 144, and the third mold layer pattern 144 is at the lower end of the lower electrode 142. It is formed to surround. Therefore, contact between neighboring lower electrodes 142 can be prevented in advance, and the structure is also very stable.

In addition, since the width of the lower portion of the lower electrode 142 is widened, the dielectric layer and the upper electrode can be easily formed.

Referring to FIG. 13, dielectric layers 146 and upper electrodes (not shown) are sequentially formed along surfaces of the third mold layer pattern 144 and the lower electrode 142. The dielectric layer 146 is formed by depositing a metal oxide having a high dielectric constant. Examples of the metal oxides include aluminum oxide and hafnium oxide. The dielectric layer 146 may be formed by a CVD process or an ALD process.

Next, an upper electrode formed of a metal material or a polysilicon material is formed on the dielectric film 146. The upper electrode may be formed of the same material as the lower electrode 142.

In this case, the width of the lower portion of the lower electrode 142 is wider than that of the related art, and thus the dielectric layer 146 and the upper electrode may be easily formed.

As a result, a capacitor including the lower electrode 142, the dielectric layer 146, and the upper electrode is formed. The capacitor as described above has a cylindrical shape in which the width of the lower portion is wider than the width of the upper portion.

As described above, the width of the lower part is wide, so that the dielectric layer 146 and the upper electrode may be easily formed in the lower electrode 142, and the outer surface of the lower end of the lower electrode 142 may be formed on the third mold layer pattern 144. It is wrapped by the lower electrode 142 can be prevented in advance. In addition, the sacrificial layer 140 inside the lower electrode 142 may be completely removed to form a dielectric layer 146 and an upper electrode up to an inner lower portion of the lower electrode 142, thereby increasing capacitance of the capacitor.

Hereinafter, a capacitor forming method according to another embodiment of the present invention will be described in detail.

14 to 16 are schematic cross-sectional views illustrating a method of forming a capacitor according to another embodiment of the present invention.

Referring to FIG. 14, by performing the same process as described with reference to FIGS. 1 to 5, the gate 204, the first contact pad 206, the second contact pad 208, The storage node contact 214 and the etch stop layer 216 may be formed. Reference numerals 210 and 214, which are not described, refer to second and third interlayer insulating films, respectively.

A plurality of mold layers having different etching selectivity are formed on the etch stop layer 216. In this case, two or more mold layers may be provided. In the present embodiment, three mold films are used, but the number of mold films is not limited in the present invention.

The lower mold layer 218, the middle mold layer 220, and the upper mold layer 222 are formed on the etch stop layer 216. In this case, the lower mold layer 218, the middle mold layer 220, and the upper mold layer 222 have an etching selectivity with respect to the same etching solution. In more detail, for the same etching solution, the lower mold layer 218 has a higher etching rate than the middle mold layer 220, and the middle mold layer 220 has a higher etching rate than the upper mold layer 222. high. That is, the etching rate decreases in the order of the lower mold layer 218, the middle mold layer 220, and the upper mold layer 222 with respect to the same etching solution.

Referring to FIG. 15, a hard mask pattern is formed on the upper mold layer 222, and the upper mold layer 222, the middle mold layer 220, and the lower mold layer are formed by using the hard mask pattern as an etching mask. Anisotropically etch the 218 to form a first mold layer pattern 224 having a first opening 226 that is narrower toward the bottom. In this case, an etch stop layer 216 is exposed on a bottom surface of the first opening 226.

Subsequently, the lower mold layer 218 exposed by the side surface of the first opening 226 isotropically etched by the etching solution to form a second opening (not shown) having a lower width than the first opening 226. The resulting second mold film pattern (not shown) is formed.

In this case, the middle mold layer 220 is etched less than the amount of the lower mold layer 218 is etched, and the upper mold layer 222 is etched more than the etching amount, as shown in the upper mold layer ( 222 and the middle mold layer 220 has a step.

That is, the second opening has a shape in which the width of the lower portion is wider than the width of the central portion, has a step in the central portion, and the width thereof becomes wider toward the upper portion.

Subsequently, the etch stop layer 216 exposed to the bottom of the second opening is removed to expose the top surface of the storage node contact 214.

Referring to FIG. 16, a conductive film (not shown) is formed along the second mold film pattern. The conductive layer may be used as a lower electrode of a capacitor, and a conductive material such as polysilicon or a metal doped with impurities may be used as the conductive layer.

A sacrificial layer (not shown) is formed on the second mold layer pattern to completely fill the inside of the second opening in which the conductive layer is formed, and the sacrificial layer is planarized to expose the upper surface of the conductive layer. In this case, the sacrificial layer is made of a material having a higher etching rate than a material forming the upper mold layer 222 and the middle mold layer 220 in the same etching solution.

Subsequently, the exposed conductive layer is removed to form the lower electrode 230 separated from the node. In this case, the lower electrode 230 has a cylindrical shape in which the width of the lower portion is wider than the width of the central portion, and the width thereof becomes wider from the middle portion to the upper portion.

Subsequently, at least a portion of the middle mold layer 220 and all of the upper mold layer 222 are removed while leaving the lower mold layer 218 to surround the lower portion of the lower electrode 230. Pattern 228 is formed.

In this case, during the etching of the upper mold layer 222 and the middle mold layer 220, the sacrificial layer is rapidly etched in the same etching solution as compared to the upper or middle mold layer 220, and thus, the inside of the lower electrode 230 may be etched. Expose the sides as a whole.

In addition, a portion of the outer surface of the lower electrode 230 is exposed. In more detail, all of the upper mold layer 222 and a part of the middle mold layer 220 are removed to expose the outer surfaces of the middle and upper portions of the lower electrode 230. In this case, the height of the exposed outer surface of the lower electrode 230 may be determined according to the thicknesses of the upper and middle mold layers 220 and the amount of the middle mold layer 220 removed.

As a result, a portion of the lower mold layer 218 and the middle mold layer 220 remain to form a third mold layer pattern 228, and the third mold layer pattern 228 is at the lower end of the lower electrode 230. It is formed to surround. Therefore, contact between neighboring lower electrodes 230 can be prevented in advance, and the structure is also very stable.

In addition, since the width of the lower portion of the lower electrode 230 is widened, the dielectric layer and the upper electrode may be easily formed.

Subsequently, a dielectric layer 232 and an upper electrode (not shown) are sequentially formed along the third mold layer pattern 228 and the lower electrode 230 surface. As a result, it is possible to form a capacitor which is structurally stable and suppresses a short circuit phenomenon under the lower electrode 230.

As described above, according to the preferred embodiment of the present invention, since the lower electrode has a wider width than the upper portion thereof, a dielectric film and an upper electrode formed on the lower electrode can be easily formed, and sacrificed inside the lower electrode. The film may be completely removed to form the dielectric film and the upper electrode up to the inner bottom of the lower electrode, thereby increasing the capacitance of the capacitor.

In addition, the lower width of the lower electrode is wider to have a more stable structure, and a third mold layer pattern is wrapped around the lower electrode, thereby preventing short circuits between neighboring lower electrodes.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (5)

Forming a lower mold layer on the substrate; Forming an upper mold layer on the lower mold layer, wherein the upper mold layer is formed of a material having a lower etching rate than a material forming the lower mold layer with respect to the same etching solution; Partially anisotropically etching the lower mold layer and the upper mold layer to form a first mold layer pattern exposing a surface of the substrate and having a first opening having a narrower width toward the bottom; Isotropically etching the lower mold layer exposed on the sidewalls of the first opening using the etching solution to form a second mold layer pattern in which a second opening having a lower width is formed than the first opening; Forming a lower electrode along a surface of a second mold layer pattern exposed on an inner wall of the second opening; Removing at least a portion of the upper mold layer while leaving the lower mold layer to form a third mold layer pattern surrounding the lower portion of the lower electrode; And And sequentially forming a dielectric film and an upper electrode along surfaces of the third mold layer pattern and the lower electrode. The capacitor of claim 1, wherein the lower mold layer is made of BPSG (Boron Phosphorus Silicate Glass) or a dielectric material having a low dielectric constant, and the upper mold layer is made of Plasma Enhanced-TetraEthyl OrthoSilicate (PE-TEOS). Forming method. The method of claim 1, wherein the lower mold layer is formed to have a thickness substantially lower than that of the upper mold layer. The method of claim 1, wherein the forming of the lower electrode comprises: Forming a conductive film for a lower electrode along a surface of the second mold film pattern; Forming a sacrificial layer on the mold layer pattern to fill the inside of the first opening in which the conductive layer is formed; Planarizing the sacrificial layer to expose an upper surface of the conductive layer; Removing the exposed conductive layer so as to expose the top surface of the second mold layer pattern to separate the nodes; And And completely removing the sacrificial film while removing a portion of the upper mold film of the second mold film pattern. The method of claim 4, wherein the sacrificial layer is made of ALD oxide (Atomic Layer deposition Oxide).

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