KR20070113812A - LCD panel - Google Patents

Abstract

A liquid crystal display panel for improving display quality is disclosed. The liquid crystal display panel includes a display substrate, an opposing substrate, and a liquid crystal layer. The display substrate is formed on the pixel portion partitioned into the first domain and the second domain, and electrically connected to the first sub electrode and the first sub electrode corresponding to the first domain, and the second sub corresponding to the second domain. An electrode. The opposing substrate is disposed to face the display substrate, and includes a common electrode having a first hole corresponding to the center portion of the first sub electrode and a second hole corresponding to the center portion of the second sub electrode. The liquid crystal layer is interposed between the display substrate and the opposing substrate. In this case, a first opening pattern surrounding the first hole is formed in the first sub-electrode, and a second opening pattern surrounding the first opening pattern is formed in the common electrode. Accordingly, the interval between electric field lines formed in the pixel portion is narrowed, so that the response speed delay section of the liquid crystal layer can be reduced.

Description

Liquid Crystal Display Panel {LIQUID CRYSTAL DISPLAY PANEL}

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 is a plan view illustrating only a pixel electrode separated from the liquid crystal display panel of FIG. 1.

FIG. 4 is a plan view illustrating only a common electrode separated from the liquid crystal display panel shown in FIG. 1.

<Description of the symbols for the main parts of the drawings>

100 display substrate 110 first transparent substrate

120: gate electrode 130: gate insulating layer

140: channel layer 154: source electrode

156: drain electrode 157: crosslinked electrode

158: storage electrode 160: passivation layer

170: organic insulating layer 180: pixel electrode

200: opposing substrate 210: second transparent substrate

220: light shielding layer 230: color filter layer

240: overcoat layer 250: common electrode

The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display panel for improving display quality.

In general, a liquid crystal display panel includes an array substrate on which a thin film transistor (TFT) for switching driving of each pixel is formed, an opposing substrate on which a common electrode is formed, and a liquid crystal layer sealed between the two substrates. The liquid crystal display panel displays an image by applying a voltage to the liquid crystal layer to control light transmittance.

In the liquid crystal display panel, a VA mode has been developed in which liquid crystal molecules are arranged in a vertical direction to display black when no voltage is applied between the two substrates. Recently, in order to improve the viewing angle of the VA mode, a PVA mode has been developed in which opening patterns are formed in the common electrode and the pixel electrode to define multiple domains in each pixel.

On the other hand, in the PVA mode, the response speed of the liquid crystal is high in the domain edge region where the electric field lines are generated and the region adjacent to the opening pattern, but the distance from the electric field line becomes far in the middle region corresponding to the edge region and the opening pattern. There is a disadvantage that the response speed of the liquid crystal is relatively slow. In particular, when the number of domains defined in the pixel is small, the width of the intermediate region is increased, and thus, the response speed of the liquid crystal in the intermediate region is further slowed. Accordingly, when the number of domains defined in the pixel is increased to improve the response speed of the liquid crystal, the aperture ratio of the pixel is lowered, thereby reducing the luminance of the display screen.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a liquid crystal display panel for improving display quality by making the response speed of the liquid crystal layer uniform.

In order to achieve the above object of the present invention, a liquid crystal display panel includes a display substrate, an opposing substrate, and a liquid crystal layer. The display substrate is formed on the pixel portion partitioned into a first domain and a second domain, and is electrically connected to the first sub-electrode corresponding to the first domain and the first sub-electrode and corresponding to the second domain. It includes a second sub electrode. The opposing substrate may be disposed to face the display substrate and include a common electrode having a first hole corresponding to a center portion of the first sub-electrode and a second hole corresponding to a center portion of the second sub-electrode. The liquid crystal layer is interposed between the display substrate and the opposing substrate. A first opening pattern surrounding the first hole is formed in the first sub-electrode, and a second opening pattern surrounding the first opening pattern is formed in the common electrode.

According to such a liquid crystal display panel, it is possible to reduce the response speed study between the liquid crystal layers disposed in each domain.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

1 and 2, the liquid crystal display device 400 may include a display substrate 100, an opposing substrate 200 facing the display substrate 100, and a gap between the display substrate 100 and the opposing substrate 200. It includes a liquid crystal layer 300 interposed therein.

The display substrate 100 includes a first transparent substrate 110. On the first transparent substrate 110, a plurality of gate lines GLn-1 and GLn .. extending in a first direction and a plurality of source lines DLm− extending in a second direction crossing the first direction. 1, DLm ..) is formed. A plurality of pixel parts is defined on the first transparent substrate 110 by the source wirings and the gate wirings.

Specifically, each pixel portion P includes a gate electrode 120 connected to the nth gate line GLn, a source electrode 154 connected to the mth source line DLm, and the source electrode 154. A switching element TFT including the drain electrodes 156 spaced apart from each other is formed.

The gate insulating layer 130 and the semiconductor layer 140 are sequentially formed between the gate electrode 120 and the source and drain electrodes 154 and 156 of the switching element TFT. The gate insulating layer 130 is formed to correspond to the entire surface of the first transparent substrate 110. For example, the gate insulating layer 130 may be formed of silicon nitride (SiNx), and may be formed by plasma enhanced chemical vapor deposition (PECVD).

The semiconductor 140 layer is formed on the gate insulating layer 130 to overlap the gate electrode 120, and has a structure in which an active layer 140a and an ohmic contact layer 140b are stacked. For example, the active layer 140a is made of amorphous silicon (a-Si: H), and the ohmic contact layer 140b is made of amorphous silicon (n + a-Si: H) doped with a high concentration of n-type impurities. . In this case, the ohmic contact layer 140b is removed from the source electrode 154 and the drain electrode 156 to expose the active layer 140a.

The drain electrode 156 extends in the first direction to be parallel to the nth gate line GLn in the pixel portion P. Therefore, the drain electrode 156 covers one end portion adjacent to the n-th gate line GLn of the pixel portion P.

The storage common line STL extending in the first direction is formed between the n−1 th gate line GLn−1 and the n th gate line GLn. The gate lines GLn−1 and GLn and the storage common line STL are formed on the same layer in a first metal pattern, and the storage common line STL defines the pixel portion P as a first domain. It partitions into A1) and the 2nd domain A2. In this case, it is preferable that the first domain A1 and the second domain A2 are divided into the same area.

The storage electrode 158 is formed on the storage common line STL formed in the pixel portion P with the gate insulating layer 130 interposed therebetween. The storage electrode 158 is electrically connected to the drain electrode 156 through a bridged electrode 157. The source wirings DLm-1 and DLm, the storage electrode 158, the bridged electrode 157, and the drain electrode 156 are formed on the same layer in a second metal pattern.

The storage common line STL and the storage electrode 158 form a storage capacitor CST using the gate insulating layer 130 as a dielectric. The storage capacitor CST is charged with a pixel voltage sufficient to hold an image for one frame.

The passivation layer 160 and the organic insulating layer 170 are sequentially formed on the gate insulating layer 130 on which the second metal pattern is formed. The passivation layer 160 may be formed of a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx), and may be formed by chemical vapor deposition. For example, the organic insulating layer 170 may be formed of a photosensitive organic composition made of a transparent material, and planarize the display substrate 100 on which the switching element TFT is formed. A contact hole 172 exposing a portion of the storage electrode 158 is formed in the passivation layer 160 and the organic insulating layer 170. A plurality of contact holes 172 formed on each storage electrode 158 may be formed.

The pixel electrode 180 is formed on the organic insulating layer 170 corresponding to each pixel portion P. The pixel electrode 180 will be described in detail with reference to FIGS. 1 to 3.

3 is a plan view illustrating only a pixel electrode separated from the liquid crystal display panel of FIG. 1.

1 to 3, the pixel electrode 180 is made of a transparent conductive material through which light can pass. For example, the pixel electrode 180 is made of indium tin oxide (ITO), indium zinc oxide (IZO), or the like, and is patterned to correspond to each pixel portion P by a photo-etching process. It is preferable that the separation interval between the pixel electrodes formed in the adjacent pixel portions is approximately 4 μm.

In detail, the pixel electrode 180 formed in the pixel portion P may include a first sub-electrode S1 corresponding to the first domain A1 and a second sub-electrode corresponding to the second domain A2. S2) and a third sub-electrode S3 connecting the first sub-electrode S1 and the second sub-electrode S2.

The first sub-electrode S1 forms an electric field with the common electrode 250 formed on the counter substrate 200 to arrange liquid crystal molecules of the liquid crystal layer 300 corresponding to the first domain A1.

Similarly, the second sub-electrode S2 forms an electric field with the common electrode 250 formed on the counter substrate 200 to arrange liquid crystal molecules of the liquid crystal layer 300 corresponding to the second domain A2. .

The third sub-electrode S3 is formed on the storage common line STL and connects the first sub-electrode S1 and the second sub-electrode S2. In this case, the third sub-electrode S3 is formed to have a narrower width than the first and second sub-electrodes S1 and S2 to clearly distinguish the first sub-electrode S1 and the second sub-electrode S2. do.

In addition, the third sub-electrode S3 contacts the storage electrode 158 through the contact hole 172 and receives a pixel voltage provided from the switching element TFT. The pixel voltage applied to the third sub electrode S3 is provided to the first sub electrode S1 and the second sub electrode S2.

Meanwhile, a first opening pattern 181 and a second opening pattern 182 are formed in the first sub electrode S1 and the second sub electrode S2, respectively. The first opening pattern 181 is formed to surround the first hole H1 formed in the common electrode 250 on a plane.

The first opening pattern 181 is formed to have a width of 3 to 4 μm, for example. The first opening pattern 181 divides the first sub-electrode S1 into a first internal electrode IE1 and a first external electrode OE1 surrounding the first internal electrode IE1. In this case, a first connection electrode BE1 is formed between the first internal electrode IE1 and the first external electrode OE1 to electrically connect the first internal electrode IE1 and the first external electrode OE2. Connect it. The first connection electrode BE1 may be formed in plural in symmetrical areas.

The second opening pattern 182 is formed to surround the second hole H2 formed in the common electrode 250 on a plane. The second opening pattern 182 may be formed to have the same width as the first opening pattern 181. The second sub-electrode is formed by the second opening pattern 182 to surround the second internal electrode IE2 and the second internal electrode IE2 formed inside the second opening pattern 182. It is partitioned by the electrode OE2. A second connection electrode BE2 is formed between the second internal electrode IE2 and the second external electrode OE2 to electrically connect the second internal electrode IE2 and the second external electrode OE2. Let's do it.

1 and 3 illustrate the first and second opening patterns 181 and 182 in a quadrangular shape, but the shapes of the first and second opening patterns 181 and 182 are not limited thereto. It may be formed as.

The display substrate 100 may include first and second light blocking patterns formed at a lower width of the source lines DLm-1, DLm, and DLm + 1 than the source lines DLm-1 and DLm. 122, 124). The first and second light blocking patterns 122 and 124 may be formed of the same first metal pattern as the gate lines GLn-1 and GLn and the storage common line STL. The first and second light blocking patterns 122 and 124 prevent back light from being provided to areas where the pixel electrode 180 is not covered between the pixel parts P adjacent in the first direction. In detail, the first light blocking pattern 122 is formed between the first sub electrodes S1. The second light blocking pattern 124 is formed between the second sub electrodes S2. Accordingly, it is possible to prevent leakage light due to abnormal operation of the liquid crystal generated in the region where the pixel electrode 180 between the pixel portions P1 and P2 adjacent in the first direction is not covered.

Although not illustrated, the display substrate 100 may be formed on the first transparent substrate 110 on which the pixel electrode 180 is formed, and may further include a first alignment layer for aligning the liquid crystal layer 300. .

1 and 2, the opposing substrate 200 includes a second transparent substrate 210. The light blocking layer 220, the color filter layer 230, the overcoat layer 240, and the common electrode 250 are sequentially formed on the opposite surface of the second transparent substrate 210 facing the display substrate 100. .

The light blocking layer 220 is formed to correspond to the gate line GL, the source line DL, and the switching element TFT, and the pixel electrode 180 is not formed between the pixel portions P adjacent to each other. Blocks leaked light from unseen areas. The light blocking layer 220 is formed of, for example, a photosensitive organic composition of a material capable of blocking light, and may be patterned through a series of photolithography.

The color filter layer 230 includes a plurality of color filters formed corresponding to each pixel unit P. For example, the color filter layer 230 is formed of a color filter of red, green, and blue. The color filters may be formed to overlap a predetermined interval on the light blocking layer 220.

The overcoat layer 240 flattens the second transparent substrate 210 on which the light blocking layer 220 and the color filter layer 230 are formed. The overcoat layer 240 is preferably formed of a transparent material. On the other hand, the overcoat layer 240 may be omitted.

The common electrode 250 will be described in detail with reference to FIGS. 1, 2, and 4.

FIG. 4 is a plan view illustrating only a common electrode separated from the liquid crystal display panel shown in FIG. 1.

1, 2 and 4, the common electrode 250 is formed on the overcoat layer 240 to correspond to the entire surface of the opposing substrate 200, and correspond to the pixel portion P. The predetermined opening pattern is formed.

In detail, a first hole H1 and a third opening pattern 251 are formed in the common electrode 250 to correspond to the first domain A1 of the pixel portion P. The first hole H1 is formed at the center of the first domain A1 and corresponds to the center of the first internal electrode IE1. The first hole H1 is preferably formed to have a diameter of about 10 μm.

The third opening pattern 251 is formed to surround the first opening pattern 181 on a plane, and may be formed to have a width spaced apart from the first opening pattern 181 by a predetermined interval, or the first opening. It may be formed adjacent to the pattern 181. In this case, the third opening pattern 251 may be formed to have the same width as the first opening pattern 181.

Although not shown, the third opening pattern 251 may be formed inside the first opening pattern 181.

A second hole H1 and a fourth opening pattern 252 are formed in the common electrode 250 corresponding to the second domain A2 of the pixel portion P. The second hole H2 is formed at the center of the second domain A1 and corresponding to the center of the second internal electrode IE2. The second hole H2 is formed to have the same size as the first hole H1.

The fourth opening pattern 252 is formed to surround the second opening pattern 182 on a plane, and may be formed to have a predetermined width spaced apart from the second opening pattern 182. It may be formed adjacent to the pattern 182. In this case, the fourth opening pattern 252 is preferably formed to have the same width as the second opening pattern 182.

Although not illustrated, the fourth opening pattern 252 may be formed inside the second opening pattern 182.

Hereinafter, an arrangement of liquid crystal molecules included in the liquid crystal layer 300 will be conceptually described with reference to FIGS. 1 and 2. The liquid crystal molecules exist in a vertical alignment state when no electric field is formed between the display substrate 100 and the counter substrate 200, and light does not pass through the liquid crystal molecules. Hereinafter, a case in which an electric field is formed between the display substrate 100 and the counter substrate 200 will be described using the first domain A1 as an example.

When voltage is applied to the pixel electrode 180 and the common electrode 250, an electric force line is formed in an oblique direction in the edge region of the first hole H1, and quickly responds to liquid crystal molecules adjacent thereto. Accordingly, liquid crystal molecules are rearranged in a direction perpendicular to or horizontal to the electric line of force around the first hole H1 to transmit light.

Similarly, an electric force is formed in an oblique direction in the edge region of the first sub-electrode S1, and responds quickly to liquid crystal molecules adjacent thereto. Accordingly, liquid crystal molecules are rearranged in the edge region in a direction perpendicular to or horizontal to the electric field line to transmit light.

Meanwhile, since the distance between the edge area of the first hole H1 and the first sub-electrode S1 is wide, the distance between electric field lines formed in the first domain A1 also increases. Accordingly, the liquid crystal molecules disposed between the electric force lines and the electric force lines have a relatively slow response speed compared to the liquid crystal molecules adjacent to the electric force lines.

Therefore, in the present invention, the first opening pattern 181 and the third opening pattern 251 are formed between the first hole H1 and the edge region of the first sub-electrode S1. Since the first opening pattern 181 and the third opening pattern 251 are formed to be offset from each other, an electric force line is also formed in an oblique direction between the first opening pattern 181 and the third opening pattern 251. Therefore, the liquid crystal molecules adjacent to the first opening pattern 181 and the third opening pattern 251 are quickly rearranged in a direction perpendicular to or horizontal to the electric line of the diagonal line to transmit light.

That is, the first opening pattern 181 and the third opening pattern 251 are formed between the first hole H1 and the edge area of the first sub-electrode S1 in the first domain A1. The spacing between electric field lines generated can be reduced. Accordingly, the response speed of the liquid crystal molecules disposed in the first domain A1 can be made uniform throughout, and display quality can be improved.

The liquid crystal array in the second domain A2 is also substantially the same as the liquid crystal array in the first domain A1, and thus description thereof will be omitted.

In the present exemplary embodiment, the first, second, third and fourth opening patterns 181, 182, 251, and 252 are formed in one pixel portion P, respectively. ) May be formed in plural numbers, respectively.

As described above, in the PVA mode in which a plurality of domains are defined in the pixel portion, the gap between the electric field lines generated in each domain can be reduced by forming opening patterns that are not overlapped with each other in the pixel electrode and the common electrode formed in each domain. have. Accordingly, since the response speed of the liquid crystal molecules disposed in each domain can be made uniform, the display quality of the liquid crystal display panel can be improved.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (5)

A second sub electrode formed on the pixel portion partitioned into a first domain and a second domain, electrically connected to a first sub electrode corresponding to the first domain and the first sub electrode, and corresponding to the second domain; A display substrate including an electrode; An opposing substrate disposed opposite the display substrate and including a common electrode having a first hole corresponding to a central portion of the first sub electrode and a second hole corresponding to a central portion of the second sub electrode; And A liquid crystal layer interposed between the display substrate and the opposite substrate, And a first opening pattern that surrounds the first hole on the first sub-electrode and a second opening pattern that surrounds the first opening pattern on the common sub-electrode. The method of claim 1, wherein the first sub-electrode First internal electrodes disposed inside the first opening pattern; A first external electrode disposed outside the first opening pattern; And And a first connection electrode connecting the first internal electrode and the first external electrode. The liquid crystal display panel of claim 1, wherein the first opening pattern and the second opening pattern are formed to have the same width. The liquid crystal display panel of claim 3, wherein the first opening pattern and the second opening pattern have a width of 3 to 4 μm. The method of claim 1, wherein a third opening pattern is formed in the second sub-electrode to surround the second hole, and a fourth opening pattern is formed in the common electrode to enclose the third opening pattern. LCD panel.

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