KR20070102825A - Pseudo SRM's Wordline Control Circuit for Continuous Burst Mode Operation - Google Patents

Abstract

The present invention relates to a word line control circuit of a pseudo SRAM capable of continuous burst mode operation. When a word line is changed during continuous burst mode operation, the word line control circuit considers the time required for the read and write operation of the repair cell. By delaying and generating the control signal for controlling the word line counter, the word line control circuit of pseudo SRAM which executes a read or write operation to the cell even if the last cell of the word line is a repair cell is disclosed.

Description

Word line control circuit of Pseudo SRAM for continuous burst mode operation

1 is a circuit diagram of a memory cell array of a general pseudo SRAM.

2 is a circuit diagram of a word line control circuit of a pseudo SRAM according to the prior art.

3 is a block diagram of a word line control circuit of a pseudo SRAM in accordance with an embodiment of the present invention.

4 is a circuit diagram of the word line reset signal generator of FIG. 3.

5 is a circuit diagram of a detection signal generator of FIG. 3.

6 is a circuit diagram of the counter control circuit of FIG. 3.

<Description of the symbols for the main parts of the drawings>

1: memory cell array 10, 100: word line control circuit

20: word line detection signal generator 21: logic combination unit

22: detection signal generator 30, 150: counter control circuit

110: address detection unit 120: cas latency delay unit

130: word line reset signal generator 140: detection signal generator

160: address counter

The present invention relates to a pseudo SRAM, and more particularly to a word line control circuit of the pseudo SRAM.

Recently, researches on so-called pseudo SRAMs that implement an SRAM-like operation using a cell of a DRAM have been actively conducted. Pseudo SRAM has the advantage of achieving high integration while reducing the chip size compared to the conventional SRAM.

1 is a circuit diagram of a memory cell array of a general pseudo SRAM.

Referring to FIG. 1, in the memory cell array 1, a plurality of word lines WL0 to WLn and a plurality of bit lines BL0 to BLm cross each other and cross one word line (for example, WL9). One memory cell (cells 0 to cell m) is connected to each of the plurality of bit lines BL0 to BLm.

In continuous burst mode operation, pseudo SRAM uses an externally accepted address to enable the corresponding word line (eg, WL9). Thereafter, columns are internally enabled in order to perform read and write operations on the corresponding memory cells (cells 0 to m). This operation detects the last column (column corresponding to cell m) and enables the next word line WL10.

2 is a circuit diagram of a word line control circuit of a pseudo SRAM according to the prior art.

Referring to FIG. 2, the word line control circuit 10 includes a word line detection signal generator 20 and a counter control circuit 30.

The word line detection signal generator 20 delays an output signal of the address detection unit 21 and the address detection unit 21 which logically combines the control signal wrap6 and the column address signals cay1 to cay6 for a predetermined time. The detection signal generator 22 generates a detection signal det in response to the delayed signal. The control signal wrap6 is a signal having a high state in the detection operation of the column address.

The counter control circuit 30 generates a control signal cnx0 for controlling a row address counter (not shown) that generates a row address signal in response to the detection signal det. Each time the control signal cinc0 is generated, the enabled word line is changed.

Meanwhile, in the case of a repair cell, a read and write operation takes longer than that of a normal cell. However, the word line control circuit according to the related art generates the control signal ccin0 as soon as the column address signals cay1 to cay6 are all input at a high level. Therefore, if the last cell (cell m) of the word line WL9 is a normal cell in the situation where the word line is changed (changes from WL9 to WL10), the next word line WL10 is enabled after a read and write operation. However, if the last cell (cell m) is a repair cell, the read and write operations are not performed and the next word line WL10 is enabled.

Accordingly, a technical problem of the present invention is to delay the control signal for controlling the word line counter in consideration of the time required for the read and write operation on the repair cell in the word line control circuit when the word line is changed during continuous burst mode operation. The present invention provides a word line control circuit of pseudo SRAM that performs a read or write operation on a cell even if the last cell of the word line is a repair cell.

The word line control circuit of the pseudo stack tick ram according to the present invention for achieving the above technical problem includes an address detector, a cas latency delay unit, a word line reset signal generator, a detection signal generator, a counter control circuit, and a word line counter. do.

The address detector generates an address detection signal in response to the column address signal. The cas latency delay unit delays the address detection signal by the cas latency and outputs a delay signal. The word line reset signal generator generates a word line reset signal having a different delay time in a write operation and a read operation in response to the delay signal and the write signal or the read signal. The detection signal generator generates a detection signal in response to the delay signal and the control signal. The counter control circuit outputs a counter control signal in response to the word line reset signal and the detection signal. The word line counter outputs a low address signal in response to the counter control signal.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a block diagram of a word line control circuit of a pseudo SRAM in accordance with an embodiment of the present invention.

Referring to FIG. 3, the word line control circuit 100 responds to the address detector 110, the cascade latency delay unit 120, the delay signal B, the write signal wt, and the read signal rde. And a word line reset signal generator 130 for generating a word line reset signal reset_wl, a detection signal generator 140, a counter control circuit 150, and a word line counter 160.

The address detector 110 generates an address signal add in response to the column addresses cay1 to cay6 and the control signal wrap6.

The cas latency delay unit 120 generates the delay signal B by delaying the address signal add by the cas latency.

The word line reset signal generator 130 receives the delay signal B and generates a word line reset signal reset_wl in response to the write signal wt or the read signal rd.

The detection signal generator 140 receives the delay signal B and generates a detection signal det in response to the control signal web4. The control signal web4 is a signal output at a low level during the write operation and at a high level during the read operation.

The counter control circuit 150 generates a control signal cnx0 in response to the word line reset signal reset_wl and the detection signal det. In addition, the counter control circuit 150 initializes the control signal cinx0 in response to a reset signal or a power-up signal pwrup.

The word line counter 160 generates a row address signal row_add by counting word lines in response to the control signal cnx0. The row address signal row_add changes a word line that is enabled.

4 is a circuit diagram of the word line reset signal generator 130 of FIG. 3.

Referring to FIG. 4, the word line reset signal generator 130 includes a path selector 131, a latch 132, a word line reset signal generator 133, and a buffer 134.

The path selector 131 includes a level shift 131S and transfer gates PT1 and PT2. The level shift 131 shifts the delay signal B by a predetermined time in response to the signal A to output the shift signal SB. The signal A is a clock signal delayed by a predetermined time (one clock and a half) from the delay signal B. The transfer gate PT1 is connected between the level shift 131S and the latch 132 and is turned on or off in response to the write signal wt and the inverted write signal wtb. Therefore, the shift signal SB is transmitted to or blocked from the latch 132 according to the turn-on or turn-off operation of the transfer gate PT1. The transfer gate PT2 is connected to the latch 132 and is turned on or off in response to the read signal rd and the inverted read signal rdb. Therefore, the delay signal B is transmitted or blocked to the latch 132 according to the turn-on or turn-off operation of the transfer gate PT2. The write signal wt has a high state during a write operation of the semiconductor memory device, and the read signal rd has a high state during a read operation.

Latch 132 includes inverters I1 and I2. The inverters I1 and I2 are connected in a reverse parallel structure, latch the delay signal B or the shift signal SB, and invert the same to output the latch signal LA.

The pulse signal generator 133 includes inverters I3 and I4 and a delay unit 133D. The inverter I3 inverts the latch signal LA and outputs it to the delay unit 133D. The delay unit 133D receives the output signal of the inverter I3 and delays the output signal by a predetermined time and outputs it. The inverter I4 inverts the output signal of the delay unit 133D and outputs the pulse signal DL.

The buffer 134 includes inverters I5 and I6. The inverters I5 and I6 are connected in series, and buffer the pulse signal DL to output the word line reset signal reset_wl.

5 is a circuit diagram of the detection signal generator 140 of FIG. 3.

Referring to FIG. 5, the detection signal generator 140 may include a first logic combiner 141, a delay unit 142, and a second logic combiner 143.

The first logic combination unit 141 includes a NAND gate ND11 and inverters I7 and I8. The NAND gate ND11 logically combines the delay signal B and the control signal web4 to generate a combined signal cs1. Inverters I7 and I8 are connected in series to buffer the output signal cs1 to produce an output signal cs2.

The delay unit 142 outputs the delayed clock signal D by delaying the clock signal A by a predetermined time. The delay time of the delay unit 142 is longer than the delay time until the delay signal B is output as the word line reset signal reset_wl.

The second logic combination unit 143 includes a NAND gate ND12 and inverters I9 and I10. The NAND gate ND12 logically combines the output signal cs2 and the delayed clock signal D to generate the output signal cs3. Inverters I9 and I10 are connected in series to buffer the output signal cs3 to generate a detection signal det.

6 is a circuit diagram of the counter control circuit 150 of FIG. 3.

Referring to FIG. 6, the counter control circuit 150 includes an internal signal generator 151, a first initializer 152, a second initializer 153, a latch 154, and a buffer 155.

The internal signal generator 151 includes an inverter I11, a PMOS transistor P1, and an NMOS transistor N1. The inverter I11 inverts the word line reset signal reset_wl and outputs it to the gate of the PMOS transistor P1. The PMOS transistor P1 is connected between the power supply voltage Vdd and the output node QA, and is turned on or off in response to the output signal of the inverter I11 to supply the power supply voltage Vdd to the output node QA. Or block it. The NMOS transistor N1 is connected between the output node QA and the ground voltage Vss, and is turned on or off in response to the detection signal det to supply or cut off the ground voltage Vss to the node QA. . The internal signal generator 131 outputs the internal signal DS1 through the output node QA according to the turn-on or turn-off states of the PMOS transistor P1 and the NMOS transistor N1.

The first initialization unit 152 is connected between the output node QA and the power supply voltage Vdd and initializes the output node QA in response to the reset signal reset. The first initialization unit 132 may be implemented as an NMOS transistor.

The second initialization unit 153 is connected between the output node QA and the power supply voltage Vdd and initializes the output node QA in response to the power-up signal pwrup. The second initialization unit 133 may be implemented as a PMOS transistor.

Latch 154 includes inverters I12 and I13. The inverters I12 and I13 are connected in parallel in the reverse direction to the output node QA. The inverters I12 and I13 latch and internally invert the internal signal DS1 and output the latch signal DS2.

The buffer 155 includes inverters I14 and I15. The inverters I14 and I15 are connected in series to buffer the latch signal DS2 and output the buffered signal as the control signal cinx0.

Referring to FIGS. 3 to 6, the operation of the word line control circuit in the continuous burst mode of the pseudo SRAM will be described below.

In the continuous burst mode operation of the pseudo SRAM, an externally accepted address is used to enable the corresponding word line. After that, the columns are internally enabled in order to perform read and write operations on the corresponding memory cells.

When all of the column address signals cay0 to cay6 are applied at the high level, the address detector 110 outputs the high level address detection signal add. The address detection signal add is output as a delay signal B delayed by the cascade latency time by the cascade latency delay unit 120.

In the write operation, the level shift unit 131 of the word line reset signal generator 130 shifts the delay signal B in response to the clock signal A and outputs a high shift signal SB. In more detail, the delay signal B is latched when the clock signal A is high, and the delay signal B is passed when the clock signal A is low. At this time, the clock signal A is a signal generated based on the delay signal B and is a clock signal shifted by one clock and a half of the delay signal B. In the write operation, the transfer gate PT1 is turned on in response to the write signal wt having the high state and the inverted write signal wtb having the low state. Therefore, the shift signal SB in the high state is transmitted to the latch 132. That is, the first path ① is selected and the delay signal B is output to the latch 132. Therefore, the delay signal B may be shifted for a predetermined time during the write operation and output to the latch 132 to compensate for the time required during the write operation.

The latch 132 latches and inverts the shift signal SB and outputs the latch signal LA.

The pulse signal generator 133 receives the latch signal LA having a low level and delays it for a predetermined time to output the pulse signal SB3.

In a read operation, the transfer gate PT2 is turned on in response to a read signal rd having a high state and an inverted read signal rdb having a low state during a read operation. Therefore, the high delay signal B is transmitted to the latch 132. That is, the second path ② is selected and the delay signal B is output to the latch 132. Since the operation is similar to the write operation, it will be omitted. Since the data is only read from the cell during the read operation, the time required for the write operation is not required. Therefore, the delay signal B is output to the latch 132 using the second pass ②.

Therefore, the delayed word line reset signal reset_wl may be output in consideration of the write and read operation times of the repair memory cell during the read operation or the write operation.

The detection signal generator 140 generates an output signal cs2 by logically combining the delay signal B and the control signal web4, and delays the clock signal A by a predetermined time to generate the delayed clock signal D. ) And the output signal cs2 are combined to generate a high level detection signal det.

The first initialization unit 152 of the counter control circuit 130 initializes the output node QA to the high level in response to the high level reset signal reset. Thereafter, the internal signal generator 151 outputs the low level internal signal DS1 through the output node QA in response to the low level word line reset signal reset_wl and the high level detection signal det. . The latch 134 latches and inverts the low level internal signal DS1 and outputs the latch signal DS2. The buffer 135 buffers the latch signal DS2 and outputs the high level control signal cnx0.

The address counter 160 enables the next word line in response to the high level control signal cnx0.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, when the word line is changed during continuous burst mode operation, the word line control circuit delays the control signal for controlling the word line counter in consideration of the time required for the read and write operation on the repair cell. By generating, even if the last cell of the word line is a repair cell, a read or write operation can be performed on the cell.

Claims (8)

An address detector for generating an address detection signal in response to the column address signal; A cas latency delay unit for delaying the address detection signal by a cas latency and outputting a delay signal; A word line reset signal generator configured to generate a word line reset signal having a different delay time in a write operation and a read operation in response to the delay signal and a write signal or a read signal; A detection signal generator for generating a detection signal in response to the delay signal and the control signal; A counter control circuit outputting a counter control signal in response to the word line reset signal and the detection signal; And And a word line counter for outputting a low address signal in response to the counter control signal. The method of claim 1, wherein the word line reset signal generator A path selector configured to generate a first pass signal and a second pass signal in response to the delay signal in response to the read signal or the write signal; A latch for latching the first pass signal and the second pass signal and inverting the same to output a latch signal; A pulse signal generator which receives the latch signal and delays a predetermined time and then outputs a pulse signal; And A buffer for buffering the pulse signal and outputting the word line reset signal; And the first pass signal and the second pass signal have different delay times. The method of claim 2, wherein the path selector A level shifter configured to shift the delayed signal in response to the delayed signal and a delayed clock that delays the delayed signal for a predetermined time; A first transfer gate configured to output the first pass signal to the latch in response to the read signal and an inverted signal of the read signal; And And a second transfer gate configured to output the delay signal as the second pass signal to the latch in response to the write signal and the inverted signal of the write signal. The method of claim 1, wherein the detection signal generation unit A combined signal generation unit configured to logically combine the delay signal and the control signal to generate a combined signal; A delay unit generating a delay signal by delaying the second clock signal for a predetermined time; And And a detection signal generator for generating a detection signal by logically combining the combination signal and the delay signal. The method of claim 4, wherein The combined signal generation unit may include a NAND gate configured to logically combine the first clock signal and the control signal; And And a buffer for buffering an output signal of the NAND gate to generate the combined signal. The method of claim 4, wherein the detection signal generator A NAND gate for logically combining the combined signal and the delay signal; And And a buffer for buffering the output of the NAND gate and outputting the detected signal as the detection signal. The method of claim 1, wherein the counter control circuit An internal signal generator configured to output an internal signal through an output node in response to the wordline reset signal and the detection signal; A first initialization unit configured to initialize the output node to a power supply voltage level in response to a reset signal; A second initialization unit for initializing the output node to a power supply voltage level in response to a power-up signal; A latch for receiving the internal signal, latching the inverted signal, and inverting the internal signal to output a latch signal; And And a buffer for buffering the latch signal to output the control signal. 8. The apparatus of claim 7, wherein the internal signal generator An inverter inverting the word line reset signal; A first transistor connected between a power supply voltage and an output node, the first transistor coupling and precharging the output node and the power supply voltage in response to an output signal of the inverter; And And a second transistor coupled between a ground voltage and the output node, the second transistor coupling and discharging the output node and the ground voltage in response to the detection signal.

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