KR20070082332A - Electron emission device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to an electron emitting device having improved structure of an insulating layer to reduce parasitic capacitance occurring at overlapping portions of electrodes and a method of manufacturing the same. The electron emission device according to the present invention is formed along a direction intersecting the cathode on the cathode electrodes with the substrate, the cathode electrodes formed on the substrate, the electron emission portions formed on the cathode electrodes and the insulating layer interposed therebetween. And the insulating layers and the gate electrodes form respective openings for electron beam passage. The opening of the insulating layer is a first opening positioned corresponding to each electron emitting portion at an upper portion of the insulating layer facing the gate electrodes, and a second exposing at least two electron emitting portions simultaneously at the lower portion of the insulating layer facing the cathode electrodes. It consists of an opening.

Description

ELECTRON EMISSION DEVICE AND METHOD FOR MANUFACTURING THE SAME

1 is a partially exploded perspective view of an electron emission display device to which an electron emission device according to an exemplary embodiment of the present invention is applied.

2 is a partial cross-sectional view of an electron emission display device to which an electron emission device according to an exemplary embodiment of the present invention is applied.

3A to 3D are schematic diagrams at each manufacturing step for explaining a method of manufacturing an electron emitting device according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron emitting device, and more particularly, to an electron emitting device having an improved structure of an insulating layer to reduce parasitic capacitance occurring at overlapping portions of electrodes and a method of manufacturing the same.

In general, electron emission elements may be classified into a method using a hot cathode and a cold cathode according to the type of electron source.

Here, the electron-emitting device using the cold cathode is a field emitter array (FEA) type, a surface conduction emission type (SCE) type, a metal-insulation layer-metal Metal (MIM) type and Metal-Insulator-Semiconductor (MIS) type are known.

The field emission array (FEA) type electron emission device includes an electron emission portion and a driving electrode for controlling electron emission of the electron emission portion, and includes one cathode electrode and one gate electrode. The use of low or high aspect ratio materials, such as carbon nanotubes and carbon-based materials such as graphite and diamond-like carbon, takes advantage of the principle that electrons are easily released by an electric field in vacuum.

The electron emission elements are arranged in an array on one substrate to form an electron emission device, and the electron emission device is combined with another substrate provided with a light emitting unit composed of a fluorescent layer and an anode electrode, and the electron emission display device. (electron emission display device) is configured.

Known field emission array (FEA) type electron emission devices have cathode electrodes, insulating layers and gate electrodes sequentially formed on a substrate, and openings are formed in the gate electrodes and insulating layers to expose a portion of the surface of the cathode electrode, The electron emission part is disposed on the cathode electrodes inside the opening.

At this time, the insulating layer has a dielectric constant of about 12, and due to this dielectric property, there is a parasitic capacitor having a relatively high capacitance C at the portion where the cathode electrodes and the gate electrodes overlap.

Therefore, when the scan driving voltage is applied to one of the cathode electrodes and the gate electrodes and the data driving voltage is applied to the other electrodes to control the electron emission amount per unit pixel, the driving signal is caused by the parasitic capacitor described above. Signal distortion occurs, such as a delay.

In order to reduce the parasitic capacitance, the insulating layer should be formed of a material having a low dielectric constant, or should be disposed so that the two electrodes face each other with a wider vacuum region by reducing the area occupied by the insulating layer at the intersection of the cathode electrode and the gate electrode. However, in the first case, the material cost is expected to increase, and in the second case, it is difficult to secure a structure to support the gate electrode.

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to improve the display quality by improving parasitic capacitance by improving the structure of the insulating layer, thereby suppressing signal delay, and fabricating the same. To provide a method.

In order to achieve the above object, the present invention,

A substrate, cathode electrodes formed on the substrate, electron emission parts formed on the cathode electrodes, and gate electrodes formed along the direction crossing the cathode electrodes on the cathode electrodes with the insulating layer interposed therebetween; The layer and the gate electrodes form their respective openings for electron beam passage, the openings of the insulating layer being the first openings corresponding to the respective electron emitting portions at the upper portions of the insulating layer facing the gate electrodes, and the insulation toward the cathode electrodes. Provided is an electron emitting device consisting of a second opening that simultaneously exposes at least two electron emitting portions in the lower portion of the layer.

Each of the second openings may be formed in each crossing region of the cathode electrodes and the gate electrodes, and the gate electrodes may form an opening having the same size as the first opening.

The insulating layer may have a low etching rate as it moves away from the cathode electrodes. For this purpose, the insulating layer may be formed to have a higher density as it moves away from the cathode electrodes.

In addition, the electron emission device may further include a focusing electrode positioned above the gate electrodes and insulated from the gate electrodes.

In addition, the present invention, in order to achieve the above object,

Forming cathode electrodes on the substrate, and gradually stacking an insulating material over the substrate with a large density while covering the cathode electrodes to form an insulating layer, and forming gate electrodes on the insulating layer in a direction crossing the cathode electrodes, Openings are formed in the gate electrodes, and the portions of the insulating layer exposed by the openings are etched to form first openings corresponding to the openings in the upper portions of the insulating layers facing the gate electrodes, and then the lower portions of the insulating layers toward the cathode electrodes. A method of manufacturing an electron emitting device is provided wherein a second opening is formed in communication with at least two first openings, and an electron emitting portion is formed on the cathode electrodes for each first opening.

When the second opening is formed, one second electrode may be formed for each crossing area of the cathode electrodes and the gate electrodes.

Further, before forming the openings in the gate electrodes, the method may further include forming an additional insulating layer and a focusing electrode on the gate electrodes, and forming respective openings by partially etching the focusing electrode and the additional insulating layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 and 2 are partially exploded perspective and partial cross-sectional views of an electron emission display device to which an electron emission device according to an exemplary embodiment of the present invention is applied.

Referring to the drawings, the electron emission display device includes a first substrate 2 and a second substrate 4 which are arranged in parallel to each other at predetermined intervals. Sealing members (not shown) are disposed at the edges of the first substrate 2 and the second substrate 4 to bond the two substrates, and the internal space is evacuated with a vacuum of approximately 10 ⁻⁶ torr to allow the first substrate 2 to be bonded. ), The second substrate 4 and the sealing member constitute a vacuum container.

On the opposite surface of the first substrate 2 to the second substrate 4, electron emission elements are arranged in an array to form the electron emission device 100 together with the first substrate 2, and the electron emission device ( 100 is combined with the second substrate 4 and the light emitting unit 110 provided on the second substrate 4 to form an electron emission display device.

First, cathode electrodes 6, which are first electrodes, are formed on the first substrate 2 in a stripe pattern along one direction of the first substrate 2, and cover the cathode electrodes 6. 2) The first insulating layer 8 is formed in its entirety. Gate electrodes 10, which are second electrodes, are formed on the first insulating layer 8 in a stripe pattern along a direction orthogonal to the cathode electrode 6.

An intersection area between the cathode electrodes 6 and the gate electrodes 10 constitutes one sub-pixel, and electron emission portions 12 are formed in each unit pixel over the cathode electrodes 6. do. In addition, openings 81 and 101 are formed in the first insulating layer 8 and the gate electrodes 10 to expose the electron emission part 12 on the first substrate 2. In this case, the gate electrode opening 101 is positioned corresponding to each electron emission part 12.

In the present embodiment, the opening 81 of the first insulating layer 8 includes a first opening 81a and a second opening 81b formed in different sizes along the thickness direction of the first insulating layer 8. . The first opening 81a is formed to correspond to each electron emission part 12 on the upper side of the first insulating layer 8 facing the gate electrode 10, and the second opening 81b opens the cathode electrode 6. It is formed encompassing at least two electron emitting portions 12 under the first insulating layer 8 facing away.

More specifically, the first opening 81a may be individually formed for each of the electron emission units 12 corresponding to the electron emission units 12, and may be formed to allow the gate electrode 10 to form an opening having an intended shape. The upper portion of the first insulating layer 8 having the first openings 81a supports the gate electrode 10.

The second opening 81b is formed to simultaneously expose at least two electron emitters 12. For example, one second opening 81b is formed for each unit pixel to communicate all the first openings 81a positioned in one unit pixel with each other. Let's do it. At this time, the second opening 81b maintains the vacuum between the cathode electrode 6 and the gate electrode 10 at the formation portion thereof.

In the structure of the first insulating layer 8, the cathode 6 and the gate electrode 10 may be formed of the first electrode while the gate electrode 10 induces an electric field required for electron emission on the electron emission part 12, as in the related art. The parasitic capacitance is reduced by effectively reducing the size of the overlapping region with the insulating layer 8 interposed therebetween. As a result, there is an effect of suppressing signal distortion due to parasitic capacitance when the electron emission device is driven.

The electron emission unit 12 may be formed of materials emitting electrons when a electric field is applied in a vacuum, such as a carbon-based material or a nanometer (nm) size material. The electron emission unit 12 may include, for example, carbon nanotubes (CNT), graphite, graphite nanofibers, diamonds, diamond-like carbons (DLC), fullerenes (C ₆₀ ), silicon nanowires, and combinations thereof. have. On the other hand, the electron emission unit may be formed of a tip structure having a pointed tip mainly made of molybdenum (Mo) or silicon (Si).

In the drawing, the circular electron emitters 12 are arranged in a line along the longitudinal direction of the cathode electrode 6, but the shape of the electron emitters 12, the number and arrangement per pixel area, etc. are illustrated. It is not limited to the example and can be variously modified.

The focusing electrode 14, which is a third electrode, is formed on the gate electrodes 10 and the first insulating layer 8. A second insulating layer 16 is positioned below the focusing electrode 14 to insulate the gate electrodes 10 and the focusing electrode 14, and passes the electron beam through the focusing electrode 14 and the second insulating layer 16. Openings 141 and 161 are provided. The openings 141 and 161 may be formed one for each electron emission part 12 or one for each unit pixel, and the second case is illustrated in the drawing.

Next, on one surface of the second substrate 4 opposite to the first substrate 2, the fluorescent layer 18, for example, the red, green, and blue fluorescent layers 18R, 18G, and 18B may be randomly selected from each other. It is formed at intervals, and a black layer 20 for improving contrast of the screen is formed between each fluorescent layer 18. The fluorescent layer 18 is disposed so that the fluorescent layers 18R, 18G, and 18B of one color correspond to the unit pixels set on the first substrate 2.

An anode electrode 22 made of a metal film such as aluminum (Al) is formed on the fluorescent layer 18 and the black layer 20. The anode 22 receives the high voltage necessary for accelerating the electron beam from the outside to maintain the fluorescent layer 18 in a high potential state, and visible light emitted toward the first substrate 2 of the visible light emitted from the fluorescent layer 18. Is reflected to the second substrate 4 side to increase the brightness of the screen.

The anode electrode may be formed of a transparent conductive film such as ITO. In this case, the anode electrode is disposed on one surface of the fluorescent layer 18 and the black layer 20 facing the second substrate 4. Moreover, the structure which forms simultaneously the above-mentioned transparent conductive film and a metal film as an anode electrode is also possible.

In addition, spacers 24 are disposed between the first substrate 2 and the second substrate 4 to support the compressive force applied to the vacuum container and to keep the distance between the two substrates constant. The spacers 24 are positioned corresponding to the black layer 20 so as not to invade the fluorescent layer 18.

The electron emission display device having the above-described configuration is driven by supplying a predetermined voltage to the cathode electrodes 6, the gate electrodes 10, the focusing electrode 14, and the anode electrode 22 from the outside.

For example, any one of the cathode electrodes 6 and the gate electrodes 10 receives a scan driving voltage to serve as scan electrodes, and the other electrodes receive a data driving voltage to serve as data electrodes. In addition, the focusing electrode 14 receives a voltage required for electron beam focusing, for example, 0 V or a negative DC voltage of several to several tens of volts, and the anode electrode 22 requires a voltage for accelerating the electron beam, for example, several hundred to several thousand volts. DC voltage of is applied.

Then, an electric field is formed around the electron emission unit 12 in the unit pixels in which the voltage difference between the cathode electrode 6 and the gate electrode 10 is greater than or equal to the threshold value, thereby emitting electrons therefrom. The emitted electrons are focused to the center of the electron beam bundle while passing through the opening 141 of the focusing electrode 14, and are attracted to the fluorescent layer 18 of the corresponding unit pixel by being attracted by the high voltage applied to the anode electrode 22. It emits light.

In the driving process described above, the size of the region in which the cathode electrodes 6 and the gate electrodes 10 overlap each other with the first insulating layer 8 interposed by the shape of the first insulating layer opening 81 described above. Decreases to minimize parasitic capacitance between the two electrodes. As a result, signal distortion due to parasitic capacitance can be reduced to perform more accurate display.

Next, a method of manufacturing an electron emission device according to an embodiment of the present invention will be described with reference to FIGS. 3A to 3D.

First, as shown in FIG. 3A, a conductive film is formed on the substrate 26 and patterned to form stripe-shaped cathode electrodes 6, and an insulating material is formed on the entire substrate 26 over the cathode electrodes 6. The first insulating layer 8 is formed by vapor deposition or screen printing.

In the present embodiment, when the first insulating layer 8 is formed, the first insulating layer 8 toward the cathode electrode 6 is gradually deposited or screen printed by densely depositing or screen-printing the insulating material away from the cathode electrode 6. The lower portion of the c) is low in density, and the upper portion of the first insulating layer 8 is high in density. Such a difference in density of the first insulating layer 8 brings about a difference in etching rate during the etching process of the first insulating layer 8.

Then, a conductive film is formed on the first insulating layer 8 and patterned to form gate electrodes 10 having a stripe shape orthogonal to the cathode electrode 6. At this time, an intersection area between the cathode electrode 6 and the gate electrode 10 forms a unit pixel.

Subsequently, an insulating material is deposited or screen printed on the entire substrate 26 over the gate electrodes 10 to form a second insulating layer 16, and a conductive material is coated on the second insulating layer 16 to focus the electrode 14. ). In addition, the focusing electrode 14 and the second insulating layer 16 are partially etched to form respective openings 141 and 161 to expose a part of the surface of the gate electrode 10. The openings 141 and 161 of the focusing electrode 14 and the second insulating layer 16 may be formed for each unit pixel.

In this case, since the second insulating layer 16 and the focusing electrode 14 are optional additions, only the cathode electrode 6, the first insulating layer 8, and the gate electrode 10 may be formed on the substrate 26. Do.

Next, as shown in FIG. 3B, the mask layer 28 is formed over the structure provided on the substrate 26 and patterned to form the opening 281. The gate electrode opening 101 is removed by etching the portion of the gate electrode 10 exposed through the mask layer opening 281.

Next, referring to FIG. 3C, the portion of the first insulating layer 8 exposed through the gate electrode opening 101 is etched to expose a portion of the surface of the cathode electrode 6 on the first insulating layer 8. Form 81. The etching process is performed by wet etching using an etchant, and etching is started from the top surface of the first insulating layer 8 exposed through the opening 281 of the mask layer, and the etching is performed toward the cathode electrode 6.

First, the upper portion of the first insulating layer 8 facing the gate electrode 10 has a relatively low etching rate because of the high density of the insulating material. Therefore, the first opening 81a having the same size as the gate electrode opening 101 is formed in the upper portion of the first insulating layer 8.

The lower portion of the first insulating layer 8 facing the cathode electrode 6 has a relatively high etching rate because of the low density of the insulating material. Accordingly, the lower portion of the first insulating layer 8 is etched faster than the upper portion of the first insulating layer 8, and eventually, adjacent etching portions that have been separately progressed through the respective mask layer openings 281 overlap each other. The second opening 81b is formed to communicate at least two first openings 81a.

One second opening 81b may be formed for each unit pixel, and FIG. 3C illustrates a configuration in which the first openings 81a formed in the unit pixel communicate with each other through one second opening 81b. .

Finally, the mask layer 28 is removed, and the electron emitter 12 is placed on the cathode electrode 6 through known screen printing, exposure, development, and baking processes using a paste including an electron emitting material and a photosensitive material. By forming, the electron emission device 100 shown in FIG. 3D is completed.

When the openings 81 are formed in the first insulating layer 8 by using the difference in etching rates as described above, the first openings 81a may be formed to have a smaller size than the conventional openings of the first insulating layer. Therefore, the electron emission device of the present embodiment increases the degree of integration of the electron emission portions 12 per unit pixel, and is advantageous in high resolution manufacturing. The electron emission portions 12 and the gate electrode 10 may be positioned close to each other. The emission efficiency is increased while reducing the driving voltage.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. Naturally, it belongs to the range of.

As described above, the electron emission device according to the present invention can suppress the signal distortion by lowering the parasitic capacitance generated at the overlapping portion of the cathode electrode and the gate electrode by the above-described first insulating layer opening shape. In addition, the electron emission device according to the present invention is advantageous in manufacturing high resolution by increasing the degree of integration of the electron emission units per unit pixel, thereby increasing the emission efficiency of the electron emission units, and enabling low voltage driving.

Claims (9)

A substrate; Cathode electrodes formed on the substrate; Electron emission parts formed on the cathode electrodes; And A gate electrode formed along the direction intersecting the cathode electrode on the cathode electrodes with an insulating layer interposed therebetween, The insulating layer and the gate electrodes form respective openings for electron beam passage, The opening of the insulating layer may include a first opening positioned at an upper portion of the insulating layer facing the gate electrodes and corresponding to each of the electron emitting portions, and at least two electron emitting portions at a lower portion of the insulating layer facing the cathode electrodes. An electron emission device comprising a second opening that exposes. The method of claim 1, And the second opening is formed one for each intersection of the cathode and gate electrodes. The method of claim 1, And the gate electrodes form an opening of the same size as the first opening. The method of claim 1, And an etching rate lower as the insulating layer moves away from the cathode electrodes. The method of claim 4, wherein And the insulating layer is formed at a greater density as it moves away from the cathode electrode. The method of claim 1, And a focusing electrode positioned above and insulated from the gate electrodes. Forming cathode electrodes on the substrate; An insulating layer is formed by gradually stacking an insulating material over the entire substrate while covering the cathode electrodes with a large density; Forming gate electrodes on the insulating layer along a direction crossing the cathode electrodes; Forming openings in the gate electrodes; Etching the portion of the insulating layer exposed by the opening to form first openings corresponding to the opening in an upper portion of the insulating layer facing the gate electrodes, and then forming at least two lower portions of the insulating layer facing the cathode electrodes. Forming a second opening in communication with the first opening; And forming electron emission portions on the cathode electrodes in each of the first openings. The method of claim 7, wherein When forming the second opening, forming one electron for each intersection region of the cathode and gate electrodes. The method of claim 7, wherein Before forming openings in the gate electrodes, An additional insulating layer and a focusing electrode are formed on the gate electrodes, And partially etching the focusing electrode and the additional insulating layer to form respective openings.

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