KR20070071006A - CMOS image sensor - Google Patents

Abstract

The present invention is to provide an image sensor that can solve the problem of causing the column fixed pattern noise caused by the variation of the drive current of the transistor constituting the unit pixel, the present invention provides a photodiode and the photodiode In a CMOS image sensor including a plurality of transistors for switching the accumulated charge to transfer to one column line, in order to increase the driving current, the channel length of the gate electrode of at least one of the plurality of transistors is increased by region To provide a CMOS image sensor having a different length of the gate electrode according to a portion to be dualized.

Description

CMOS image sensor {CMOS IMAGE SENSOR}

1 is a configuration diagram showing the configuration of a general CMOS image sensor.

Fig. 2 is a circuit diagram showing the configuration of unit pixels having a 3-T structure of a general CMOS image sensor.

3 is a circuit diagram illustrating a pixel array in which a plurality of unit pixels illustrated in FIG. 2 is formed.

4 is a circuit diagram showing the configuration of unit pixels having a 4-T structure of a general CMOS image sensor.

FIG. 5 is a circuit diagram illustrating a pixel array including a plurality of unit pixels illustrated in FIG. 4.

6A and 6B are a circuit diagram and a plan view showing a drive transistor and a select transistor of a unit pixel.

FIG. 7 is a conceptual diagram illustrating column fixed pattern noise generated in the CMOS image sensor according to the related art. FIG.

8 is a plan view showing unit pixels of a CMOS image sensor according to Embodiment 1 of the present invention;

FIG. 9 is an enlarged plan view of a gate electrode of the select transistor Sx shown in FIG. 8.

10A to 10D are plan views illustrating still another examples of unit pixels of a CMOS image sensor according to Embodiment 1 of the present invention;

FIG. 11 is a plan view showing unit pixels of a CMOS image sensor according to Embodiment 2 of the present invention; FIG.

<Explanation of symbols for the main parts of the drawings>

10: pixel array

20: to decoder

30: column decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a complementary metal oxide semiconductor (SMOS) image sensor.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

The camera module basically includes an image sensor. In general, an image sensor refers to a device that converts an optical image into an electrical signal. As such an image sensor, a charge coupled device (hereinafter referred to as a CCD) and a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor are widely used.

CCD has a complicated driving method, high power consumption, complicated process due to the large number of mask processes in the manufacturing process, and it is difficult to realize a signal processing circuit in a chip, making it difficult to make one chip. There are disadvantages. In contrast, CMOS image sensors are receiving more attention recently because of the monolithic integration of control, drive, and signal processing circuitry on a single chip. In addition, CMOS image sensors offer potentially lower cost than conventional CCDs due to low voltage operation and low power consumption, compatibility with peripherals, and the availability of standard CMOS fabrication processes.

However, analog signals generated by light receiving elements, such as photo diodes, in CMOS image sensors have various parasitic effects caused by parasitic capacitance, resistance, dark current leakage, or mismatch of semiconductor device characteristics. This parasitic effect is indispensable in the semiconductor device, which leads to a decrease in the signal to noise ratio of the image data. Therefore, noise is an important factor limiting the performance of the CMOS image sensor.

Noise in the CMOS image sensor is caused by kT / C noise related to the sampling of the image data, 1 / f noise associated with the circuit used to amplify the image signal, and fixed by the mismatch of the signal processing circuit of the sensor. Patterned Pattern Noise (hereinafter referred to as FPN). Dual FPNs are not very good visually because they appear as vertical lines or strips in the image and are easily found in the human eye.

1 is a diagram illustrating a CMOS image sensor having a unit pixel having a square shape.

As shown in FIG. 1, when a row address is designated around the pixel array 10, a row decoder 20 is disposed in one direction of the pixel array 10, and is positioned at a right angle thereof. The data output of the pixel is connected to, and a column decoder 30 for designating a column address of the pixels is disposed.

A process of reading data from a CMOS image sensor having such a configuration will be described below.

First, the first column is selected by the row decoder 20, and then data of each pixel of the first column selected by the column decoder 30 is read, and then the data of each pixel is amplified. Next, the second column is selected by the row decoder 20, and then data for each pixel of the second column selected by the column decoder 30 is read and then amplified. In this manner, data of all pixels is read.

There are many types of unit pixels used in CMOS image sensor, but among them, the typical commercially available pixel type is 3-T (3-transistor) composed of three basic transistors and one photodiode. There is a 4-T (4-transistor) structure pixel composed of a pixel of the structure, four basic transistors, and a photodiode.

FIG. 2 is a circuit diagram illustrating a general 3-T structure among the CMOS image sensor unit pixels.

Referring to FIG. 2, a 3-T pixel includes one photodiode PD for converting and storing photon into electrons and three NMOS transistors. The three NMOS transistors are configured as a source follower by operating the reset transistor Rx for resetting one end of the photodiode PD to the power supply voltage VDD and the charge accumulated in the photodiode PD. The drive transistor Dx serves as a buffer amplifier, and the select transistor Sx allows addressing by switching.

4 is a circuit diagram illustrating a general 4-T structure among the CMOS image sensor unit pixels.

Referring to FIG. 4, a 4-T pixel includes one photodiode PD and four NMOS transistors. The four NMOS transistors have a transfer transistor Tx for transporting the photo-generated charges concentrated in the photodiode PD to the floating diffusion region FD, and the floating diffusion region FD to a desired value. A reset transistor Rx for setting the potential and discharging the charge to reset the floating diffusion region FD, and a drive transistor acting as a buffer amplifier in a source follower configuration by operating according to the accumulated charge in the floating diffusion region FD. (Dx), it consists of a select transistor (Sx) which enables addressing by switching.

As described above, the greatest difference in the circuit configuration between the pixels of the 3-T structure and the pixels of the 4-T structure is the presence or absence of the transfer transistor Tx and the floating diffusion region. The pixel of the 3-T structure first detects the signal level and then turns on the reset transistor Rx to detect the reset level. On the other hand, the pixel of the 4-T structure turns on the reset transistor Rx to detect the reset level first, and then turns on the transfer transistor Tx to detect the signal level.

3 is a circuit diagram illustrating a pixel array in which pixels of the 3-T structure shown in FIG. 2 share one column line. As illustrated in FIG. 3, each unit pixel UP1 to UPn is connected to one column line in common and is connected to one load transistor Load.

FIG. 5 is a circuit diagram illustrating a pixel array in which pixels of the 4-T structure illustrated in FIG. 4 share one column line. As illustrated in FIG. 5, each unit pixel UP1 to UPn is connected to one column line in common and is connected to one load transistor Load.

As shown in FIGS. 3 and 5, the pixels of the 3-T structure and the 4-T structure are configured such that a plurality of pixels share one column line and are connected to one load transistor through the column line. As shown in FIG. 1, a signal is read and output for each column line.

As described above, since the pixel data output from the plurality of pixels is read out through one column line, column fixed pattern noise (FPN) is generated by a difference in offset generated for each pixel in the process. do. One of the causes of the fixed pattern noise is a change in channel length and a change in saturation current due to a change in final inspection critical dimension (FICD) of a gate electrode of a neighboring transistor.

Currently, the characteristics of the transistor to which the CMOS image sensor process of 0.18 μm is shown in Table 1 below.

Transistor type W / L (㎛) Idsat Idsat '(㎂ / ㎛)                         Load tr 2/2 256 128 2/4 139 70 4/2 506 124 Dx & Sx Tr 0.25 / 0.35 150 600

As shown in FIGS. 6A and 6B and Table 1, the unit pixel according to the related art is designed to have the gate electrode length L of the driver transistor Dx and the select transistor Sx equal to 0.35 占 퐉. Therefore, the driving current is approximately 150 mA in the driver transistor Dx and the select transistor Sx, and approximately 260 mA in the load transistor Load.

In general, the driving current when driving the CMOS image sensor is determined by the driving current value of the driver transistor Dx or the select transistor Sx having the minimum value. For this reason, the manufacturing process of the driver transistor Dx or the select transistor Sx must be precisely controlled.

However, there is a problem in that the length of the gate electrode FICD is changed during an etching process for defining the gate electrodes of the driver transistors Dx and the select transistor Sx. This gate variation causes the drive current to fluctuate, causing column fixed pattern noise.

The column fixed pattern noise will be described in detail with reference to FIG. 7.

As shown in FIG. 7, a minimum current for driving the pixel for each column line is affected by both the drive transistor Dx and the select transistor Sx. That is, it is determined by the variation combination of the transistors Dx and Sx. As a result, the column fixed pattern noise is influenced by two factors by the drive transistor Dx and the select transistor Sx, and thus the probability of generating the column fixed pattern noise increases.

Accordingly, the present invention has been proposed to solve the above-described problems of the prior art, and provides an image sensor capable of solving the problem of causing column fixed pattern noise due to variations in driving currents of transistors constituting a unit pixel. The purpose is.

According to an aspect of the present invention, there is provided a CMOS diode sensor including a photodiode and a plurality of transistors for switching charges stored in the photodiode and transmitting the same to one column line. In order to increase, the CMOS image sensor having a different length of the gate electrode according to a portion is provided so that the channel length of the gate electrode of at least one of the plurality of transistors is dualized for each portion.

According to another aspect of the present invention, there is provided a photodiode, a transfer transistor for switching charges accumulated in the photodiode and transporting the charges to the floating diffusion region, and resetting the floating diffusion region to a reset voltage. A reset transistor for amplifying the reset transistor; a drive transistor for amplifying and outputting the charge accumulated in the floating diffusion region; and a select transistor for switching the signal amplified through the driver transistor to be transferred to the column line. Provided is a CMOS image sensor in which the channel length of the transistor is smaller than the channel length of the drive transistor.

According to still another aspect of the present invention, there is provided a photodiode, a reset transistor for resetting the photodiode to a reset voltage, a drive transistor for amplifying and outputting the charge accumulated in the photodiode; And a select transistor configured to switch a signal amplified through the driver transistor and transfer the signal amplified through the driver transistor to the column line, wherein the channel length of the select transistor is smaller than the channel length of the drive transistor.

The present invention prevents the driving current from being lowered by dualizing the gate length per unit width of the gate electrode of at least one of the transistors constituting the unit pixel.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals throughout the specification represent the same elements performing the same function.

Example 1

FIG. 8 is a plan view illustrating a structure of a unit pixel of a CMOS image sensor according to Embodiment 1 of the present invention, and FIG. 9 is a plan view illustrating only the select transistor Sx illustrated in FIG. 8. Here, the unit pixel having the 4-T structure shown as an example is shown.

8 and 9, the unit pixel of the CMOS image sensor according to the first exemplary embodiment of the present invention measures the length of the gate electrode of at least one of four NMOS transistors Tx, Rx, Dx, and Sx. Binary to L and L 'per width (W). Where L> L '.

The transistor current Itot of the image sensor illustrated in FIG. 9 is represented by Equation 1 below.

Itot = Idsat × W1 × α + Idsat '× W2 × (1-α)

In Equation 1, Idsat &lt; Idsat 'relation is established by short channel effect. Here, Idsat is a current flowing through the length L of the gate electrode, and Idsat 'is a current flowing through the length L' of the gate electrode.

As shown in Equation 1, in the unit pixel of the image sensor according to the first embodiment of the present invention, a high current value may be obtained by a short channel effect by a relative fraction corresponding to (1-α). Therefore, when the driving current is lowered, a current as high as (1-α) is obtained at a predetermined portion to compensate. Thereby, the column fixed pattern noise caused by the variation of the FICD of the gate electrode can be eliminated.

9 illustrates a gate electrode structure having a length unidirectionally unidirectional as an example, but this is not limited to various structures for dualizing the length of the gate electrode as an example.

Various structures for dualizing the length of the gate electrode are shown in FIG. 10.

(A) of FIG. 10 has a unidirectional diagonal structure to have the smallest length at the center portion, and (b) has a bidirectional diagonal structure (ribbon form). (c) is in the form of a dumbbell, (d) is in the form of a dumbbell, the length is reduced to form a diagonal structure having an inclination angle in θ. In addition to this structure, although not shown, it may be formed in a unidirectional or bidirectional ladder structure.

Example 2

12 is a plan view for explaining the structure of a unit pixel of the CMOS image sensor according to a second embodiment of the present invention. Here, the unit pixel having the 4-T structure shown as an example is shown.

Referring to FIG. 12, the unit pixel of the CMOS image sensor according to the second exemplary embodiment of the present invention uses a gate length L ′ of a select transistor Sx among four NMOS transistors Tx, Rx, Dx, and Sx. It is smaller than the gate length L of (Dx). That is, the channel length of the select transistor Sx is made smaller than the channel length of the drive transistor Dx.

As a result, the magnitude of the total driving current in the unit pixel is the load transistor Load, the select transistor Sx, and then the drive transistor Dx. Therefore, although the column fixed pattern noise has been determined by a combination of fluctuations in the FICDs of the drive transistor and the select transistor in the related art, in the second embodiment of the present invention, the fixed pattern noise can be improved by the single parameterization of the drive transistor.

On the other hand, the gate electrode length of the select transistor Sx is in the range of 0.30 to 0.25 μm so that Id (Dx) <Id (Sx) <Id (Load) is established, and the gate electrode length of the drive transistor Dx is 0.35 μm. do.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the gate electrode of at least one of the transistors constituting the unit pixel is dualized in gate length per unit width to prevent driving current from being lowered, thereby improving column fixed pattern noise. have.

In addition, according to the present invention, by forming the gate length of the select transistor constituting the unit pixel to be smaller than the gate length of the drive transistor, it is possible to improve the fixed pattern noise by making the generation factor of the fixed pattern noise into a single variable of the drive transistor.

Claims (10)

In a CMOS image sensor comprising a photodiode and a plurality of transistors for switching the charge accumulated in the photodiode to be transmitted to one column line, The CMOS image sensor having a different length of the gate electrode according to a portion so that the channel length of the gate electrode of at least one of the plurality of transistors is dualized for each portion to increase a driving current. The method of claim 1, And the gate electrode is connected to the photodiode and has a lowest channel length at a central portion of an active region overlapping the gate electrode. The method of claim 2, The gate electrode is a CMOS image sensor formed to be short in the diagonal shape toward the center portion. The method of claim 2, The gate electrode is a CMOS image sensor formed of any one of ribbons, dumbbells and ladders. The method according to any one of claims 1 to 4, The plurality of transistors, A transfer transistor for switching charges accumulated in the photodiode and transporting the charges to the floating diffusion region; A reset transistor for resetting the floating diffusion region to a reset voltage; A drive transistor for amplifying and outputting the charge accumulated in the floating diffusion region; And Select transistor for switching the signal amplified through the driver transistor to the column line CMOS image sensor comprising a. The method according to any one of claims 1 to 4, The plurality of transistors, A reset transistor for resetting the photodiode to a reset voltage; A drive transistor for amplifying and outputting the charge accumulated in the photodiode; And Select transistor for switching the signal amplified through the driver transistor to the column line CMOS image sensor comprising a. Photo diodes; A transfer transistor for switching charges accumulated in the photodiode and transporting the charges to the floating diffusion region; A reset transistor for resetting the floating diffusion region to a reset voltage; A drive transistor for amplifying and outputting the charge accumulated in the floating diffusion region; And Including a select transistor for switching the signal amplified through the driver transistor to deliver to the column line, And a channel length of the select transistor is smaller than a channel length of the drive transistor. Photo diodes; A reset transistor for resetting the photodiode to a reset voltage; A drive transistor for amplifying and outputting the charge accumulated in the photodiode; And Including a select transistor for switching the signal amplified through the driver transistor to deliver to the column line, And a channel length of the select transistor is smaller than a channel length of the drive transistor. The method according to claim 7 or 8, The length of the gate electrode of the select transistor is a CMOS image sensor formed of 0.25 ~ 0.30㎛. The method of claim 9, And a gate electrode having a length of 0.35 μm.

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