KR20070054927A - Semiconductor memory device and method having a single clock path - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal clock supply circuit of a memory in a synchronous peninsula. The present invention relates to a synchronous semiconductor memory device for supplying an internal clock generated from a delayed synchronization loop to a termination circuit and a data output circuit. A clock driver for transmitting the internal clock to termination circuits and a data output circuit in response; A single clock path for transferring the internal clock from the clock driver; And a distribution circuit for amplifying an internal clock delivered from the single clock path and distributing it to the termination circuits and the data output circuits.

Through the unified clock path described above, chip area and power consumption can be reduced.

Description

Semiconductor memory device and method having a single clock path {SEMICONDUCTOR MEMORY DEVICE HAVING COMMON CLOCK PATH}

1 is a block diagram illustrating clock transfer of a typical memory device;

2 is a detailed circuit diagram of FIG. 1;

3 is a block diagram illustrating a clock path in accordance with the present invention;

4 is a circuit diagram illustrating an embodiment of implementing FIG. 3.

* Explanation of symbols for main parts of drawings *

10: DLL 20, 110: Clock Driver

30, 50: clock path 40: first clock repeater

60: second clock repeater 70: data output control circuit

120, 140: Unified clock path

130: first repeater 150: second repeater

160: data output control circuit 170: control signal transmission path

 The present invention relates to a semiconductor memory device, and more particularly, to a clock supply circuit of a synchronous memory device.

In general, a synchronous DRAM used as a main memory and a graphic memory of a computer requires a high bandwidth to improve performance of a system. To meet this requirement, the bandwidth is increased by increasing the clock frequency at which the DRAM operates. On the other hand, in order for the memory to operate at a high frequency clock of 100 MHz or higher, a delay locked loop (DLL) circuit that synchronizes an external clock and an internal clock is essential.

Meanwhile, semiconductor devices have input / output pins for exchanging data with an external device, output circuits for transmitting internal data to the outside through input / output pins, and input circuits for receiving external data therein. However, in order to enable high-speed interfacing with the outside, it is necessary to minimize the reflection of the signal due to impedance mismatch at the input / output pins to which data is input / output. In general, for active impedance matching, an impedance circuit is formed near the input / output pins of the chip. Such a circuit is called an on-die termination (ODT) or an on-chip termination circuit. In addition, a data input / output circuit is provided around the input / output pin to latch external data or output internal data when data is input / output. The clock for driving the input / output circuit is supplied from the delayed synchronization loop (DLL) circuit described above.

However, the clock driving the ODT circuit and the output circuit is a clock whose output delay of data generated from the delay synchronization loop DLL is compensated. In synchronization with this clock, control of the data output and adjustment of the termination impedance are made. Therefore, the output circuit and the ODT circuit are located near the output pin of the data, and the clock signal must be received from the delay synchronization loop (DLL) circuit described above in order to drive the clock with the internal delay compensated. In view of the layout of the memory device, a problem arises in that the spatial distances of all the input / output pins from the delayed synchronization loop (DLL) circuit are not uniform. Therefore, a separate clock driving driver, a clock path, and a clock supply circuit such as a repeater are required to transfer the aforementioned main clock signal to an input / output pin located relatively far from the delay synchronization loop (DLL) circuit. In particular, in the case of the synchronous semiconductor memory in which the cell array occupies an absolute chip area, the position of the delayed synchronization loop (DLL) circuit must be located at the outer edge of the chip, and thus the clock supply circuit described above is essential.

FIG. 1 is a block diagram briefly explaining a transfer path of an ODT control clock and an internal clock DLL_CLK as a data output control clock in a general memory device. Referring to FIG. 1, a memory device has an interior to an ODT circuit (not shown) and a data input / output circuit (not shown) that are distributed at a relatively long distance from a left side of a chip on which a delay synchronization loop (DLL) 10 is located. The driving clock DLL_CLK is transferred. Hereinafter, the transfer of the internal driving clock DLL_CLK will be described in detail with reference to the drawings.

The delay synchronization loop 10 is a clock generation circuit for compensating the output delay (tSAC) of data according to an operation inside the chip with a clock (or system clock) supplied from the outside of the chip. Referring to the schematic operation of the delayed synchronization loop 10, the delayed synchronization loop 10 generates an internal clock in response to the system clock, which writes and reads data into the selected memory device. It is a reference signal for controlling all the operations. In order to generate such an internal clock, a synchronous semiconductor memory device typically employs a clock buffer (not shown) that receives a system clock supplied from the outside. This clock buffer and internal delays prevent the system clock from having the same phase as the internal clock. Therefore, when the system clock is applied to the memory chip, the internal operation of the chip is always delayed by a predetermined phase and then operated, and the delayed data is output to the input clock. The delay lock loop 10 provides an internal clock DLL_CLK which minimizes skew between the system clock and the internal clock.

The clock driver 20 supplies the internal clock DLL_CLK provided from the delay synchronization loop 10 described above to each component of the memory device in response to the control signals TERMON, CLKDQP2D, and STANDBY. In particular, the above-described internal clock must be supplied to the ODT control circuit and the data input / output circuits for controlling the input / output pins of the data located in the outer portion of the memory. Therefore, the clock driver 20 should be a driver of a size that can supply sufficient current. The clock driver 20 supplies an internal clock DLL_CLK to a corresponding path in response to the data output control signal CLKDQP2D and the ODT control signal TERMON transmitted from the command decoder (not shown) and the MRS. When the data output control signal CLKDQP2D is input, the clock driver 20 outputs the internal clock DLL_CLK to the path CDQ_F to supply a clock for controlling the data output. When the ODT control signal TERMON is input and the standby signal STANDBY is in the low level state, the clock driver 20 transmits the aforementioned internal clock DLL_CLK to the path CODT_F for supplying the ODT control clock. do. On the other hand, when the standby signal STANDBY is at the HIGH level, the internal clock DLL_CLK is controlled not to be output to the path CODT_F.

The first clock repeater 40 compensates for the level drop of the internal clock DLL_CLK transmitted by the path CODT_F for supplying the ODT control clock and the path CDQ_F for supplying the data output control clock, respectively. The first clock repeater 40 is inserted in the middle of the clock path to supply a sufficient level of clock signal to the above-described ODT control circuits and data output control circuits that are distributed at a relatively long distance from the clock driver 20. do.

The second clock repeater 60 recovers the level of the internal clock DLL_CLK transferred from the first clock repeater 40 described above via the path CODT_F and the path CDQ_F2, respectively, so that the clock is used. To distribute. Of course, the divided clocks will again be delivered via repeaters (not shown) for supplying an internal clock DLL_CLK to each control circuit. The second clock repeater 40 transmits the internal clock DLL_CLK to the path CDOT_FL and the path CDOT_FU, respectively, according to the position in the chip of the ODT control circuits (not shown). The internal clock DLL_CLK delivered to the path CDOT_FL may be supplied to an ODT gate (not shown) and a DQ multiplex (not shown), respectively, to be used for the ODT control operation. In addition, the internal clock transmitted by the path CODT_FU will also be supplied to the ODT control circuit near the DQ pin distributed at the corresponding position. In addition, the internal clock DLL_CLK supplied to the path CDQ_FL and the path CDQ_FU by the second clock repeater 60 will be used as a control clock of the data output circuits, respectively.

The data output control circuit 70 receives the internal clock DLL_CLK transmitted from the first clock repeater 40 described above to the clock path CDQ_F as a control clock. For example, the data output control circuit 70 generates an output buffer enable signal PTRST that activates the output buffer so that data sensed from the memory cell is output to the outside. When the data output control signal CLKDQP2D is enabled, the data output control circuit 50 receives the internal clock DLL_CLK through the clock path CDQ_F via the first clock repeater 40.

According to the conventional clock transfer circuit, the provision of the internal clock DLL_CLK to the ODT control circuit and the data input / output control circuit in which data input / output pins are disposed is provided through separate clock paths, separate drivers, and repeaters, respectively. It can be seen.

FIG. 2 is a circuit diagram briefly illustrating a configuration for supplying the internal clock DLL_CLK of FIG. 1 described above. Referring to FIG. 2, a transfer path from the clock driver 20 to the end position of the second clock repeater 60 in which the internal clock DLL_CLK is distributed in response to the control signals TERMON, STANDBY, and CLKDQP2D is illustrated.

The clock driver 20 transmits the internal clock DLL_CLK supplied from the delay synchronization loop 10 to the corresponding path in response to the control signals TERMON, STANDBY, and CLKDQP2D. When the standby signal STANDBY is at the 'HIGH' level, the internal clock DLL_CLK cannot be transmitted to the inverted ODT control clock path CODTB_F regardless of the level of the ODT control signal TERMON. This means that the output of NOR1 is fixed at the 'LOW' level and consequently the control signal input of NOR2, which determines whether the internal clock DLL_CLK is delivered, is always fixed at the 'HIGH' level. Because. When the data output control signal CLKDQP2D is input as 'HIGH', the input of the internal clock DLL_CLK may be output by the inverted data output signal CLKDQP2D of the NOR3. Therefore, the signals TERMON, STANDBY and the data input / output control signal CLKDQP2D, which control the clock transmitted to the ODT, are independently input to the clock driver 20, and the internal clock DLL_CLK is independently transferred to each path. Can be sent to. In FIG. 1, the output of the clock driver 20 is represented by paths CODT_F and CDQ_F. However, in a practical circuit configuration, each path 31, 32, 51, and 52 is controlled by the control signals TERMON, STANDBY, CLKDQP2D. Is blocked, the logic level 'HIGH' is maintained, so CODTB_F (31, 51) and CDQB_F (32, 52) are represented.

The first clock repeater 40 includes a repeater 41 for restoring the level of the ODT control clock each consisting of two inverters and a repeater 42 for restoring the level of the data output control clock. This is a configuration that must be included in order to amplify and retransmit the internal clock DLL_CLK transmitted through two paths CODTB_F and CDQB_F, respectively.

The second clock repeater 60 is also provided with a repeater for restoring the internal clock DLL_CLK transmitted to the paths COT_F 51 and CDQB_F 52, respectively, and distributing it to an ODT control circuit or data input / output circuit in which an input / output pin is located. . The output of the repeaters will be distributed to each repeater or control circuit in the area where the termination circuit or data input / output circuit is located.

It can be seen that the clock supply circuit described above has two separate paths for transmitting the same internal clock DLL_CLK to the ODT control circuit and the data output circuit in response to each control signal. Each separate clock driver and separate clock repeater are required to deliver the same internal clock (DLL_CLK). In addition, since the internal clock DLL_CLK transmitted is the main clock supplied to the control circuit, the above-described clock driver and the clock repeater should be composed of a large-size device that consumes a relatively large current. In addition, two long lines are required to transmit the same internal clock DLL_CLK in the same direction in the chip. This causes power losses due to large current consumption and area limitations in terms of layout of the chip design.

 The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a clock supply method and apparatus for unifying two paths through which the same clock signal is transmitted in the same direction.

 A synchronous semiconductor memory device for supplying an internal clock generated from the delayed synchronization loop of the present invention to the termination circuits and the data output circuit for achieving the above object, the internal clock in response to the termination control signal and the data output control signal. A clock driver for transmitting; A distribution circuit for distributing the internal clock to the termination circuits and the data output circuits; And a single clock path for transferring the internal clock between the clock driver and the distribution circuit.

In a preferred embodiment, the clock driver outputs the internal clock to the single clock path when at least one of the termination control signal and the data output control signal is enabled.

In a preferred embodiment, the single clock path further comprises a repeater to compensate for the level drop of the internal clock.

In a preferred embodiment, a data output control circuit is provided to control a data output buffer in response to an internal clock from the single clock path and the data output control signal.

In a preferred embodiment, the data output control circuitry receives the internal clock from the single clock path only when the data output control signal is activated.

In a preferred embodiment, the data output control signal further comprises a control signal path for transferring from the first area to the data output control circuit.

In a preferred embodiment, the control signal path has a smaller layout than the clock path and an operation characteristic of a small current.

The internal clock supply method of the synchronous semiconductor memory device of the present invention for achieving the above object is to unify the clock path from the internal clock generation source to the distribution circuit for distributing the internal clock to the termination circuit and the data input / output circuit, The internal clock transmitted through the unified clock path is distributed to the termination circuit and the data input / output circuit.

In a preferred embodiment, the internal clock generator further comprises a clock driver for transmitting the internal clock to the unitary clock path in response to a control signal.

In a preferred embodiment, the unified clock path includes a repeater that recovers and retransmits the level of the internal clock.

In a preferred embodiment, the control signal includes a first control signal for controlling the transfer of the internal clock to the termination circuit and a second control signal for controlling whether the internal clock is transferred to the data input / output circuit.

The method may further include a control signal transfer path transferring the second signal to the data input / output circuit such that the internal clock is transmitted to the data input / output circuit only when the second control signal is activated.

According to the present invention according to the above configuration and method, it is possible to reduce the chip area by unifying the clock path, it is possible to reduce the clock path and repeaters that consume a large current can reduce the power consumption.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram showing a preferred embodiment of the present invention. Here, the same reference numerals as in FIG. 1 shown above indicate the same members having the same function. Referring to FIG. 3, the internal clock DLL_CLK transfer circuit of the present invention includes a clock driver 110 that outputs the internal clock DLL_CLK to one output terminal in response to each control signal TERMON, STANDBY, CLKDQP2D. . In addition, it consists of repeaters that reproduce and retransmit signals transmitted through one path (CDQ_ODT_F).

The clock driver 110 outputs the internal clock in the unified path CDQ_ODT_F in response to the control signals TERMON, STANDBY, and CLKDQP2D. When the standby signal STANDBY is enabled, the clock driver 110 blocks the output of the internal clock DLL_CLK. On the other hand, when the standby signal STANDBY is disabled, if only one of the ODT control signal TERMON or the data output control signal CLKDQP2D is enabled, the internal clock DLL_CLK is moved to the unified clock path CDQ_ODT_F. Is output. In particular, the data output control signal CLKDQP2D is input to the clock driver 110 and transmitted to the data output control circuit 160 through the control signal path 170.

The single clock path (CDQ_ODT_F) 120, 140 is a clock path composed of one line for transferring the internal clock DLL_CLK output from the clock driver 110 to the second repeater 150, which will be described later. According to the control scheme of the clock driver 110 described above, the internal clock DLL_CLK always moves from the clock driver 110 to the second repeater 150 at a time when the standby signal STANDBY is deactivated. ) And the first repeater 130.

The first repeater 130 restores and retransmits the level of the internal clock DLL_CLK transmitted to the single clock path CDQ_ODT_F 120 described above. This is in contrast to the configuration of the repeaters for recovering and retransmitting the levels of the signals delivered to the two conventional clock paths, respectively.

The second repeater 150 distributes the internal clock DLL_CLK transmitted to the single clock path CDQ_ODT_F 140 to an ODT control circuit and a data output control circuit located near the data input / output pin. Or it may be distributed to the repeater circuits which are located at the front end of each control circuit located near the above-described input and output pins.

The data output control circuit 160 receives an internal clock DLL_CLK transmitted through the clock path CDQ_ODT_F 140 and generates a signal (eg, PTRST) for controlling the data output buffer. In particular, since the data output control circuit needs to receive the internal clock DLL_CLK only when the data output control signal CLKDQP2D is enabled, a control operation must be performed, and thus a separate control signal path provided with a separate data output control signal CLKDQP2D. It may be input through the 170. Therefore, when the ODT control signal TERMON is enabled and the data output control signal CLKDQP2D is disabled, the internal clock DLL_CLK, which is transmitted to the unified clock path CDQ_ODT_F, is not received. On the other hand, the data output control circuit 160 receives the transferred internal clock DLL_CLK regardless of whether the data output control signal CLKDQP2D is enabled and the value of the ODT control signal TERMON.

The control signal path 170 through which the data output control signal CLKDQP2D is transmitted is connected to the above-described data output control circuit 160 which is input to the clock driver 110. However, since the control signal path 170 is a path through which a control signal having a relatively small number of toggles is transmitted, rather than a line that consumes a large current such as a clock signal, no additional repeater is required and the current consumption is also low. Therefore, the width of the line does not need to be as large as the clock path described above.

The above-described transfer circuit of the internal clock DLL_CLK according to the present invention constitutes one internal clock path, and the circuit outputs the internal clock DLL_CLK only when the data output control signal CLKDQP2D is enabled. Provides a separate control line that carries the signal CLKDQP2D. This configuration unifies the clock path, which occupies a large layout area and consumes a large current resulting from the transmission of a high frequency clock signal. In addition, a control line that occupies a small layout area due to a relatively small number of toggles and a current consumption is provided, thereby ensuring overall control operations for the data output control circuit 140.

FIG. 4 is a circuit diagram briefly illustrating a method of supplying an internal clock DLL_CLK according to the present invention of FIG. 3. Referring to FIG. 4, a general control scheme for supplying the internal clock DLL_CLK to the unified clock path and unified path of the present invention is briefly shown.

Unlike the related art, the clock driver 110 is supplied with an internal clock DLL_CLK to one output terminal including three inverters. When the standby signal STANDBY is enabled, the internal clock DLL_CLK is not output to the output terminal in any case because the control input terminal of the NOR6 is set to a 'HIGH' level. But. When the standby signal STANDBY is disabled, the input control signal of NOR5 is transmitted to NOR6 and the internal clock DLL_CLK is transmitted to the output terminal. Therefore, when either or both of the ODT control signal TERMON and the data output control signal CLKDQP2D, which are inputs of the NOR gate 4 NOR4, are activated, the internal clock DLL_CLK is transferred to the output terminal. In particular, when the data output control signal CLKDQP2D is input, the data output control circuit 160 is transferred to the data output control circuit 160 through a transmission path 170 of a control signal provided separately.

The first repeater 130 recovers and retransmits the level of the internal clock DLL_CLK transmitted through the unified clock path CDQB_ODTB_F when the data output control signal CLKDQP2D or the ODT control signal TERMON is enabled. . Since the first repeater 120 amplifies and retransmits a signal for only one path, the first repeater 120 can reduce the area or size in half compared to the conventional repeater.

The second repeater 150 redistributes the internal clock DLL_CLK via the unified path CDQB_ODTB_F extending from the first repeater 130 to each part where the data input / output pins are distributed.

The data output control circuit 160 receives the internal clock DLL_CLK via the unified path CDQB_ODTB_F extending from the first repeater 130 described above in response to the data output control signal CLKDQP2D. The data output control circuit 160 does not receive the internal clock DLL_CLK when the data output control signal CLKDQP2D is disabled.

According to the internal clock DLL_CLK supply circuit of the present invention having the unified clock path and the repeater described above, unification of the output terminal and the repeater of the clock driver requiring large current consumption is implemented. In addition, the main clock path, which is accompanied by the consumption of large currents, is reduced to one, and the layout advantage of the unification of the relatively wide internal clock supply line is also obtained.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

 As described above, according to the clock supply circuit of the present invention, it is possible to reduce the current consumption and reduce the chip area allocated to the clock path by unifying the clock path providing the internal clock having a large number of toggles.

Claims (12)

A synchronous semiconductor memory device for supplying an internal clock generated from a delayed synchronization loop to termination circuits and a data output circuit. A clock driver for transmitting the internal clock in response to a termination control signal and a data output control signal; A distribution circuit for distributing the internal clock to the termination circuits and the data output circuits; And a single clock path for transferring the internal clock between the clock driver and the distribution circuit. The method of claim 1, And the clock driver outputs the internal clock to the single clock path when at least one of the termination control signal and the data output control signal is enabled. The method of claim 1, And the single clock path further comprises a repeater to compensate for a level drop of the internal clock. The method of claim 1, And a data output control circuit for controlling a data output buffer in response to the internal clock from the single clock path and the data output control signal. The method of claim 4, wherein And the data output control circuit receives the internal clock from the single clock path only when the data output control signal is activated. The method of claim 1, And a control signal path for transferring the data output control signal from the first area to the data output control circuit. The method of claim 6, And the control signal path has a smaller layout and a smaller current operating characteristic than the clock path. In the internal clock supply method of a synchronous semiconductor memory device, Unify a clock path from an internal clock source to a distribution circuit that distributes the internal clock to termination circuits and data input / output circuits; And distributing an internal clock transmitted through the unified clock path to the termination circuit and the data input / output circuit. The method of claim 8, The internal clock source further comprising a clock driver for transmitting the internal clock to the unified clock path in response to a control signal. The method of claim 9, And wherein said unified clock path comprises a repeater that recovers and retransmits the level of said internal clock. The method of claim 9, And the control signal includes a first control signal for controlling the transfer of the internal clock to the termination circuit and a second control signal for controlling whether the internal clock is transferred to the data input / output circuit. The method of claim 11, And a control signal transfer path transferring the second signal to the data input / output circuit such that the internal clock is transmitted to the data input / output circuit only when the second control signal is activated.

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