KR20070038675A - Voltage control device and method of semiconductor integrated circuit - Google Patents

Abstract

The present invention relates to a voltage control device and method for a semiconductor integrated circuit, comprising: a first circuit unit receiving external power through a corresponding power pin and an internal power line connected thereto; and at least two or more power sources corresponding to the external power source A second circuit part supplied through a pin and an internal power line connected to each of the pins, and connected between a power line of the first circuit part and a power line of the second circuit part, in response to a power down signal; It provides a voltage control device of a semiconductor integrated circuit comprising a switching means for connecting the. This allows the voltage to remain constant at all times, regardless of active mode or power-down mode, maximizing the operational reliability of the circuit.

VDD / DLL / Switching Part

Description

Apparatus and Method for Controlling Voltage of Semiconductor Integrated Circuits

1 is a circuit diagram showing an external power supply configuration of a semiconductor integrated circuit according to the prior art;

2 is a circuit diagram showing a configuration of a voltage control device of a semiconductor integrated circuit according to the present invention;

3 is a voltage waveform diagram according to FIG. 2.

-Explanation of symbols for the main parts of the drawing-

11: DLL circuit 12: peripheral circuit

21: switching unit

The present invention relates to a semiconductor integrated circuit, and more particularly, to a voltage control apparatus and method for a semiconductor integrated circuit.

In general, a semiconductor integrated circuit includes a core in which cells, which are the minimum units for data storage, are arranged, a data input / output related circuit for writing or reading data into a cell, peripheral circuits, and timing of each signal. A chip (Delay Locked Loop) circuit that provides a delay for generating a chip is manufactured by using a semiconductor process, and this is packaged using a method such as a fine ball grid array (FBGA). Configured.

The package includes a plurality of pins for receiving various signals and external voltages.

The semiconductor integrated circuit configured as described above requires operating power for operating the above-described configurations, and the operating power includes an external power supply VDD generated from a board of a system in which the semiconductor integrated circuit is installed. Received into the chip through and used to increase or reduce the pressure to fit the configuration.

Hereinafter, an external power supply configuration of a semiconductor integrated circuit according to the related art will be described with reference to FIG. 1.

1 is a circuit diagram showing an external power supply configuration of a semiconductor integrated circuit according to the related art.

In the related art, as shown in FIG. 1, an external power source VDD generated from a board is supplied to a DLL circuit 11 and a peripheral circuit 12 inside a chip through pins of a package.

At this time, the external power supply VDD supplied to the peripheral circuit 12 is supplied through a plurality of, for example, four pins and internal power lines connected to each pin to be used as a current source.

In contrast, the external power supply VDDL1 supplied to the DLL circuit 11 is supplied through one pin and an internal power supply line connected to the pin and used as a voltage source.

At this time, VDDL1 is at the same level as VDD supplied to the peripheral circuit 12 and is supplied from the same source, that is, the board. However, it is indicated by the VDD supplied to the peripheral circuit 12 and the VDDL1 supplied to the DLL circuit 11 based on the configuration in which each power source is used.

On the other hand, unlike the peripheral circuit 12 uses VDD as the current source, since the DLL circuit 11 uses VDDL1 as the voltage source, the voltage itself determines the stability of the operation. Therefore, VDDL1 is supplied through one pin, unlike when supplying to the peripheral circuit 12 for stable voltage supply.

VDDL1 then passes from the board through the package to the chip, via a resistor. That is, it passes through the contact resistance Ra and the metal resistance Rb.

Therefore, the voltage of the node A actually applied to the DLL circuit 11 when the DLL circuit 11 is in the active mode is as follows.

VA (voltage at node A) = VDDL1-(IVDDL1 * (Ra + Rb))

That is, VA falls in proportion to the resistances Ra and Rb and the current IVDDL1 flowing in the DLL circuit 11 in the active mode.

However, in the power down mode, that is, when the DLL circuit 11 is not the active mode, the power line applying the voltage to the DLL circuit 11 is in a floating state and accordingly the DLL circuit ( Since no current flows in 11), VA becomes equal to VDDL1.

That is, VA increases from VDDL1-(IVDDL1 * (Ra + Rb)) to VDDL1 by (IVDDL1 * (Ra + Rb)).

Subsequently, when the DLL circuit 11 enters the active mode again, the above-described voltage level is proportional to the resistances Ra and Rb and the current IVDDL1 flowing in the DLL circuit 11 in the active mode. VDDL-drops to (IVDDL1 * (Ra + Rb)).

Therefore, the semiconductor integrated circuit according to the related art has a problem that the voltage level applied to the DDL circuit is changed every time the active mode is entered from the power down mode, thereby causing a malfunction of the DLL circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a voltage control apparatus and method for a semiconductor integrated circuit capable of preventing a change in voltage supplied to a DLL circuit regardless of an operating state.

According to an embodiment of the present invention, a voltage controller of a semiconductor integrated circuit may include: a first circuit unit receiving external power through a corresponding power pin and an internal power line connected thereto; at least two power pins corresponding to the external power; A second circuit unit supplied through an internal power line connected to the second circuit unit and a switching unit connected between a power line of the first circuit unit and a power line of the second circuit unit to connect the two power lines according to a power down signal; It comprises a means.

In the voltage control method of a semiconductor integrated circuit according to the present invention, a first circuit unit receiving external power through an internal power line and using it as a voltage source, and a second circuit unit receiving the external power through an internal power line and using it as a current source A voltage control method of a semiconductor integrated circuit having a power supply, the power supply of the first circuit portion by switching means connected to a power line of the first circuit portion and a power line of the second circuit portion when the first circuit portion is in a power down mode. It characterized in that the line and the power line of the second circuit portion is connected.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram showing the configuration of a voltage control device of a semiconductor integrated circuit according to the present invention, Figure 3 is a voltage waveform diagram according to FIG.

As shown in FIG. 2, the voltage control device of a semiconductor integrated circuit according to the present invention includes a first circuit unit that receives an external power supply VDD from a corresponding power pin and an internal power line connected thereto, and uses the same as a voltage source. A second circuit part, that is, a peripheral circuit that receives the DLL circuit 11 and the external power supply VDD through a plurality of corresponding pins, for example, four pins and an internal power line connected to each of them, and uses them as a current source. 12 and a switching unit 21 connected between the power line of the DLL circuit 11 and the power line of the peripheral circuit 12 to connect the two power lines according to a power down signal. It is configured to include.

At this time, the external power supply VDDL2 supplied to the DDL circuit 11 is the same level as the VDD supplied to the peripheral circuit 12, and is denoted as VDDL2 to distinguish from each other and to distinguish from the prior art.

The DLL circuit 11 used as the VDDL2 operates sensitive to voltage. That is, since the voltage itself is not used as a current source but the stability of the operation, VDDL2 is supplied through one pin, unlike when supplying to the peripheral circuit 12 for stable voltage supply.

The switching unit 21 includes a transistor in which the power down signal is input to a gate, and a source and a drain are respectively connected to the two power lines. At this time, if the power supply signal is a low active signal, that is, a signal indicating the entry into the power down mode when the signal level is low, the switching unit 21 is turned on when the power down signal is low to the source and drain It is configured to connect two connected power lines.

The power down signal is a signal generated inside the chip and stops the operation of the DLL circuit 11 during the active period (high or low) of the signal.

Referring to the operation of the embodiment according to the present invention configured as described above are as follows.

First, as shown in FIG. 3, the DLL circuit 11 is in an active mode while the power down signal maintains a high level.

The VDDL2 supplied to the DLL circuit 11 goes from the board to the chip via the pins of the package and passes through the resistor. That is, it passes through the contact resistance Ra and the metal resistance Rb.

At this time, since the power down signal is high, the switching unit 21 is turned off, and the power line of the DLL circuit 11 and the power line of the peripheral circuit 12 are not connected.

Therefore, when the DLL circuit 11 is in the active mode, the voltage VA of the node A actually applied to the DLL circuit 11 is proportional to the current flowing through the resistance components Ra and Rb and the DLL circuit 11 in the active mode. It is dropped by using the following formula.

VA = VDDL2-(IVDDL2 * (Ra + Rb))

Meanwhile, as shown in FIG. 3, when the power down signal turns low, the active mode of the DLL circuit 11 is terminated and the operation is stopped.

Since the power down signal is low, the switching unit 21 is turned on to connect the power supply VDDL2 of the DLL circuit 11 and the power supply VDD of the peripheral circuit 12. Therefore, the resistance components Ra and Rb present in the power supply line of the DLL circuit 11 and the resistance components Rc and Rd present in the power supply line of the peripheral circuit 12 are also connected in parallel.

At this time, since the power line of the DLL circuit 11 and the power line of the peripheral circuit 12 are configured in the same package and chip, the contact resistance Ra and the metal resistance Rb and the peripheral current which exist in the power line of the DLL circuit 11. The contact resistance Rc and the metal resistance Rd present in the power supply line of the circuit 12 are not the same but have almost the same value so that the difference can be ignored.

In addition, since the same power source (VDD) is used, IVDDL2 and IVDD are also the same, and as a result, voltages applied to node A and node B have almost the same value.

That is, since the relationship IVDDL2 = IVDD, Ra = Rc, and Rb = Rd is established, VA when the DLL circuit 11 is in the power down mode becomes equal to VA when the DLL circuit 11 is in the active mode.

Subsequently, when the power down signal turns high again, the DLL circuit 11 operates in the active mode and the switching unit 21 is turned off to disconnect the power line of the DLL circuit 11 from the power line of the peripheral circuit 12. do.

Therefore, the voltage VA of the node A actually applied to the DLL circuit 11 continues to hold VDDL2-(IVDDL2 * (Ra + Rb)).

As described above, the VA according to the related art shown in FIG. 3 has risen to VDDL1 during the active period (low) of the power down signal. However, in the VA according to the present invention, the DLL circuit 11 is configured to switch between the active mode and the power down mode. It can be seen that VDDL2 − (IVDDL2 * (Ra + Rb)) remains constant regardless of repetition.

On the other hand, the DLL circuit 11 is an example of a circuit using an external power source (VDDL2) as a voltage source, the peripheral circuit 12 is only an example of a circuit using an external power source (VDD) as a current source. The present invention can be applied to any semiconductor integrated circuit having a circuit using an external power source as a voltage source and a circuit using a current source.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

The apparatus and method for controlling voltage of a semiconductor integrated circuit according to the present invention can maintain a constant voltage applied to a circuit using an external power source as a voltage source at all times regardless of an active mode and a power down mode, thereby maximizing operational reliability of the circuit. It can work.

Claims (8)

A first circuit unit receiving external power through a corresponding power pin and an internal power line connected thereto; A second circuit unit configured to receive the external power through at least two power pins corresponding to the external power and an internal power line connected to each of the external power; And And switching means connected between a power line of the first circuit portion and a power line of the second circuit portion to connect the two power lines according to a power down signal. The method of claim 1, And the first circuit part is a circuit part using an external power source as a voltage source. The method of claim 1, And the second circuit portion is a circuit portion using an external power source as a current source. The method of claim 1, And said first circuit portion is a DLL circuit. The method of claim 1, And the second circuit portion is a peripheral circuit. The method of claim 1, And said switching means is a transistor for receiving said power down signal at a gate and having a source and a drain connected to said two power lines, respectively. In the voltage control method of a semiconductor integrated circuit comprising a first circuit portion for receiving external power through an internal power line to use as a voltage source, and a second circuit portion for receiving the external power supply through an internal power line to use as a current source. , A semiconductor for connecting the power line of the first circuit portion and the power line of the second circuit portion by switching means connected to the power line of the first circuit portion and the power line of the second circuit portion when the first circuit portion is in the power down mode. Voltage control method of integrated circuit. The method of claim 7, wherein And controlling the switching means so that the power line of the first circuit part and the power line of the second circuit part are not connected when the first circuit part is in an active mode.

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