KR20070030711A - Semiconductor device - Google Patents

Abstract

In the device for data writing and erasing of a nonvolatile memory cell, data is rewritten by the FN tunnel current on the entire channel.

The p-type wells HPW1 to HPW3 are installed in the n-type buried well DNW of the semiconductor substrate 1S in the region where the flash memory is formed, and the capacitor portions are respectively disposed in the wells HPW1 to HPW3. (C), the capacitor portion CWE for data recording and erasing and the MIS FET (QR) for data reading are arranged. In the capacitor CWE for data recording and erasing, data is rewritten (recorded and erased) by the FN tunnel current on the entire channel.

Buried wells, sidewalls, bit lines for data writing and erasing, floating gate electrodes

Description

Semiconductor device {A SEMICONDUCTOR DEVICE}

1 is a plan view of a memory cell of a nonvolatile memory examined by the present inventors.

2 is a cross-sectional view taken along the line Y1-Y1 of FIG.

3 is a cross-sectional view taken along the line Y1-Y1 of FIG.

4 is an explanatory diagram showing the timing of voltage application during the data erasing operation of the nonvolatile memory examined by the present inventor.

Fig. 5 is an explanatory diagram showing the timing of voltage application in the data erasing operation of the nonvolatile memory examined by the present inventor.

Fig. 6 is an explanatory diagram showing the timing of voltage application in the data erasing operation of the nonvolatile memory examined by the present inventor.

7 is a main circuit diagram of a nonvolatile memory in the semiconductor device of one embodiment of the present invention.

FIG. 8 is a circuit diagram showing the voltage applied to each unit in the data write operation of the nonvolatile memory in FIG.

FIG. 9 is a circuit diagram showing an applied voltage of each unit in the data collective erasing operation of the nonvolatile memory of FIG. 7.

FIG. 10 is a circuit diagram showing the voltage applied to each part in the data bit unit erase operation of the nonvolatile memory shown in FIG. 7.

FIG. 11 is a circuit diagram showing an applied voltage of each part in the data read operation of the nonvolatile memory of FIG. 7.

12 is a plan view of a memory cell for one bit of the nonvolatile memory in the semiconductor device of one embodiment of the present invention.

FIG. 13 is a cross-sectional view taken along the line Y2-Y2 of FIG. 12.

FIG. 14 is a cross-sectional view taken along the line Y2-Y2 in FIG. 12 showing an example of the voltage applied to each part in the memory cell during the data write operation of the nonvolatile memory in the semiconductor device of one embodiment of the present invention.

FIG. 15 is a cross-sectional view taken along the line Y2-Y2 of FIG. 12 which shows applied voltages of respective portions in the data erasing operation of the nonvolatile memory of the semiconductor device of one embodiment of the present invention.

FIG. 16 is a cross-sectional view taken along the line Y2-Y2 of FIG. 12 which shows an applied voltage of each part in a data read operation of a nonvolatile memory of a semiconductor device of one embodiment of the present invention.

17 is a sectional view of principal parts of a semiconductor substrate in a main circuit formation region during a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 18 is a sectional view of principal parts of the semiconductor substrate in the nonvolatile memory region in the same process as in FIG. 17.

FIG. 19 is a sectional view of principal parts of the semiconductor substrate in the main circuit formation region during the manufacturing process of the semiconductor device continued from FIGS. 17 and 18.

FIG. 20 is a sectional view of principal parts of the semiconductor substrate in the nonvolatile memory region in the same process as in FIG. 19.

FIG. 21 is a sectional view of principal parts of the semiconductor substrate in the main circuit formation region during the manufacturing process of the semiconductor device continued from FIGS. 19 and 20.

FIG. 22 is a sectional view of principal parts of the semiconductor substrate in the nonvolatile memory region in the same process as in FIG.

FIG. 23 is a sectional view showing the principal parts of the semiconductor substrate in the main circuit formation region during the manufacturing process of the semiconductor device continued from FIGS. 21 and 22;

FIG. 24 is a sectional view of principal parts of the semiconductor substrate in the nonvolatile memory region in the same process as in FIG.

FIG. 25 is a cross sectional view of principal parts of the semiconductor substrate in the main circuit formation region during the manufacturing process of the semiconductor device continued from FIGS. 23 and 24;

FIG. 26 is a sectional view showing the principal parts of a semiconductor substrate in a nonvolatile memory region in the same process as in FIG.

FIG. 27 is a sectional view of principal parts of the semiconductor substrate in the main circuit formation region during the manufacturing process of the semiconductor device continued from FIGS. 25 and 26.

FIG. 28 is a sectional view of principal parts of the semiconductor substrate in the nonvolatile memory region in the same process as in FIG.

29 is a cross-sectional view of a semiconductor substrate in a main circuit formation region of a semiconductor device according to another embodiment of the present invention.

FIG. 30 is a cross-sectional view of a semiconductor substrate in a nonvolatile memory region of the semiconductor device of FIG. 29.

31 is an explanatory diagram of data recording characteristics and erasing characteristics of the semiconductor devices of FIGS. 29 and 30.

32 is a cross-sectional view of a semiconductor substrate in a main circuit formation region of a semiconductor device according to another embodiment of the present invention.

FIG. 33 is a cross-sectional view of a semiconductor substrate in a nonvolatile memory region of the semiconductor device of FIG. 32.

34 is a cross sectional view of a semiconductor substrate in a main circuit formation region of a semiconductor device according to another embodiment of the present invention.

FIG. 35 is a cross-sectional view of a semiconductor substrate in a nonvolatile memory region of the semiconductor device of FIG. 34.

36 is a cross sectional view of a semiconductor substrate in a main circuit formation region of a semiconductor device according to another embodiment of the present invention.

FIG. 37 is a cross-sectional view of a semiconductor substrate in a nonvolatile memory region of the semiconductor device of FIG. 36.

38 is a cross sectional view of a semiconductor substrate in a main circuit formation region of a semiconductor device according to another embodiment of the present invention.

FIG. 39 is a cross-sectional view of a semiconductor substrate in a nonvolatile memory region of the semiconductor device of FIG. 38.

40 is a plan view of a nonvolatile memory region of a semiconductor device according to still another embodiment of the present invention.

41 is a plan view of one example of a memory cell of a flash memory in a semiconductor device according to another embodiment of the present invention.

42 is a cross-sectional view taken along the line Y3-Y3 in FIG. 41.

43 is a plan view of one example of a memory cell of a flash memory in a semiconductor device according to another embodiment of the present invention.

FIG. 44 is a cross-sectional view taken along the Y4-Y4 line in FIG. 43.

45 is a cross-sectional view of the semiconductor substrate of the charge injection and discharge portion of the memory cell of the semiconductor device according to the embodiment of the present invention.

Fig. 46 is a cross sectional view of the semiconductor substrate of the charge injection and discharge portion of the memory cell of the semiconductor device according to another embodiment of the present invention;

Fig. 47 is a sectional view of the semiconductor substrate of the capacitor portion of the memory cell of the semiconductor device according to the embodiment of the present invention.

48 is a cross-sectional view of a semiconductor substrate of a capacitor of a memory cell of another embodiment of the present invention.

Fig. 49 is a graph showing a comparison of recording and erasing characteristics of data of a semiconductor device according to another embodiment of the present invention.

50 is a graph showing data recording characteristics of a semiconductor device according to another embodiment of the present invention.

51 is a graph showing data erasing characteristics of a semiconductor device according to another embodiment of the present invention.

Fig. 52 is a plan view of a memory cell formation region of a main surface of a semiconductor substrate during a manufacturing process of a semiconductor device according to another embodiment of the present invention.

Fig. 53 is a plan view of a memory cell formation region of a main surface of a semiconductor substrate during a semiconductor device manufacturing process;

Fig. 54 is a plan view of a memory cell formation region of a main surface of a semiconductor substrate in the manufacturing process of the semiconductor device of another embodiment of the present invention.

Fig. 55 is a plan view of a memory cell showing a mask for forming an n-type semiconductor region and a p-type semiconductor region in a memory cell of a flash memory of a semiconductor device according to another embodiment of the present invention.

Fig. 56 is a sectional view showing the principal parts of the semiconductor substrate in the charge injection and discharging portion of the memory cell in the flash memory of the semiconductor device according to the other embodiment of the present invention in a second direction X;

Fig. 57 is a sectional view showing the principal parts of the semiconductor substrate of the capacitor portion of the memory cell in the flash memory of the semiconductor device according to the other embodiment of the present invention in a second direction X;

Fig. 58 is a sectional view showing the principal parts of the semiconductor substrate in the second direction X of the capacitor portion at the time of data writing of the memory cell in the flash memory of the semiconductor device according to the other embodiment of the present invention.

Fig. 59 is a sectional view showing the principal parts of the semiconductor substrate of the capacitor portion at the time of data erasing of the memory cell in the flash memory of the semiconductor device according to another embodiment, in the second direction X;

(Explanation of the sign)

1S semiconductor substrate 4a p + type semiconductor region

5a silicide layer 6, 6a, 6b insulation layer

7a to 7k conductor region 8a n + type semiconductor region

10a gate insulating film 10b gate insulating film (second insulating film)

10c capacitive insulating film (third insulating film) 10d capacitive insulating film (first insulating film)

10e, 10f, 10g gate insulating film 11SW, 11DW n-type semiconductor region

12R n-type semiconductor region 12N-type semiconductor region

12a n-type semiconductor region 12b n + type semiconductor region

13 p-type semiconductor region 13a p + type semiconductor region

13b p- type semiconductor region 15 p type semiconductor region

15a p-type semiconductor region 15b p + type semiconductor region

20 Conductor film 21p type semiconductor region

21a p-type semiconductor region 21b p + type semiconductor region

22n-type semiconductor region 22a n-type semiconductor region

22b n + type semiconductor region 23p type semiconductor region

23a p-type semiconductor region 23b p + type semiconductor region

24n n-type semiconductor region 24a n-type semiconductor region

24b n + type semiconductor region 28 cap insulating film

28b cap insulating film 30 n-type semiconductor region

30a n-type semiconductor region 30b n + type semiconductor region

31-n-type semiconductor region 31a n--type semiconductor region

31b n + type semiconductor region 35 inversion layer

36 Depletion layer 40a, 40b n + type semiconductor region

43a depletion layer of 41a, 41b p + type semiconductor region

Buried well with TI separation part DNW n (first well)

HPWa, HPWb p wells HPW1 p wells (fourth well)

HPW2 p-type well (second well) HPW3 p-type well (third well)

HNW n-type well CT contact hole

L, L1-L5 active region FG floating gate electrode

MIS / FET FGW gate electrode for QW data recording and erasing

MIS / FET FGR gate electrode (second electrode) for reading QR data

C Capacitor CGW Control Gate Electrode

FGC capacitor electrode FGC2 capacitor electrode (third electrode)

MR memory cell array PR peripheral circuit area

WBL, WBL0, WBL1 Data writing and erasing RBL, RBL0, RBL2 data reading

              Bit line of bit line of

CG, CG0, CG1 control gate wiring SL source line

GS select line MC memory cell

Capacitor for recording and erasing CWE data FGC1 Capacitive electrode (first electrode)

QS Select MISFET FGS Gate Electrode

DPW p type well PV p type semiconductor region

NV n-type semiconductor region PW p-type well

NW n-type well FGH gate electrode

FGL gate electrode QPH p channel type MISFET

QPL p-channel MISFET QNH n-channel MISFET

QNL n-channel MISFET SW sidewall

NA, NB, NB2, NC, ND openings PA, PB, PC, PD, PE openings

TECHNICAL FIELD The present invention relates to semiconductor device technology, and more particularly, to a technology effective in application to a semiconductor device having a nonvolatile memory.

In the semiconductor device, a nonvolatile memory circuit unit for storing relatively small sized information such as information used for trimming, for relief, and for adjusting an image of an LCD (Liquid Crystal Device), or a manufacturing number of a semiconductor device. There is a thing.

A semiconductor device having this kind of nonvolatile memory circuit portion is described in, for example, Japanese Patent Laid-Open No. 2001-185633 (Patent Document 1). In this document, a single-level poly EEPROM device capable of reducing the area per bit in an EPROM (Electric Erasable Programmable Read Only Memory) device constituted over a single conductive layer insulated by an insulating layer on a semiconductor substrate is provided. Is shown.

For example, Japanese Patent Laid-Open No. 2001-257324 (Patent Document 2) discloses a technique capable of improving long-term information retention performance in a nonvolatile memory device formed by a single-layer poly flash technique.

Further, for example, Fig. 7 of USP6788574 (Patent Document 3) shows a configuration in which the capacitor portion, the write transistor, and the read transistor are separated in n wells, respectively. Further, in Fig. 4A-4C and column 6-7 of Patent Document 3, a configuration in which recording / erasing is performed at an FN tunnel current is shown.

[Patent Document 1] Japanese Patent Application Laid-Open No. 2001-185633

[Patent Document 2] Japanese Patent Application Laid-Open No. 2001-257324

[Patent Document 3] Figs. 7 and 4A-4c of USP6788574

By the way, the inventors of the present invention have studied about writing data into the write field effect transistor by the FN tunnel current on the entire channel. As a result, when data is written by the FN tunnel current, the breakdown recording field effect transistor deteriorates without having a junction breakdown voltage between the source and drain semiconductor regions of the field effect transistor and the well of the recording field effect transistor, and the data is rewritten. This unstable problem and the inability to record data were found to occur.

It is therefore an object of the present invention to provide a technique in which data can be rewritten by the FN tunnel current on the entire surface of a nonvolatile memory cell for data writing and erasing.

BRIEF DESCRIPTION OF THE DRAWINGS The above and further objects of the present invention will become apparent from the description and the accompanying drawings.

Among the inventions disclosed in the present application, an outline of representative ones will be briefly described as follows.

That is, the present invention relates to a nonvolatile memory cell having a data writing and erasing element having a common floating gate electrode as its gate electrode and a transistor for data reading, wherein the elements for data writing and erasing and data reading are used. Transistors are placed in wells of the same conductivity type that are electrically separated from each other, and a pair of semiconductor areas of the data recording and erasing elements are formed of the wells and the same conductivity type semiconductor area.

Best Mode for Carrying Out the Invention

In the following embodiments, when necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments. However, unless specifically indicated, they are not related to each other, and one side is partially or entirely modified on the other side. Yes, details, supplementary explanations and so on. In addition, in the following embodiment, when referring to the number of elements (including number, numerical value, quantity, range, etc.), except when specifically stated and when it is specifically limited to the specific number clearly, the same It is not limited to a specific number, More than a specific number may be sufficient. Moreover, in the following embodiments, it is needless to say that the components (including the element steps and the like) are not necessarily essential except when specifically stated and when considered to be clearly essential in principle. Equally, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is substantially similar or similar to the shape except for the case where it is specifically stated and when it thinks that it is not clear in principle. It shall include things.

This also applies to the above numerical values and ranges. In addition, in all the drawings for demonstrating this embodiment, the thing which has the same function is attached | subjected with the same code | symbol, and the description of the repetition is abbreviate | omitted as much as possible. EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on drawing.

Embodiment 1

First, the configuration of the flash memory examined by the present inventors and the problem of data writing in the flash memory will be described. 1 is a plan view of a memory cell MC of a flash memory examined by the present inventors, and FIGS. 2 and 3 are cross-sectional views taken along the line Y1-Y1 of FIG. 1, respectively. An example is shown. In addition, Y of the sign indicates the extension direction of the local data line in the first direction, and X of the sign indicates the extension direction of the word line in the second direction orthogonal to the first direction.

The semiconductor substrate (hereinafter simply referred to as substrate) 1S constituting the semiconductor chip is formed of, for example, silicon (Si) single crystal of P type (second conductive type). Separation part TI is arrange | positioned at the main surface of this board | substrate 1S. This separating portion TI is a portion defining the active regions L (L1, L2, L3, L4, L5). Here, the separation portion TI is formed by embedding an insulating film made of silicon oxide or the like in a shallow groove formed in the main surface of the substrate 1S, for example, so-called shallow groove isolation (SGI) or shallow trench isolation (STI). It is a groove-shaped separation part called.

An n-type (first conductive type) buried well DNW is formed in the substrate 1S over a desired depth on its main surface. The p wells HPWa and HPWb and the n well HNW are formed in the buried well DNW. The p-type wells HPWa and HPWb are contained in the buried well DNW in a state where they are electrically separated from each other by the n-type wells HNW.

The p-type wells HPWa and HPWb contain impurities such as p-type such as boron. The p + type semiconductor region 4a is formed in a part of the upper layer of the p type well HPWa. The p + type semiconductor region 4a contains the same impurities as the p type well HPWa, but the impurity concentration of the p + type semiconductor region 4a is higher than that of the p type well HPWa. It is set to be high. In part of the surface layer of the p + type semiconductor region 4a, a silicide layer 5a such as cobalt silicide (CoSi) or the like is formed. The p + type semiconductor region 4a is electrically connected to the conductor portion 7a in the contact hole CT formed in the insulating layer 6 on the main surface of the substrate 1S via the silicide layer 5a. . The insulating layer 6 is equipped with the insulating layer 6a and the insulating layer 6b deposited on it. The lower insulating layer 6a is made of, for example, silicon nitride (Si 3 N 4), and the upper insulating layer 6b is made of, for example, silicon oxide (SiO 2).

In addition, the n-type well HNW contains an n-type impurity such as phosphorus (P) or arsenic (As), and the impurity concentration is higher than that of the buried well DNW. Is formed. An n + type semiconductor region 8a is formed in a portion of the upper layer of the n type well HNW. The n + type semiconductor region 8a contains the same impurities as the n type well HNW, but the impurity concentration of the n + type semiconductor region 8a is higher than the impurity concentration of the n type well HNW. It is set to be high. The n + type semiconductor region 8a is electrically connected to the conductor portion 7b in the contact hole CT formed in the insulating layer 6 via the silicide layer 5a formed at a portion of the surface layer thereof.

The memory cell MC of the flash memory includes a floating gate electrode FG, a metal insulator semiconductor field effect transistor (MISFET) (QW) for data writing and erasing, and a MISFET (QR) for data reading. ) And a capacitive portion (C).

The floating gate electrode FG is a portion which accumulates electric charges which contribute to the storage of information. The floating gate electrode FG is formed of a conductor film such as low-resistance polycrystalline silicon or the like, and is formed in an electrically floating state (a state insulated from other conductors). In addition, as shown in FIG. 1, the floating gate electrode FG is formed in a state extending along the first direction Y so as to overlap planarly on both of the p-type wells HPWa and HPWb adjacent to each other. .

The data recording / erasing MISFET QW is arranged at a position where the floating gate electrode FG overlaps with the active region L1 of the p-type well HPWa in plan view. The MISFET QW for data recording and erasing includes a gate electrode FGW, a gate insulating film 10a, an n-type semiconductor region 11SW for a pair of sources, and an n-type semiconductor for a drain. The region 11DW is provided. The channel of the data recording / erasing MISFET QW is formed in the upper layer of the p-type well HPWa in which the gate electrode FGW and the active region L1 overlap in a plane.

The gate electrode FGW is formed by a part of the floating gate electrode FG.

The gate insulating film 10a is made of, for example, silicon oxide, and is formed between the gate electrode FGW and the substrate 1S (P type well HPWa). The thickness of the gate insulating film 10a is, for example, about 13.5 nm. The source semiconductor region 11SW and the drain semiconductor region 11DW are formed in a self-aligned manner with respect to the gate electrode FGW at a position where the gate electrode FGW is inserted in the p-type well HPWa. do. The semiconductor regions 11SW and 11DW each have an n-type semiconductor region on the channel side and an n + type semiconductor region connected to each of them. The n-type semiconductor region and the n + type semiconductor region contain the same conductivity type impurities such as phosphorus or arsenic (As), for example, but the impurity concentration of the n + type semiconductor region is the n-type semiconductor. It is set to be higher than the impurity concentration of the region. The semiconductor regions 11SW and 11DW are electrically connected to the conductor portion 7c in the contact hole CT formed in the insulating layer 6 via the silicide layer 5a formed at a portion of the surface layer thereof.

The MISFET QR for data reading is arranged at a position where the floating gate electrode FG overlaps with the active region L2 of the p-type well HPWa in plan view. The MISFET QR for reading data includes a gate electrode FGR, a gate insulating film 10b, and a pair of n-type semiconductor regions 12R and 12R. The channel of the data read MISFET QR is formed in the upper layer of the p-type well HPWa in which the gate electrode FGR and the active region L2 overlap in a plane.

The gate electrode FGR is formed by a part of the floating gate electrode FG.

The gate insulating film 10b is made of, for example, silicon oxide, and is formed between the gate electrode FGR and the substrate 1S (P type well HPW). The thickness of the gate insulating film 10b is, for example, about 13.5 nm. The pair of n-type semiconductor regions 12R and 12R are formed in self-alignment with respect to the gate electrode FGR at a position where the gate electrode FGR is inserted in the p-type well HPWa. Each of the pair of n-type semiconductor regions 12R and 12R includes an n-type semiconductor region on the channel side and an n + type semiconductor region connected to each of them. The n-type semiconductor region and the n + -type semiconductor region contain the same conductivity type impurities such as phosphorus (P) or arsenic (As), but the impurity concentration of the n + -type semiconductor region is n-. It is set to be higher than the impurity concentration in the semiconductor region of the mold. The semiconductor regions 12R and 12R are electrically connected to the conductor portion 7d in the contact hole CT formed in the insulating layer 6 via the silicide layer 5a formed at a portion of the surface layer thereof.

The capacitor C is formed at a position where the floating gate electrode FG overlaps the planar well of the p-type well HPWb. The capacitor C includes a control gate electrode CGW, a capacitor electrode FGC, a capacitor insulating film 10c, and a p + type semiconductor region 13a.

The control gate electrode CGW is formed by the p-type well HPWb portion facing the floating gate electrode FG. On the other hand, the capacitor electrode FGC is formed by a portion of the floating gate electrode FG opposite to the control gate electrode CGW. By setting the gate structure of the memory cell MC into a single layer structure in this way, it is possible to facilitate the manufacturing matching between the memory cell MC of the flash memory and the elements of the main circuit, thereby reducing the manufacturing time of the semiconductor device. The manufacturing cost can be reduced.

The length of the second direction X of the capacitor electrode FGC is equal to that of the gate electrodes FGW and FGR of the MISFET QW for data writing and erasing and the MISFET QR for data reading. It is formed to be longer than the length of the second direction X. As a result, since the planar area of the capacitor electrode FGC can be largely secured, the coupling ratio can be increased and the voltage supply efficiency from the control gate wiring CGW can be improved.

The capacitor insulating film 10c is made of, for example, silicon oxide, and is formed between the control gate electrode CGW and the capacitor electrode FGC. The capacitor insulating film 10c is simultaneously formed by a thermal oxidation process for forming the gate insulating films 10a and 10b, and the thickness thereof is, for example, about 13.5 nm. Further, the gate insulating films 10a and 10b and the capacitor insulating film 10c are high withstand voltage MISFETs having a relatively thick gate insulating film in a main circuit, and among the low breakdown voltage MISFETs having a relatively thin gate insulating film, It is formed by the same process as the gate insulating film of the MISFET. As a result, the reliability of the flash memory can be improved.

The p + type semiconductor region 13a is formed in a self-aligned manner with respect to the capacitor electrode FGC at the position where the capacitor electrode FGC is inserted in the p type well HPWb. The semiconductor region 13a contains impurities of the same conductivity type as the p-type well HPWb such as boron (B) and the like, but the impurity concentration of the p + type semiconductor region 13a is p-type. It is set to be higher than the impurity concentration of the well HPWb. The semiconductor region 13a is electrically connected to the conductor portion 7e in the contact hole CT formed in the insulating layer 6 via the silicide layer 5a formed at a portion of the surface layer thereof.

By the way, in the MISFET (QW) for writing and erasing a flash memory having such a configuration, when data is recorded by the FN tunnel current in the front of the channel, as shown in Figs. The n-type semiconductor regions 11SW and 11DW for the source and the drain of the MISFET QW for drainage are set to, for example, open (OPEN) or set to 9V. However, in the case of opening (FIG. 2), it has been found that transistors for cutoff are required on both sides of the n-type semiconductor regions 11SW and 11DW for source and drain, which hinders the miniaturization of the semiconductor device. On the other hand, when 9V is applied to the n-type semiconductor regions 11SW and 11DW (FIG. 3), the junction breakdown voltage of the n-type semiconductor regions 11SW and 11DW for the source and drain is lower than 9V. A problem arises in that the write / erase MIS / FET (QW) deteriorates due to breakdown without holding. In addition, it has been found that the data rewriting area and the data reading area are formed in the same well, so that the data rewriting becomes unstable and the data cannot be recorded well.

In the flash memory having the above-described configuration, timing design is necessary so that voltages higher than the breakdown voltage are not applied to the n-type semiconductor regions 11SW and 11DW for the source and drain. 4 to 6 show explanatory diagrams showing timings of voltage application in the data erase operation of the flash memory. First, as shown in FIG. 4, before the voltage of 9V is applied to the p-type well HPWa, the voltage of 9V is applied to the drain of the MISFET QW for data recording and erasing. In addition, when the voltage of the p-type well HPWa is returned to 0V before the drain voltage of the MISFET QW for data recording and erasing is returned to 0V, the potential difference V1 of both sides exceeds the junction breakdown voltage. It throws away and causes joint breakage. In the data erasing operation, the p-type well HPWa and the drain of the MIS FET QW for data recording / erasing (n-type semiconductor region 11DW) at the same timing as shown in FIGS. 5 and 6. A voltage is applied to)) so that the potential difference (V1) of both is not more than about 7V.

For example, as shown in FIG. 5, the voltage of the drain of the MISFET QW is generated before the voltage of the p-type well HPWa is applied. At this time, both voltages are gradually raised without suddenly being applied so that the potential difference V1 does not exceed the junction breakdown voltage.

In addition, prior to returning the drain voltage of the MISFET QW to 0V, the voltage of the p-type well HPWa is returned to 0V, so that both voltage variations at this time are not abrupt. ) Do not exceed the junction internal pressure.

For example, as shown in Fig. 6, before applying the voltage of the p-type well HPWa, the voltage of the drain of the MISFET QW is applied, and the voltage of the p-type is set to 4V or 5V before raising to 9V. The voltage of the well HPWa may be applied. At this time, the voltage of the P-type well HPWa is changed to be the same as the voltage of the drain of the MISFET QW only with a different timing. Thereby, it is possible to prevent both potential differences V1 from exceeding the junction breakdown voltage. When the drain voltage of the MISFET QW and the voltage of the p well HPWa are returned to 0 V, the voltage of the p well HPWa is reduced before the drain voltage of the MISFET QW is lowered. The voltage change at that time may be reversed through the change process at the time of raising the voltage.

In this manner, in the MIS FET (QW) for writing and erasing the flash memory having the above-described structure, the n-type semiconductor regions 11SW and 11DW for the source and drain thereof are used for rewriting data by the FN tunnel current in front of the channel. In the case of applying 9V), the above timing design is required. However, in order to realize the above timing design, it has been found that there is a problem that the size of the peripheral circuit formed on the same substrate 1S becomes large, which hinders the miniaturization of the semiconductor device.

Next, the semiconductor device of the first embodiment will be described.

In the semiconductor device according to the first embodiment, a flash memory (non-volatile memory) for storing a main circuit and relatively small desired information relating to the main circuit is formed on the same semiconductor chip. The main circuit includes, for example, memory circuits such as DRAM (Dynamic Random Access Memory), SRAM (StaticRAM), logic circuits such as CPU (Central Processing Unite), MPU (Micro Processing Unite), and the like, and a mixture of such memory circuits and logic circuits. Circuit or liquid crystal device (LCD) driver circuit.

In addition, the desired information includes, for example, arrangement address information of an effective (used) device used for trimming in a semiconductor chip, an effective memory cell (memory cell without defect) or an effective LCD used for memory or LCD rescue. And the arrangement address information of the device, trimming tap information of the adjustment voltage used in adjusting the LCD image, or the serial number of the semiconductor device. The external power source supplied from the outside of the semiconductor device (semiconductor chip, semiconductor substrate) is a single power source. The power supply voltage of a single power supply is about 3.3V, for example.

Fig. 7 shows a main circuit diagram of the flash memory in the semiconductor device of the first embodiment. This flash memory has a memory cell array MR and a peripheral circuit region PR. The memory cell array MR includes a plurality of bit lines WBL (WBL0, WBL1 ...) for data writing and erasing extending in the first direction Y, and bit lines RBL (RBLO, RBL2, ...) for data reading. ) Is disposed along the second direction X. The memory cell array MR further includes a plurality of control gate wirings (word lines) CG (CG0, CG1, ...) extending along the second direction X orthogonal to the bit lines WBL and RBL. A plurality of source lines SL and a plurality of selection lines GS are disposed along the first direction Y. In FIG.

The bit line WBL for data writing and erasing is electrically connected to the inverter circuit INV for inputting data (0/1) arranged in the peripheral circuit region PR. In addition, the bit lines RBL for reading data are electrically connected to the sense amplifier circuits SA arranged in the peripheral circuit region PR. The sense amplifier circuit SA is, for example, a current mirror type. One bit of the memory cell MC is electrically connected to the bit line WBL, RBL, the control gate wiring CG, the source line SL, and the selection line GS near the lattice-shaped intersection. Connected. Here, the case where one bit is comprised by two memory cells MC is illustrated.

Each memory cell MC includes a capacitor portion (charge injection / discharge portion) CWE for data recording and erasing, a MISFET (QR) for reading data, a capacitor portion C, and a selected MISFET. Equipped with (QS). The capacitors CWE and CWE for recording and erasing data of the two memory cells MC of each bit are electrically connected to each other in parallel. One electrode of each of the capacitive sections CWE for data recording and erasing is electrically connected to the bit line WBL for data recording and erasing. The other electrode (floating gate electrode FG) of the capacitive portion CWE for data recording and erasing, respectively, is a gate electrode (floating) of the MISFETs QR and QR for reading data, respectively. It is electrically connected to the gate electrode FG, and is electrically connected to one electrode (the floating gate electrode FG) of the capacitors C and C. The other electrodes (control gate electrodes CGW) of the capacitors C and C are electrically connected to the control gate wiring CG. On the other hand, the MISFETs (QR, QR) for data reading of the two memory cells MC of each bit are electrically connected in series with each other, and the drain thereof is connected to the data through the selected MISFET (QS). It is electrically connected to the read bit line RBL, and the source is electrically connected to the source line SL. The gate electrode of the selection MIS-FET QS is electrically connected to the selection line GS.

Next, examples of the data writing operation in such a flash memory will be described with reference to Figs. FIG. 8 shows the voltage applied to each part in the data write operation of the flash memory of FIG. The broken line S1 indicates the memory cell MC (hereinafter referred to as the selected memory cell MCs) as the data recording target. Incidentally, in this example, the injection of electrons into the floating gate electrode is defined as data recording. On the contrary, the extraction of electrons from the floating gate electrode can be defined as data recording.

When data is written, a positive control voltage of, for example, about 9V is applied to the control gate wiring CG0 (CG) to which the other electrode of the capacitor C of the selected memory cells MCs is connected. Is authorized. A voltage of 0 V is applied to the other control gate wiring CG1 (CG), for example. The bit line WBL0 (WBL) for data recording / erasing, which is electrically connected to one electrode of the capacitor CWE for data recording / erasing of the selected memory cells MCs, is, for example, about -9V. A negative voltage is applied. A voltage of 0 V is applied to the other bit lines WBL1 (WBL) for data recording and erasing. Further, for example, 0 V is applied to the selection line GS, the source line SL, and the bit line RBL for data writing. As a result, electrons are injected into the floating gate electrodes of the capacitors CWE and CWE for data recording and erasing of the selected memory cells MCs by the FN tunnel current on the entire surface of the channel, and data is recorded.

Next, FIG. 9 shows the voltage applied to each part in the data collective erasing operation of the flash memory of FIG. The broken line S2 indicates a plurality of memory cells MC (hereinafter referred to as the selected memory cell MCsel) to be subjected to data collective erasing. In this case, the extraction of electrons from the floating gate electrode is defined as data erasing. On the contrary, the injection of electrons into the floating gate electrode can be defined as data erasing.

At the time of data collective erasing, a negative control voltage of, for example, about -9V is applied to the control gate wirings CG0 and CG1 (CG) to which the other electrode of the capacitor C of the plurality of selected memory cells MCse1 is connected. Is applied. Further, for example, about 9V to the bit lines WBL0 and WBL1 (WBL) for data recording and erasing, in which one electrode of the capacitor CWE for data recording and erasing of the selected memory cell MCsel is electrically connected. Apply a negative voltage of. Further, for example, 0 V is applied to the selection line GS, the source line SL, and the bit line RBL for data writing. As a result, electrons accumulated in the floating gate electrodes of the capacitors CWE and CWE for data recording and erasing of the plurality of selected memory cells MCse1 for collective data erasing are discharged by the FN tunnel current on the entire channel surface. The data of the plurality of selected memory cells MCse1 are collectively erased.

Next, FIG. 10 shows the voltage applied to each part in the data bit unit erase operation of the flash memory of FIG. The broken line S3 indicates the memory cell MC (hereinafter referred to as the selected memory cell MCse2) which is the data collective erasing target.

At the time of data bit unit erase, a negative control voltage of, for example, about -9 V is applied to the control gate wiring CG0 (CG) to which the other electrode of the capacitor C of the selected memory cell MCse2 is connected. do. A voltage of 0 V is applied to the other control gate wiring CG1 (CG), for example. Further, for example, a definition of about 9 V is defined for the bit line WBL0 (WBL) for data recording / erasing, in which one electrode of the capacitor CWE for data recording / erasing of the selected memory cell MCse2 is electrically connected. Apply voltage. A voltage of 0 V is applied to the other bit lines WBL1 (WBL) for data recording and erasing. Further, for example, 0 V is applied to the selection line GS, the source line SL, and the bit line RBL for data writing.

As a result, electrons accumulated in the floating gate electrodes of the capacitor parts CWE and CWE for data recording and erasing in the selected memory cell MCse2 for data erasing are discharged by the FN tunnel current on the entire channel to erase the data. The data of the target selected memory cell MCse2 is erased.

Next, FIG. 11 shows the voltage applied to each part in the data read operation of the flash memory of FIG. The broken line S4 indicates the memory cell MC (hereinafter referred to as the selected memory cell MCr) as the data reading object.

When reading data, a control voltage of, for example, about 3V is applied to the control gate wiring CG0 (CG) to which the other electrode of the capacitor C of the selected memory cell MCr is connected. A voltage of 0 V is applied to the other control gate wiring CG1 (CG), for example. Further, for example, about 0 V to the bit lines WBL0 and WBL0 (WBL) for data recording and erasing, in which one electrode of the capacitor CWE for data recording and erasing of the selected memory cell MCr is electrically connected. Apply a voltage of. In addition, a voltage of, for example, about 3V is applied to the selection line GS to which the gate electrode of the selection MISFET QS of the selection memory cell MCr is electrically connected. Then, for example, a voltage of about 1 V is applied to the bit line RBL for data writing. In addition, for example, 0 V is applied to the source line SL. As a result, the MISFET (QR) for data reading of the selected memory cell MCr to be read data is turned on and a drain current is applied to the channel of the MISFET (QR) for data reading. By whether or not it flows, it reads out whether the data stored in the selected memory cell MCr is 0/1.

Next, FIG. 12 is a plan view of the memory cell MC for one bit of the flash memory in the semiconductor device of the first embodiment, and FIG. 13 is a sectional view taken along the line Y2-Y2 in FIG. In addition, in FIG. 12, a part was hatched to make the drawing easy to see.

 On the main surface of the p-type substrate 1S, the spherical separation portions TI defining the active regions L (L1, L2, L3, L4, L5) are formed. In the n-type (first conductive type) buried well (first well) DNW formed in the substrate 1S, p-type (second conductive type) wells (HPW1, HPW2, HPW3) and n-type wells (HNW) is formed. The p-type wells HPW1, HPW2 and HPW3 are embedded in the embedded well DNW in a state in which they are electrically separated from each other by the buried well DNW and the n-type well HNW.

The p-type wells HPW1 to HPW3 contain impurities such as p-type such as boron (B) and the like. The p + type semiconductor region 4a is formed in a portion of the upper layer of the p type well HPW3. The p + type semiconductor region 4a contains the same impurities as the p type well HPW3, but the impurity concentration of the p + type semiconductor region 4a is higher than that of the p type well HPW3. It is set to be high. The p + type semiconductor region 4a is electrically connected to the conductor portion 7a in the contact hole CT formed in the insulating layer 6 on the main surface of the substrate 1S. The silicide layer 5a may be formed at a portion of the surface layer of the p + type semiconductor region 4a that the conductor portion 7a is in contact with.

The n-type well HNW contains an n-type impurity such as phosphorus (P) or arsenic (As). An n + type semiconductor region 8a is formed in a portion of the upper layer of the n type well HNW. The n + type semiconductor region 8a contains the same impurities as the n type well HNW, but the impurity concentration of the n + type semiconductor region 8a is higher than the impurity concentration of the n type well HNW. It is set to be high. The n + type semiconductor region 8a is separated from the p type wells HPW1 to HPW3 so as not to contact the p type wells HPW1 to HPW3. In other words, a portion of the n-type buried well DNW is interposed between the n + -type semiconductor region 8a and the p-type wells HPW1 to HPW3. The n + type semiconductor region 8a is electrically connected to the conductor portion 7b in the contact hole CT formed in the insulating layer 6. The silicide layer 5a may be formed in a portion of the surface layer of the n + type semiconductor region 8a which the conductor portion 7b is in contact with.

The memory cell MC of the flash memory of the first embodiment includes a floating gate electrode FG, a capacitor portion CWE for data writing and erasing, a MISFET QR for reading data, and a capacitor portion. (C) is provided.

The floating gate electrode FG is a portion which accumulates electric charges which contribute to the storage of information. The floating gate electrode FG is made of a conductor film such as low-resistance polycrystalline silicon, for example, and is formed in an electrically floating state (isolated from other conductors). 12, this floating gate electrode FG is formed in the state extended along the 1st direction Y so that it may overlap planarly with the said p-type wells HPW1, HPW2, HPW3 adjacent to each other. .

The capacitor CWE for data recording and erasing is disposed at a first position where the floating gate electrode FG overlaps with the active region L2 of the p-type well (second well) HPW2 in plan view. . The capacitor portion CWE for data recording and erasing includes a capacitor electrode (first electrode) FGC1, a capacitor insulating film (first insulating film) 10d, p-type semiconductor regions 15 and 15, and p. A type well HPW2 is provided.

The capacitor electrode FGC1 is formed by a part of the floating gate electrode FG, and is a portion which forms the other electrode of the capacitor portion CWE. The capacitor insulating film 10d is made of, for example, silicon oxide, and is formed between the capacitor electrode FGC1 and the substrate 1S (p type well HPW2). The thickness of the capacitor insulating film 10d is, for example, 10 nm or more and 20 nm or less.

However, in the capacitor portion CWE of the first embodiment, in rewriting data, electrons are injected into the capacitor electrode FGC1 from the p-type well HPW2 through the capacitor insulating film 10d or the capacitor electrode FGC1. Electrons are emitted into the p-type well HPW2 through the capacitor insulating film 10d, so that the thickness of the capacitor insulating film 10d is thin, specifically, set to a thickness of about 13.5 nm, for example. The reason why the thickness of the capacitor insulating film 10d is 10 nm or more is that if the thickness is thinner than that, the reliability of the capacitor insulating film 10d cannot be secured. The reason why the thickness of the capacitor insulating film 10d is 20 nm or less is because it is difficult to pass electrons when it is thicker than that, and data rewriting is not good.

The p-type semiconductor region 15 of the capacitor portion CWE is formed in self-alignment with respect to the capacitor electrode FGC1 at the position where the capacitor electrode FGC1 is inserted in the p-type well HPW2.

Each of the semiconductor regions 15 includes a p-type semiconductor region 15a on the channel side and a p + type semiconductor region 15b connected to each of them. Although the p-type semiconductor region 15a and the P + type semiconductor region 15b contain impurities of the same conductivity type as, for example, boron (B), the impurity concentration of the p + type semiconductor region 15b is higher. It is set to be higher than the impurity concentration of the p-type semiconductor region 15a. The p-type semiconductor region 15 is electrically connected to the P-type well HPW2. The p-type semiconductor region 15 and the p-type well HPW2 are portions which form the above-mentioned electrode of the capacitor portion CWE. The p-type semiconductor region 15 is electrically connected to the conductor portion 7c in the contact hole CT formed in the insulating layer 6. The conductor portion 7c is electrically connected to the bit line WBL for data recording and erasing. The silicide layer 5a may be formed at a portion of the surface layer of the p + type semiconductor region 15b in contact with the conductor portion 7c.

The MISFET QR for data reading is arranged at a second position where the floating gate electrode FG overlaps with the active region L1 of the p-type well (third well) HPW3 in plan view. do. The configuration of the MIS FET (QR) for data reading is the same as that described with reference to FIGS. That is, the MISFET QR for reading data includes a gate electrode (second electrode) FGR, a gate insulating film (second insulating film) 10b, and a pair of n-type semiconductor regions 12 and 12. ). The channel of the MISFET QR for data reading is formed in the upper layer of the well 1 of the type 1 HPW3 in which the gate electrode FGR and the active region L1 overlap in a plane.

The gate electrode FGR is formed by a part of the floating gate electrode FG.

The gate insulating film 10b is made of, for example, silicon oxide, and is formed between the gate electrode FGR and the substrate 1S (P type well HPW3). The thickness of the gate insulating film 10b is, for example, about 13.5 nm. The pair of n-type semiconductor regions 12 and 12 of the MISFET QR for data reading have the gate electrode FGR at a position where the gate electrode FGR is inserted in the p-type well HPW3. Self-aligning with respect to The pair of n-type semiconductor regions 12 and 12 of the MISFET (QR) for data reading are respectively n-type semiconductor regions 12a on the channel side and n + type semiconductor regions connected to each of them. 12b is provided.

The n-type semiconductor region 12a and the n + -type semiconductor region 12b contain impurities of the same conductivity type, such as phosphorus (P) or arsenic (As), for example, but the n + -type semiconductor region 12b. Impurity concentration is set to be higher than the impurity concentration of the n-type semiconductor region 12a. One of the semiconductor regions 12 and 12 of the MISFET QR for data reading is electrically connected to the conductor portion 7d in the contact hole CT formed in the insulating layer 6. This conductor portion 7d is electrically connected to the source line SL. The silicide layer 5a may be formed at a portion of the surface layer of the n + type semiconductor region 12b in contact with the conductor portion 7d. On the other hand, the other of the semiconductor regions 12 and 12 of the MISFET QR for data reading is one of the n-type semiconductor regions 12 for the source and the drain of the selected MISFET QS. Is shared.

The selection MIS-FET QS includes a gate electrode FGS, a gate insulating film 10e, and a pair of n-type semiconductor regions 12 and 12 for source and drain. The channel of the selected MISFET QS is formed in the upper layer of the p-type well HPW3 in which the gate electrode FGS and the active region L1 overlap in a plane.

The gate electrode FGS is formed of, for example, low resistance polycrystalline silicon. The gate electrode FGS is electrically connected to the conductor portion 7f in the contact hole CT formed in the insulating layer 6. This conductor portion 7f is electrically connected to the selection line GS. The gate insulating film 10e is made of, for example, silicon oxide, and is formed between the gate electrode FGS and the substrate 1S (p type well HPW3). The thickness of the gate insulating film 10e is, for example, about 13.5 nm. The configuration of the pair of n-type semiconductor regions 12 and 12 of the selected MIS-FET QS is the same as the n-type semiconductor region 12 of the MIS-FET QR for data reading. The other n-type semiconductor region 12 of the selected MIS-FET QS is electrically connected to the conductor portion 7g in the contact hole CT formed in the insulating layer 6.

The conductor portion 7g is electrically connected to the bit line RBL for data reading.

The silicide layer 5a may be formed at a portion of the surface layer of the n + type semiconductor region 12b in contact with the conductor portion 7g.

The capacitor C is formed at a position where the floating gate electrode FG overlaps with the p-type well (fourth well) HPW1 in plan view. The structure of this capacitor | capacitor C is as having demonstrated in FIGS. That is, the capacitor C includes the control gate electrode CGW, the capacitor electrode (third electrode) FGC2, the capacitor insulating film (third insulating film) 10c, and the p-type semiconductor region 13. And the p-type well HPW1.

The capacitor electrode FGC2 is formed by a portion of the floating gate electrode FG facing the control gate electrode CGW, and is a portion which forms one electrode of the capacitor portion C. As shown in FIG. By setting the gate structure of the memory cell MC into a single layer structure in this way, it is possible to facilitate the manufacturing matching between the memory cell MC of the flash memory and the elements of the main circuit, thereby reducing the manufacturing time of the semiconductor device. The manufacturing cost can be reduced.

The length of the second direction X of the capacitor electrode FGC2 is equal to the length of the capacitor electrode FGC1 of the capacitor portion CWE for data writing and erasing or the gate electrode of the MISFET QR for data reading. FGR) is formed to be longer than the length of the second direction X. As a result, since the planar area of the capacitor electrode FGC2 can be secured large, the coupling ratio can be increased, and the voltage supply efficiency from the control gate wiring CGW can be improved.

The capacitor insulating film 10c is made of, for example, silicon oxide, and is formed between the capacitor electrode FGC2 and the substrate 1S (p type well HPW1). The capacitor insulating film 10c is formed simultaneously by a thermal oxidation process for forming the gate insulating films 10b and 10e and the capacitor insulating film 10d, and the thickness thereof is, for example, about 13.5 nm.

The p-type semiconductor region 13 of the capacitor portion C is formed in self-alignment with the capacitor electrode FGC2 at the position where the capacitor electrode FGC2 is inserted in the p-type well HPW1. Each of the semiconductor regions 13 includes a p-type semiconductor region 13b on the channel side and a p + type semiconductor region 13a connected to each of them. Although the p-type semiconductor region 13b and the P + type semiconductor region 13a contain the same conductivity type impurities as, for example, boron (B), etc., the impurity concentration of the p + type semiconductor region 13a is higher. It is set to be higher than the impurity concentration of the p-type semiconductor region 13b. The p-type semiconductor region 13 is electrically connected to the P-type well HPW1. The p-type semiconductor region 13 and the p-type well HPW1 are portions which form the control gate electrode CGW (the other electrode) of the capacitor portion C. As shown in FIG.

The p-type semiconductor region 13 is electrically connected to the conductor portion 7e in the contact hole CT formed in the insulating layer 6. This conductor portion 7e is electrically connected to the control gate wiring CG. The silicide layer 5a may be formed at a portion of the surface layer of the p + type semiconductor region 15b in contact with the conductor portion 7c.

Next, FIG. 14 is a sectional view of the Y2-Y2 line in FIG. 12 showing an example of the voltage applied to each part in the selected memory cells MCs in the data write operation of the flash memory of the first embodiment.

Here, a voltage of, for example, about 9V is applied to the n-type well HNW and the n-type buried well DNW through the conductor portion 7b, so that the substrate 1S and the p-type wells HPW1 to HPW3 are applied. Make electrical separation. A positive control voltage of, for example, about 9V is applied from the control gate wiring CG to the control gate electrode CGW of the capacitor C through the conductor portion 7e. Further, from the bit line WBL for data recording / erasing, through the conductor portion 7c, to one electrode (p-type semiconductor region 15 and p-type well HPW2) of the capacitor portion CWE. For example, a negative voltage of about -9V is applied. In addition, for example, 0 V is applied to the p-type well HPW3 through the conductor portion 7a.

Further, for example, 0 V is applied from the selection line GS to the gate electrode FGS of the selection MISFET QS through the conductor portion 7f. In addition, for example, 0V is applied to one n-type semiconductor region 12 of the MISFET QR for data reading from the source line SL through the conductor portion 7d. In addition, for example, 0 V is applied to one n-type semiconductor region 12 of the selected MISFET QS from the bit line RBL for data writing through the conductor portion 7g. As a result, electrons e of the p-type well HPW2 of the capacitor portion CWE for data recording / erasing of the selected memory cells MCs are transferred through the capacitor insulating film 10d by the FN tunnel current on the entire surface of the channel. It is injected into the capacitor electrode FGC1 (floating gate electrode FG) and data is recorded.

Next, FIG. 15 is a sectional view of the Y2-Y2 line in FIG. 12 which shows the voltage applied to each part in the data erasing operation of the flash memory of the first embodiment.

Here, a voltage of, for example, about 9V is applied to the n-type well HNW and the n-type buried well DNW through the conductor portion 7b, so that the substrate 1S and the p-type wells HPW1 to HPW3 are applied. Make electrical separation. In addition, a negative control voltage of, for example, about −9 V is applied from the control gate wiring CG to the control gate electrode CGW of the capacitor C through the conductor portion 7e. Further, from the bit line WBL for data recording / erasing, through the conductor portion 7c, to one electrode (the P-type semiconductor region 15 and the p-type well HPW2) of the capacitor portion CWE. For example, a positive voltage of about 9V is applied. In addition, for example, 0 V is applied to the p-type well HPW3 through the conductor portion 7a.

Further, for example, 0 V is applied from the selection line GS to the gate electrode FGS of the selection MIS-FET QS through the conductor portion 7f. In addition, for example, 0V is applied to one n-type semiconductor region 12 of the MISFET QR for data reading from the source line SL through the conductor portion 7d. In addition, for example, 0 V is applied to one n-type semiconductor region 12 of the selected MISFET QS from the bit line RBL for data writing through the conductor portion 7g. As a result, the electrons e accumulated in the capacitor electrode FGC1 (the floating gate electrode FG) of the capacitor portion CWE for data recording and erasing of the selected memory cells MCse1 and MCse2 are transferred to the FN on the front surface of the channel. The tunnel current discharges the p-type well HPW2 through the capacitor insulating film 10d and erases the data.

Next, FIG. 16 is a sectional view of the Y2-Y2 line in FIG. 12 which shows the voltage applied to each part in the data read operation of the flash memory of the first embodiment.

Here, a voltage of, for example, about 3V is applied to the n-type well HNW and the n-type buried well DNW through the conductor portion 7b, so that the substrate 1S and the p-type wells HPW1 to HPW3 are separated. Make electrical separation. A positive control voltage of, for example, about 3V is applied from the control gate wiring CG to the control gate electrode CGW of the capacitor C through the conductor portion 7e. As a result, a positive voltage is applied to the gate electrode FGR of the MISFET QR for data reading. In addition, for example, 0 V is applied to the p-type well HPW3 through the conductor portion 7a. Further, for example, 3V is applied from the selection line GS to the gate electrode FGS of the selection MISFET QS through the conductor portion 7f. In addition, for example, 0V is applied to one n-type semiconductor region 12 of the MISFET QR for data reading from the source line SL through the conductor portion 7d. Further, for example, 1 V is applied to one n-type semiconductor region 12 of the selected MIS / FET QS from the bit line RBL for data writing through the conductor portion 7g. Further, from the bit line WBL for data recording / erasing, through the conductor portion 7c, to one electrode (p-type semiconductor region 15 and P-type well HPW2) of the capacitor portion CWE. For example, a voltage of 0 V is applied. As a result, whether the drain current flows in the channel of the data read MIS FET QR with the MIS FET QR for data read of the selected memory cell MCr turned on. This reads out whether the data stored in the selected memory cell MCr is 0/1.

According to this first embodiment, the p-type data rewriting area (capacitor CWE), data read area (MISFET (QR) for data read), and capacitive coupling area (capacitor C) are individually p-type. In the wells HPW1 to HPW3, and each is separated by an n-type well HNW and an n-type buried well DNW. Data rewriting is performed by the capacitor.

This eliminates the necessity of providing the cutoff transistor in the data rewrite area of the flash memory, which can promote miniaturization of the semiconductor device.

In addition, since the element for data rewriting is formed in the capacitor element and the data is rewritten by the FN tunnel current on the entire channel, the p-type semiconductor region 15 and the p-type well HPW2 have the same potential. There is no problem of the above-mentioned junction breakdown voltage. For this reason, deterioration of the memory cell MC of a flash memory can be suppressed or prevented, and the operation reliability of a flash memory can be improved. In addition, since the timing design as described above is unnecessary, the scale of the peripheral circuit of the flash memory can be reduced to a small size, and the miniaturization of the semiconductor device can be promoted. In addition, since the data rewriting can be performed by the FN tunnel current on the entire surface of the channel which is the smallest in current consumption and suitable for rewriting a single power supply at low voltage, the single power supply by the internal boost circuit is easy. Moreover, since the channel FN tunnel current without hole generation is used for data writing and erasing, the number of times of rewriting of data can be improved.

The data rewrite area (capacitor CWE) and the data read area (MISFET QR for data read) are formed in separate p-type wells HPW2 and HPW3, respectively. It can be stabilized. For this reason, the operation reliability of a flash memory can be improved.

Embodiment 2

In the second embodiment, for example, a semiconductor device in which an LCD driver circuit (main circuit) is formed, a flash memory for storing a relatively small amount of desired information relating to the main circuit is formed. It demonstrates by FIG.

17 to 28 are cross-sectional views of principal parts of the same substrate 1S (herein, a semiconductor circular plate called a semiconductor wafer) in the manufacturing process of the semiconductor device of the second embodiment. The high breakdown voltage section and the low breakdown voltage section are regions in which MIS / FETs forming an LCD driver circuit are formed. The operating voltage of the MISFET of the high withstand voltage portion is about 25V, for example. In addition, the operating voltage of the MISFET of a low withstand voltage part is about 6.0V, for example. In addition, in the MISFET of the low withstand voltage portion, there is a MISFET having an operating voltage of 1.5V, in addition to the above operating voltage of 6.0V. The MISFET having an operating voltage of 1.5 V is provided for the purpose of operating at a higher speed than the MISFET having an operating voltage of 6.0 V, and together with other MISFETs constitutes the above LCD driver circuit. In the MISFET having an operating voltage of 1.5 V, the gate insulating film is thinner than the gate insulating film of the MISFET having an operating voltage of 6.0 V, and the film thickness thereof is configured to be about 1 to 3 nm. In the following drawings and the specification, for the sake of simplicity, mainly the MISFET of the high breakdown voltage portion having an operating voltage of 25V and the MISFET of the low breakdown portion having an operating voltage of 6.0V are shown, and the operating voltage is 1.5V. MIS / FET is not shown. In addition, also in the semiconductor device (semiconductor chip, board | substrate 1S) of this Embodiment 2, the power supply supplied from the outside is set as a single power supply.

First, as shown in Figs. 17 and 18, a p-type substrate 1S (semiconductor wafer) is prepared, and the p-type buried well DPW is subjected to photolithography (hereinafter, simply referred to as lithography) in the high withstand voltage portion. It is formed by a process and an ion implantation process. A lithography process is a series of processes of forming a desired resist pattern by application | coating, exposure, image development, etc. of a photoresist (hereinafter simply called a resist) film. In the ion implantation process, a desired impurity is selectively introduced into a desired portion of the substrate 1S by using a resist pattern formed on the main surface of the substrate 1S through a lithography process as a mask. The resist pattern herein is a pattern in which an impurity introduction region is exposed and other regions are covered.

Subsequently, n-type buried wells DNW are simultaneously formed in the high breakdown portion, the low breakdown portion, and the memory cell forming regions of the flash memory by a lithography process, an ion implantation process, and the like. Thereafter, a separation groove is formed in the separation region of the main surface of the substrate 1S, and then an insulating film is embedded in the separation sphere to form a spherical separation portion TI. This defines the active area.

19 and 20, an n-type semiconductor region NV is formed in the n-channel MIS-FET formation region of the high breakdown voltage portion by a lithography process, an ion implantation process, or the like. The n-type semiconductor region NV is a region having a higher impurity concentration than the n-type buried well DNW. Subsequently, a P-type semiconductor region PV is formed in the p-channel MIS-FET formation region of the high withstand voltage portion by a lithography process, an ion implantation process, or the like. The p-type semiconductor region PV is a region having a higher impurity concentration than the p-type buried well DPW.

Subsequently, the p-type well PW is formed in the n-channel MIS-FET formation region of the low breakdown voltage portion by a lithography process, an ion implantation process, or the like. The p-type well PW is a region having a higher impurity concentration than the p-type buried well DPW and a region having a higher impurity concentration than the p-type semiconductor region PV. Subsequently, an n-type well NW is formed in the p-channel MIS-FET formation region of the low breakdown voltage portion by a lithography process, an ion implantation process, or the like. The n-type well NW is a region having a higher impurity concentration than the n-type buried well DNW and a region having a higher impurity concentration than the n-type semiconductor region NV.

Subsequently, p-type wells HPW1 to HPW3 are simultaneously formed in the memory cell formation region of the flash memory by a lithography process, an ion implantation process, and the like. The p-type wells HPW1 to HPW3 are regions having an impurity concentration higher than that of the p-type buried well DPW, and are regions having an impurity concentration equivalent to that of the p-type semiconductor region PV.

The n-type buried well (DNW), p-type buried well (DPW), n-type semiconductor region (NV), p-type semiconductor region (PV), n-type well (NW), p-type The magnitude relationship between the impurity concentrations of the well PW and the p-type wells HPW1 to HPW3 is the same in the embodiments described later.

After that, the gate insulating films 10b, 10e, 10f, and 10g and the capacitor insulating films 10c and 10d are formed by thermal oxidation or the like, and then, for example, low-resistance polycrystalline silicon on the main surface of the substrate 1S (semiconductor wafer). The conductive film 20 composed of the above is formed by CVD (Chemical Vapor Deposition) method or the like. At this time, the gate insulating film 10f of the MISFET of the high withstand voltage portion is formed of a gate insulating film having a thickness greater than that of the gate insulating film 10g of the MISFET of the low breakdown voltage portion. The thickness of the gate insulating film 10f of the high breakdown voltage MISFET is, for example, 50 to 100 nm. In addition to the oxide film by the above thermal oxidation method, an insulating film deposited by the CVD method or the like may be laminated.

In the present embodiment, the gate insulating films 10b and 10e and the capacitor insulating films 10c and 10d of the nonvolatile memory are formed of MISFETs (here, MISFETs having an operating voltage of, for example, 6.0 V) in the low withstand voltage. The thickness of the gate insulating films 10b and 10e and the capacitor insulating films 10c and 10d of the nonvolatile memory is formed by the same process as the gate insulating film 10g. It is formed at the same thickness as. For the same reasons as the insulating film 10a and the like of the first embodiment, the film thicknesses of the gate insulating films 10b, 10e and 10g and the capacitor insulating films 10c and 10d are preferably 10 nm or more and 20 nm or less, for example, 13.5 nm. Is formed.

Next, as shown in Figs. 21 and 22, the above-described conductor film 20 is patterned by a lithography process and an etching process, whereby the gate electrodes FGH, FGL, FGS and floating gates FG (gate electrodes ( FGR)) and the capacitor electrodes FGC1 and FGC2 are formed simultaneously. Subsequently, the p-type semiconductor region 21a, in the p-channel MIS-FET formation region of the high breakdown voltage section, the formation region of the capacitor portion C, and the formation region of the capacitor portion CWE for data recording / erasing is formed. 13b and 15a are simultaneously formed by a lithography process, an ion implantation method, or the like. Subsequently, the n-type semiconductor region 22a is formed in the n-channel type MISFET formation region of the high withstand voltage portion, the formation region of the MISFET (QR) for reading data, and the formation region of the selected MISFET (QS). , 12a) are simultaneously formed by a lithography process, an ion implantation method, or the like.

Subsequently, the p-type semiconductor region 23a is formed in the p-channel MIS-FET formation region of the low withstand voltage portion by a lithography process, an ion implantation method, or the like. Subsequently, the n-type semiconductor region 24a is formed in the n-channel MIS-FET formation region of the low breakdown voltage portion by a lithography process, an ion implantation method, or the like.

Next, as shown in FIGS. 23 and 24, an insulating film made of, for example, silicon oxide is deposited on the main surface of the substrate 1S (semiconductor wafer) by CVD or the like, and then etched back by anisotropic dry etching. As a result, sidewalls SW are formed on the side surfaces of the gate electrodes FGH, FGL, FGR, and FGS and the capacitor electrodes FGC1 and FGC2.

Subsequently, p + type semiconductors are formed in the p-channel MIS / FET formation region of the high withstand voltage portion and the low withstand voltage portion, the capacitor portion and the recording / erasing capacitance portion formation region, and the lead-out region of the p-type well HPW3. Regions 21b, 23b, 13a, 15b, and 4a are simultaneously formed by a lithography process, an ion implantation method, or the like. As a result, the p-type semiconductor region 21 for the source and the drain is formed in the high breakdown voltage portion, and the p-channel MISFET QPH is formed. Further, the p-type semiconductor region 23 for the source and the drain is formed in the low breakdown voltage portion, and the p-channel MISFET (QPL) is formed. In addition, the p-type semiconductor region 13 is formed in the capacitor portion forming region, and the capacitor portion C is formed. Further, the p-type semiconductor region 15 is formed in the recording / erasing capacitor portion forming region, and the capacitor portion CWE for data recording / erasing is formed.

Subsequently, n + type semiconductor regions 22b, 24b, 12b are simultaneously formed in the n-channel MISFET formation region of the high breakdown portion, the low breakdown portion, the read portion, and the select portion by a lithography process, an ion implantation method, or the like. . As a result, the n-type semiconductor region 22 for the source and the drain is formed in the high breakdown voltage portion, and an n-channel MISFET (QNH) is formed. Further, the n-type semiconductor region 24 for the source and the drain is formed in the low breakdown voltage portion, and the n-channel MIS FET QNL is formed. In addition, the n-type semiconductor region 12 is formed in the reading section and the selection section, and the MIS FET QR and the selection MIS FET QS for data reading are formed.

Next, as shown in FIG. 25 and FIG. 26, the silicide layer 5a is selectively formed. Prior to the formation process of the silicide layer 5a, in the region of the memory cell MC, the floating gate electrodes FG (capacitive electrodes FGC1 and FGC2, gate electrodes FGR) and gate electrodes FGS are formed. The cap insulating film 28 is formed on the upper surface, and the insulating film is formed on a part of the substrate 1S so that the silicide layer 5a is not formed thereon. Subsequently, as shown in FIG. 27 and FIG. 28, after the insulating layer 6a made of, for example, silicon nitride is deposited on the main surface of the substrate 1S (semiconductor wafer), for example, thereon, for example, The insulating layer 6b made of silicon oxide is deposited thicker than the insulating layer 6a by the CVD method or the like, and further, the chemical mechanical polishing (CMP) treatment is applied to the insulating layer 6b to insulate the insulating layer 6b. Planarize the top surface of. Thereafter, contact holes CT are formed in the insulating layer 6 by a lithography process and an etching process. Thereafter, a conductor film made of, for example, tungsten (W) or the like is deposited on the main surface of the substrate 1S (semiconductor wafer) by CVD or the like, and then polished by the CMP method or the like to form the conductor portion in the contact hole CT. (7a, 7c-7k) are formed. After that, the semiconductor device is manufactured through a normal wiring forming step, an inspection step, and an assembling step.

According to the second embodiment, the components of the MISFETs QPH, QNH, QPL and QNL for the LCD driver circuit, the capacitors C and CWE of the memory cell MC and the MISFETs QR and QS Can be formed at the same time, thereby simplifying the manufacturing process of the semiconductor device. This can shorten the manufacturing time of the semiconductor device. In addition, the cost of the semiconductor device can be reduced.

The external single power supply voltage (e.g., 3.3V) of the semiconductor device is used by the negative voltage boosting circuit (internal boosting circuit) for the LCD driver circuit to be used for data writing of the memory cell MC (e.g., -9V). Can be converted to In addition, an external single power supply voltage (e.g., 3.3V) can be converted into a voltage (e.g., 9V) used for erasing data of the memory cell MC by a constant voltage boosting circuit (internal boosting circuit) for the LCD driver circuit. . That is, there is no need to newly install an internal boost circuit for the flash memory. For this reason, since the circuit size inside a semiconductor device can be suppressed small, miniaturization of a semiconductor device can be promoted.

Embodiment 3

FIG. 29 is a sectional view of the main part of the LCD driver circuit (main circuit) area of the semiconductor device of the third embodiment, and FIG. 30 is a sectional view of the main part of the flash memory area formed on the substrate 1S as shown in FIG.

In the third embodiment, as illustrated in FIGS. 29 and 30, the p-type well PW is formed in the P-type wells HPW1, HPW2 of the capacitors C, CWE. As a result, the concentration of the p-type impurity in the portion of the substrate 1S immediately below the capacitor electrodes FGC1 and FGC2 increases, so that the data of the capacitor electrodes FGC1 and FGC2 at the time of data rewriting (writing and erasing) is increased. Depletion of the underlying substrate 1S portion can be suppressed or prevented. For this reason, the voltage applied to the capacitor insulating films 10c and 10d can be made high, so that the data rewriting speed can be increased. Fig. 31 shows recording / erasing characteristics of data. Solid lines A1 and B1 denote recording characteristics and erasures of the third embodiment, respectively, and solid lines A0 and B0 denote recording characteristics and erasures when no p-type well PW is formed in the p-type wells HPW1 and HPW2, respectively. The characteristics are shown. In the third embodiment, it can be seen that the data recording and erasing time can be shortened.

The p-type well PW in the p-type wells HPW1l and HPW2 in the flash memory area is the p-type of the n-channel type MISFET QNL in the low breakdown portion of the LCD driver circuit area. Is formed at the same time as forming the well PW. That is, after forming a resist pattern so that the flash memory region and the region of the p-type well PW of the low withstand voltage portion are exposed and other regions are applied, the resist pattern is masked and the p-type impurity It is formed by introducing into 1S). As a result, when the p-type well PW is formed in the p-type wells HPW1 and HPW2, the manufacturing process does not increase. The other manufacturing process is the same as that of the said 2nd Embodiment. In addition, since the effect of that excepting the above is the same as that of the said Embodiment 1, 2, description is abbreviate | omitted.

Embodiment 4

Fig. 32 is a sectional view of the main part of the LCD driver circuit (main circuit) area of the semiconductor device of the fourth embodiment, and Fig. 33 is a sectional view of the main part of the flash memory area formed on the substrate 1S as shown in Fig. 32.

In the fourth embodiment, as shown in Figs. 32 and 33, the wells of the capacitors C and CWE are wells of the formation region of the n-channel MISFET QNL of the low breakdown voltage portion of the LCD driver circuit region. It is formed by the p-type well PW. The p-type impurity concentration of the p-type well PW is set higher than the p-type impurity concentration of the p-type well HPW3. As a result, the concentration of the p-type impurity in the portion of the substrate 1S immediately below the capacitor electrodes FGC1 and FGC2 of the capacitors C and CWE increases, so that at the time of data rewriting (writing and erasing), Depletion of the portion of the substrate 1S immediately below the electrodes FGC1 and FGC2 can be suppressed or prevented. For this reason, the voltage applied to the capacitor insulating films 10c and 10d can be made high, so that the data rewriting speed can be increased.

The p-type well PW in the flash memory area is the p-type well in the formation region of the n-channel type MISFET QNL in the low breakdown voltage portion of the LCD driver circuit area as in the third embodiment. PW) is formed at the same time. As a result, when the p-type well PW is formed in the memory cell MC, the manufacturing process does not increase.

The other manufacturing process is the same as that of the said 2nd Embodiment. In addition, since the effect of that excepting the above is the same as that of the said Embodiment 1, 2, description is abbreviate | omitted.

Embodiment 5

Fig. 34 is a sectional view of the main part of the LCD driver circuit (main circuit) area of the semiconductor device of the fifth embodiment, and Fig. 35 is a sectional view of the main part of the flash memory area formed on the substrate 1S as shown in Fig. 34.

In the fifth embodiment, as shown in Figs. 34 and 35, the wells of the capacitors C and CWE, the MIS FET QR for reading data and the selected MIS FET QS have an LCD driver circuit area. Is formed by the p-type semiconductor region PV of the p-channel MISFET QPH of the high withstand voltage portion of the transistor. The p-type semiconductor region PV forming the wells of the capacitors C and CWE, the MISFET QR for reading data, and the selected MISFET QS is provided in the high voltage resistance section of the LCD driver circuit region. It is formed simultaneously when forming the p-type semiconductor region PV of the p-channel MISFET QPH. That is, after forming a resist pattern so that the flash memory region and the region of formation of the p-type semiconductor region PV of the high withstand voltage region are exposed and the other regions are applied, the resist pattern is masked and the p-type impurity substrate is formed. It is formed by introducing into (1S). This reduces the lithography process (a process of manufacturing a photomask to be used during exposure and a series of processes such as resist coating, exposure and development) for forming the p-type wells HPW1 to HPW3 of the flash memory. Therefore, the manufacturing time of the semiconductor device can be shortened. In addition, the manufacturing cost of the semiconductor device can be reduced.

The other manufacturing process is the same as that of the said 2nd Embodiment. In addition, since the effect of that excepting the above is the same as that of the said Embodiment 1, 2, description is abbreviate | omitted.

Embodiment 6

Fig. 36 is a sectional view of the main part of the LCD driver circuit (main circuit) area of the semiconductor device of the sixth embodiment, and Fig. 37 is a sectional view of the main part of the flash memory area formed on the substrate 1S as shown in Fig. 36.

In the sixth embodiment, as shown in Figs. 36 and 37, the wells of the capacitors C and CWE, the MISFET QR for reading data and the selected MISFET QS are formed in the LCD driver circuit area. Is formed by the p-type semiconductor region PV of the p-channel MISFET QPH of the high withstand voltage portion of the transistor. The p-type semiconductor region PV forming the wells of the capacitors C and CWE, the MISFET QR for data reading, and the selected MISFET QS is the same as that of the fifth embodiment. It is formed simultaneously when the p-type semiconductor region PV of the p-channel MIS / FET QPH of the high breakdown voltage portion of the driver circuit region is formed. As a result, the lithography process for forming the p-type wells HPW1 to HPW3 of the flash memory can be reduced as in the fifth embodiment, so that the manufacturing time of the semiconductor device can be shortened.

In addition, the manufacturing cost of the semiconductor device can be reduced.

Further, the p-type well PW is formed in the p-type semiconductor region PV forming the wells of the capacitors C and CWE. As a result, the concentration of the p-type impurity in the portion of the substrate 1S immediately below the capacitor electrodes FGC1 and FGC2 of the capacitors C and CWE increases, and therefore, at the time of data rewriting (writing and erasing), Depletion of the portion of the substrate 1S immediately below the capacitor electrodes FGC1 and FGC2 can be suppressed or prevented. For this reason, the voltage applied to the capacitor insulating films 10c and 10d can be made high, so that the data rewriting speed can be increased.

The p-type well PW in the p-type semiconductor region PV of the capacitor portions C and CWE of the memory region is the n-channel type of the low breakdown portion of the LCD driver circuit region as in the third embodiment. It is formed simultaneously when the p-type well PW in the formation region of the MIS-FET QNL is formed.

As a result, when the p-type well PW is formed in the p-type semiconductor region PV forming the wells of the capacitors C and CWE, the manufacturing process does not increase. Other manufacturing processes are the same as those of the second embodiment. In addition, since the effect of that excepting the above is the same as that of the said Embodiment 1, 2, description is abbreviate | omitted.

Embodiment 7

FIG. 38 is a sectional view of the main part of the LCD driver circuit (main circuit) area of the semiconductor device of the seventh embodiment, and FIG. 39 is a sectional view of the main part of the flash memory area formed on the substrate 1S as shown in FIG.

In the seventh embodiment, as shown in Figs. 38 and 39, the wells of the capacitors C and CWE are wells of the formation region of the n-channel MISFET QNL of the low breakdown voltage portion of the LCD driver circuit region. It is formed by the p-type well PW. The p-type impurity concentration of the p-type well PW is set higher than the p-type impurity concentration of the p-type wells HPW1 to HPW3. As a result, the concentration of the p-type impurity in the portion of the substrate 1S immediately below the capacitor electrodes FGC1 and FGC2 of the capacitors C and CWE increases, so that at the time of data rewriting (writing and erasing), Depletion of the portion of the substrate 1S immediately below the electrodes FGC1 and FGC2 can be suppressed or prevented. For this reason, the voltage applied to the capacitor insulating films 10c and 10d can be made high, so that the data rewriting speed can be increased.

The p-type well PW in the flash memory area is the p-type well in the formation region of the n-channel type MISFET QNL in the low breakdown voltage portion of the LCD driver circuit area as in the third embodiment. PW) is formed at the same time. As a result, when the p-type well PW is formed in the memory cell MC, the manufacturing process does not increase.

In the seventh embodiment, the wells of the MISFET (QR) and the selected MISFET (QS) for data reading are the P of the p-channel type MISFET (QPH) of the high breakdown voltage portion of the LCD driver circuit area. It is formed by the semiconductor region PV of a type | mold. The p-type semiconductor region PV forming the wells of the MIS FET QR and the selected MIS FET QS for data reading is, as in the fifth embodiment, p of the high breakdown portion of the LCD driver circuit region. It is formed simultaneously when forming the p-type semiconductor region (PV) of the channel-type MIS-FET (QPH). That is, in the seventh embodiment, as in the fifth embodiment, the lithography process for forming the p-type wells HPW1 to HPW3 of the flash memory can be reduced, so that the manufacturing time of the semiconductor device can be shortened. . In addition, the manufacturing cost of the semiconductor device can be reduced.

Other manufacturing processes are the same as those of the second embodiment. In addition, since the effect of that excepting the above is the same as that of the said Embodiment 1, 2, description is abbreviate | omitted.

Embodiment 8

40 is a plan view of principal parts of a flash memory formation region of the semiconductor device according to the eighth embodiment. Since the cross-sectional structure of the semiconductor device of the eighth embodiment is the same as that shown in the first to seventh embodiments, illustration and description are omitted.

In the eighth embodiment, in the flash memory area of the main surface (first main surface) of the substrate 1S constituting the semiconductor chip, for example, a plurality of the memory cells MC having an 8 × 2 bit configuration are arranged in an array shape (matrix shape). Are arranged side by side regularly.

The p-type wells HPW1 to HPW2 extend in the second direction X and are formed. In the p-type well HPW1, the capacitor portion C for a plurality of bits is disposed. Further, in the p-type well HPW2, a capacitor portion CWE for data recording / erasing for a plurality of bits is disposed.

In the p-type well HPW3, a plurality of bits of the MISFET (QR) and the selected MISFET (QS) for data reading are arranged.

By configuring such an array configuration, the area occupied by the flash memory can be reduced, so that the added value of the semiconductor device can be improved without causing an increase in the size of the semiconductor chip on which the main circuit is formed.

Embodiment 9

In the ninth embodiment, the selected MISFET of the memory cell of the flash memory is, for example, a MISFET having a relatively low breakdown voltage of 1.2V (or 1.5V) of an LCD driver circuit (main circuit). , Which is also referred to as a 1.2V MISFET).

In the above embodiment, the selection MIS FET QS of the memory cell MC of the flash memory preferentially manufactures easily, and the operating voltage of 6 V is the same as that of the MIS FET QR for data reading. It is formed by a MISFET (hereinafter also referred to as a 6V MISFET).

However, in the configuration of the flash memory of this embodiment, the drain voltage applied to the data read MIS FET (QR) of the memory cell MC is, for example, about -1.0V. That is, only about 1.0 V is applied to the drain of the selection MIS FET QS for data reading, for example. Further, the gate electrode of the selected MIS FET QS is not connected to the floating gate electrode FG of the memory cell MC, and there is no influence on the charge holding ability.

41 and 42 show the selection of the MISFET QS2 for data reading, as shown in FIG. 41 and FIG. 42, for example, in the above 1.2V system of the LCD driver circuit. It was formed by MISFET.

41 is a plan view of an example of a memory cell MC of a flash memory in the semiconductor device of the ninth embodiment, and FIG. 42 is a cross-sectional view taken along the line Y3-Y3 in FIG. 41. In addition, in FIG. 41, a part is hatched to make the drawing easier to see.

The p type well PW2 is formed in the selection portion of the substrate 1S. The P type well PW2 of the selection portion is surrounded by the p type well HPW3 of the memory cell MC. That is, the p type well PW2 is contained in the p type well HPW3.

The p-type well PW2 of this selector is the same as the p-type well of the arrangement area of the 1.2V-type MISFET of the LCD driver circuit. That is, the p-type well PW2 of the selector is formed by introducing boron of p-type impurity at the same process as the p-type well for the 1.2V-based MIS / FET of the LCD driver circuit. The impurity concentration of the well PW2 of the type is equal to the impurity concentration of the p type well for the MIS / FET of 1.2V system of the LCD driver circuit.

In this P-type well PW2, an n-type semiconductor region 12c constituting a pair of n-type semiconductor regions 12 and 12 for source and drain of the selected MISFET QS2 is formed. Is formed. The n-type semiconductor region 12c is disposed on both sides of the channel formation region by sandwiching the channel formation region of the selected MISFET QS2, and is electrically connected to the n + type semiconductor region 12b. The n-type semiconductor region 12c and the n + type semiconductor region 12b contain the same conductivity type impurities such as phosphorus (P) or arsenic (As), for example, but the n + type semiconductor region 12b Impurity concentration is higher than that of the n-type semiconductor region 12c.

In the ninth embodiment, the configuration of the n-type semiconductor region 12c of the selected MISFET QS2 is a pair of semiconductors for the source and drain of the 1.2V system MISFET of the LCD driver circuit. It is the same as the structure of the n-type semiconductor region which comprises a region. That is, the n-type semiconductor region 12c of the selected MIS / FET (QS2) has n-type impurities in the same process as the n-type semiconductor region of the 1.2V-based MIS / FET of the LCD driver circuit. It is formed to be introduced, and the impurity concentration of the n-type semiconductor region 12c is equal to the impurity concentration of the n-type semiconductor region for the MIS / FET of 1.2V system of the LCD driver circuit.

On the main surface (channel formation region) of the substrate 1S on which the p-type well PW2 is formed, a gate insulating film 10h of the selected MISFET QS2 is formed. The structure of the gate insulating film 10h of the selected MISFET QS2 is the same as the structure of the gate insulating film of the 1.2V MISFET of the LCD driver circuit. In other words, the gate insulating film 10h of the selected MIS-FET QS2 is formed of, for example, silicon oxide. The gate insulating film 10h of the selected MISFET QS2 is formed at the same process as the gate insulating film of the 1.2V MISFET of the LCD driver circuit. For this reason, the thickness of the gate insulating film 10h of the selected MIS / FET QS2 is equal to the thickness of the gate insulating film of the 1.2 V-type MIS / FET of the LCD driver circuit. However, the thickness of the gate insulating film 10h of the selected MISFET QS2 is determined by two gate processes, and the gate insulating film 10e of the selected MISFET QS and the MISFET for data reading ( It is formed thinner than the gate insulating film 10b of QR.

The two kinds of gate processes have the following steps, for example. First, the 1st thermal oxidation process is performed with respect to the board | substrate 1S, and the 1st gate insulating film of predetermined thickness is simultaneously formed on the main surface of both the thickness film part and the thin film part of the board | substrate 1S. Subsequently, only the first gate insulating film of the thin film portion is selectively removed. Thereafter, the second thermal oxidation treatment or the like is performed on the substrate 1S while leaving the first gate insulating film in the thick film portion. In this second thermal oxidation treatment, the oxidation treatment is performed so that the thickness of the gate insulating film formed in the thin film portion becomes a desired thickness. As a result, a relatively thin gate insulating film is formed in the thin film portion, and a relatively thick gate insulating film is formed in the thick film portion.

On this gate insulating film 10h, the gate electrode FGS2 of the selected MIS-FET QS2 is formed. The structure of the gate electrode FGS2 of the selected MISFET QS2 is the same as that of the gate electrode of the MISFET of the 1.2V system of the LCD driver circuit. In other words, the gate electrode FGS2 of the selected MISFET QS2 is formed of, for example, n + type polycrystalline silicon of low resistance. The gate electrode FGS2 of the selected MISFET QS2 is formed at the same process as the gate electrode of the 1.2V MISFET of the LCD driver circuit. The gate length (the length in one direction of the gate electrode FGS2 and the length in the direction in which the drain current flows) Lg of the gate electrode FGS2 of the selected MISFET QS2 is 1.2V in the LCD driver circuit. The gate length Lg (minimum dimension) of the MISFET of the system is smaller than the gate length of the selected MISFET QS or the gate length of the MISFET QR for data reading.

In the ninth embodiment, the floating gate electrode FG (i.e., the capacitor electrode FGC),

The cap insulating film 28b is formed so as to cover the upper surface of the gate electrodes FGW and FGR, the entire surface of the side wall SW, and a part of the main surface of the substrate 1S of the outer circumference.

The cap insulating film 28b is made of, for example, silicon oxide, and is insulated from the top surface of the floating gate electrode FG so that the insulating layer 6a made of silicon nitride does not directly contact the top surface of the floating gate electrode FG. It is formed between the layers 6b. This is because of the following reasons. That is, when the insulating layer 6a made of silicon nitride is deposited by the plasma chemical vapor deposition (CVD) method, the insulating layer 6a becomes a silicon rich film in the initial stage of deposition. easy. For this reason, when the insulating layer 6a is formed in the state which directly contacted the upper surface of the floating gate electrode FG, the electric charge in the floating gate electrode FG will pass through the board | substrate 1S through the part which is the silicon rich of the insulating layer 6a. May flow to the side and may be released through the plug. As a result, the data retention characteristics of the flash memory are deteriorated, so that such defects are suppressed or prevented.

The cap insulating film 28b is also formed on a resistance element (not shown) provided in another region of the semiconductor substrate 1S. This resistive element can be formed, for example, in the same process as the above-described capacitor electrode FGC and gate electrodes FGW, FGR, FGS, FGS2 and the like, and is made of a polycrystalline silicon film. By providing the cap insulation film 28b on such a resistance element, a region in which the silicide layer 5a is formed and a region in which the silicide layer 5a is formed on the resistance element can be selectively divided, whereby the resistance element having a desired resistance value is formed. Can be formed.

That is, in this embodiment, the cap insulating film 28b is used to form an insulating film for dividing the silicide layer 5a on the resistance element and an insulating film provided between the insulating layer 6a on the floating gate electrode FG. Is formed in the same process. Thereby, it is not necessary to form each insulating film in a separate process, and the manufacturing process can be simplified.

In the ninth embodiment, since the cap insulating film 28b is formed between the upper surface of the floating gate electrode FG and the insulating layer 6b, the discharge of the above charges can be suppressed or prevented. Can improve the data retention characteristics.

The silicide layer 5a is formed after the cap insulating film 28b is patterned. For this reason, although the silicide layer 5a is formed on the main surface (p + type semiconductor regions 13a and 15b and n + type semiconductor region 12b) of the substrate 1S, the top surface of the floating gate electrode FG is formed. Is not formed.

Thus, in this Embodiment 9, the following effects can be acquired in addition to the effect obtained by the said embodiment.

In other words, the gate length of the selection MISFET QS2 is smaller than the gate length of the selection MISFET QS, and the film thickness of the gate insulating film 10h is the gate of the selection MISFET QS. Thinner than the insulating film 10e, a larger current (drain current Ids) can be obtained when driven at the same voltage. For this reason, since the data read current can be increased, the circuit margin can be expanded.

In addition, since the occupied area of the selected MIS / FET QS2 can be made small, the occupied area of the flash memory can be made small. In particular, when the plurality of memory cells MC are arranged in an array, the area occupied by the flash memory can be reduced.

Embodiment 10

In the tenth embodiment, a configuration for suppressing or preventing the depletion layer from being formed on the substrate 1S during erasing or writing data in the flash memory will be described.

43 is a plan view showing one example of the memory cells MC of the flash memory in the semiconductor device of Embodiment 10, and FIG. 44 is a cross-sectional view taken along the Y4-Y4 line in FIG. In addition, in FIG. 43, hatching is attached to a part in order to make the drawing easy to see.

In the tenth embodiment, a conductive semiconductor region different from the p-type semiconductor region 15 and the n-type semiconductor region 30 is formed in the capacitor portion CWE for data recording and erasing. In the capacitor portion CWE for data recording and erasing, the conductive type of the semiconductor regions on the left and right sides of the capacitor electrode FGC1 is asymmetric.

The n-type semiconductor region 30 includes an n-type semiconductor region 30a and an n + type semiconductor region 30b electrically connected to each other. The n-type semiconductor region 30a is postponed by the width of the sidewall SW along the main surface of the substrate 1S near one end of the capacitor electrode FGC1. The n + type semiconductor region 30b partially overlaps at the end of the n-type semiconductor region 30a, and is deferred from the overlapped position by a desired length along the main surface of the substrate 1S and separated by the separation unit TI. Terminated.

The n-type semiconductor region 30a and the n + type semiconductor region 30b contain the same conductivity type impurities as, for example, phosphorus (P) or arsenic (As), but the n + type semiconductor region 30b. Impurity concentration is higher than that of the n-type semiconductor region 30a.

In the tenth embodiment, the n-type semiconductor region 30 is formed between adjacent two floating gate electrodes FG adjacent to each other, as shown in FIG. In other words, the n-type semiconductor region 30 becomes a shared region of the capacitive units CWE for two data recording and erasing operations.

In the tenth embodiment, in the capacitor portion C, another conductive semiconductor region of the p-type semiconductor region 13 and the n-type semiconductor region 31 is formed. That is, in the capacitor portion C, the conductivity type of the semiconductor regions on the left and right sides of the capacitor electrode FGC2 is asymmetric.

The n-type semiconductor region 31 includes an n-type semiconductor region 31a and an n + type semiconductor region 31b electrically connected to each other. The n-type semiconductor region 31a is postponed by the width of the sidewall SW along the main surface of the substrate 1S near one end of the capacitor electrode FGC2 and terminated. The n + type semiconductor region 31b partially overlaps at the end of the n-type semiconductor region 31a, and extends from the overlapped position by a desired length along the main surface of the substrate 1S to the separation portion TI. Terminated.

The n-type semiconductor region 31a and the n + type semiconductor region 31b contain the same conductivity type impurities as, for example, phosphorus (P) or arsenic (As), but the n + type semiconductor region 31b. Impurity concentration is higher than that of the n-type semiconductor region 31a.

In the tenth embodiment, the n-type semiconductor region 31 is formed between adjacent two floating gate electrodes FG adjacent to each other, as shown in FIG. In other words, the n-type semiconductor region 31 becomes a shared region of the two capacitor portions C. FIG.

The n-type semiconductor regions 30a and 31a are simultaneously used during the formation process of the n-type semiconductor region 12a of the MISFET QR and the selected MISFET QS for data reading. Is formed. The n + type semiconductor regions 30b and 31b are simultaneously used in the formation process of the n + type semiconductor region 12b of the MISFET QR and the selected MISFET QS for data reading. Is formed.

Next, the reason for such a configuration will be described with reference to FIGS. 45 to 48. 45 to 48, reference numeral 35 denotes an inversion layer, reference numeral 36 denotes a depletion layer, and e- denotes an electron.

First, the charge injection discharge portion will be described. 45 is a cross-sectional view taken along the second direction X of the substrate 1S of the charge injection and ejection portion of the memory cell MC of the above embodiment. For data recording, a negative voltage of, for example, about -9V is applied to the p-type well HPW2 of the charge injection discharge portion. For this reason, the depletion layer 36 is formed directly under the capacitor insulating film 10d. As a result, the coupling capacity decreases. In addition, it is thought that the electrons to be injected are also depleted and the injection efficiency is lowered. Thus, the data writing speed is lowered. In addition, the data writing speed becomes uneven.

46 is a sectional view taken along the second direction X of the substrate 1S of the charge injection and ejection portion of the memory cell MC of the tenth embodiment. As described above, the formation of the inversion layer 35 is promoted by adding the n + type semiconductor region 30b. In addition, electrons are a small number of careers in an n-type semiconductor, while a small number of careers are used in a p-type semiconductor. For this reason, by providing the n + type semiconductor region 30b, the injected electrons can be easily supplied to the inversion layer 35 directly under the capacitor electrode FGC1. As a result, the effective coupling capacitance can be increased, so that the potential of the capacitor electrode FGC1 (the floating gate electrode FG) can be efficiently controlled. Therefore, the recording speed of data can be improved. In addition, the nonuniformity of the data recording speed can be reduced.

Next, the capacitive portion will be described. Fig. 47 is a sectional view taken along the second direction X of the substrate 1S of the capacitor portion of the memory cell MC of the above embodiment. For data erasing, since a negative voltage of, for example, about -9 V is applied to the p-type well HPW1 of the capacitor portion, a depletion layer 36 is formed directly under the capacitor insulating film 10c. As a result, the actual coupling capacity is lowered, and the time for erasing data is delayed. In addition, the erase speed of data becomes uneven.

48 is a sectional view taken along the second direction X of the substrate 1S of the capacitor portion of the memory cell MC of the tenth embodiment. By adding the n + type semiconductor region 31b as described above, it is possible to smoothly supply electrons directly under the capacitor insulating film 10c. For this reason, since the inversion layer 35 can be formed quickly, the p type well HPW1 can be quickly fixed to -9V. As a result, the effective coupling capacitance can be increased, so that the potential of the capacitor electrode FGC2 (the floating gate electrode FG) can be efficiently controlled. Therefore, the data erasing speed can be improved. In addition, the nonuniformity of the data erasing speed can be reduced.

As described above, according to the tenth embodiment, the charge injection discharge portion and the capacitor portion are provided with both the p + type semiconductor regions 15b and 13b and the n + type semiconductor regions 30b and 31b. In this case, the n + type semiconductor region 30b acts as a source of electrons at the time of charge injection, and in the capacitive portion, the n + type semiconductor region 31b acts as a source of electrons to the inversion layer. And the erase speed can be improved.

Here, FIG. 49 compares and shows the data recording / erasing characteristics in the case of the tenth embodiment and the case of the embodiment. 50 shows the data recording characteristics by extracting them, and FIG. 51 shows the data erasing characteristics by extracting them.

Solid lines A2 and B2 show the data recording and data erasing characteristics of the tenth embodiment, respectively, and solid lines A01 and B01 do not form n + type semiconductor regions 30b and 31b, and P + type semiconductor regions 15b and 13b. ), Data recording characteristics and data erasing characteristics are shown.

In the case of the tenth embodiment, the data recording time can be shortened by about 1.5 digits. In addition, the data erase time can be shortened by about two digits.

In the above description, the case where both the p + type semiconductor regions 15b and 13b and the n + type semiconductor regions 30b and 31b are provided in both the charge injection discharge portion and the capacitor portion is limited to this. It doesn't happen.

For example, in the case of speeding up only erasing of data, the capacitor section includes the p-type semiconductor region 13 (P + -type semiconductor region 13b) and the n-type semiconductor region 31 (n + -type semiconductor region 31b). Both may be provided, and only the p-type semiconductor region 15 (p + -type semiconductor region 15b) may be provided in the charge injection discharge portion.

In addition, when only writing data is accelerated, the p-type semiconductor region 15 (p + -type semiconductor region 15b) and the n-type semiconductor region 30 (n + -type semiconductor region 30b) are provided in the charge injection emission section. May be provided, and only the p-type semiconductor region 13 (p + -type semiconductor region 13b) may be provided in the capacitor portion.

In addition, you may combine the structure demonstrated by Embodiment 10 and the structure demonstrated by Embodiment 3 about the viewpoint which suppresses or prevents depletion of the board | substrate 1S. That is, in the tenth embodiment, the P-type well PW may be provided in the p-type wells HPW1 and HPW2 of the capacitors C and CWE.

Next, an example of a method of forming the n-type semiconductor regions 30 and 31 will be described with reference to FIGS. 52 to 54.

Fig. 52 shows a mask when the n-type semiconductor regions 30 and 31 and the p-type semiconductor regions 13 and 15 are formed in the memory cell MC in the flash memory of the semiconductor device of the tenth embodiment. The top view of the memory cell MC shown is shown.

The openings NA and NB shown in FIG. 52 are the first deposited on the main surface of the substrate 1S (a planar circular semiconductor thin plate called a wafer in this step) in the manufacturing process of the semiconductor device of the tenth embodiment. It is a planar square opening formed in the resist film (mask). The openings NA and NB serve as introduction regions of n-type impurities for forming the n-type semiconductor regions 30 and 31, respectively.

Further, the two openings PA and the two openings PB are deposited on the main surface of the substrate 1S (the wafer in this step) during the manufacturing process of the semiconductor device of the tenth embodiment. It is a planar rectangular opening formed in (mask). The openings PA and PB serve as introduction regions of p-type impurities for forming the p-type semiconductor regions 15 and 13, respectively.

In addition, although the said 1st resist film and the said 2nd resist film are each a separate resist film apply | coated separately, it is shown in the same figure in order to show the relative planar positional relationship of opening part NA, NB, PA, and PB here.

The openings NA disposed in the charge injection and discharge portions are mutually disposed in a state where both ends of the second direction X overlap with a part of two capacitor electrodes FGC1 (the floating gate electrode FG) adjacent to each other. It is arranged between two adjacent capacitor electrodes FGC1 (floating gate electrode FG).

The opening portion NA is arranged to contain a portion of the active region L2 between two capacitor electrodes FGC1 adjacent to each other. The length of the second direction X of the opening NA is the other of the capacitor electrodes FGC1 adjacent to each other from the center of the second direction X (single direction) of one of the capacitor electrodes FGC1 to the other of the capacitor electrodes FGC1. It extends to the center of 2nd direction X (unidirectional) of (). Moreover, the length of the 2nd direction Y of the opening part NA becomes a grade substantially corresponded to the length of the 2nd direction of the p-type well HPW2.

Therefore, from the opening portion NA, the entire portion of the active region L2 between the capacitor electrodes FGC1 adjacent to each other and half of each second direction X (unidirectional) of the two capacitor electrodes FGC1. Part (iii) is exposed.

On the other hand, each of the two openings PA disposed in the charge injection and discharge portion has two ends of the two capacitor electrodes FGC1 (the floating gate electrode FG) adjacent to each other at one end of the second direction X. It is arranged to overlap on a part of. One end of each of the two directions X of the two openings PA is terminated at the center of each of the second directions X (single direction) of the two capacitor electrodes FGC1 adjacent to each other. Therefore, from each of the two openings PA, each of the second directions X of the two capacitor electrodes FGC1, which are different from the formation region (active region L2) of the p-type semiconductor region 15, is formed. Half of the (unidirectional) is exposed.

For this reason, in each of the two capacitor electrodes FGC1 adjacent to each other, an n-type semiconductor region formed by introduction of an n-type impurity from the opening NA and a p-type impurity from the opening PA are introduced. P-type semiconductor regions formed by the second semiconductor films are formed side by side along the second direction X (unidirectional).

However, the junction surface (boundary surface) of the n-type semiconductor region of the capacitor electrode FGC1 and the p-type semiconductor region does not intersect with the long direction (second direction Y) of the floating gate electrode FG. Is formed. That is, the junction surface of the n-type semiconductor region and the P-type semiconductor region of the capacitor electrode FGC1 is disposed along the longitudinal direction (second direction Y) of the floating gate electrode FG.

This is, for example, when the junction surface of the n-type semiconductor region of the capacitor electrode FGC1 and the p-type semiconductor region is formed so as to intersect with the longitudinal direction (second direction Y) of the floating gate electrode FG, This is because the pn junction surface intersects the supply direction of the potential, so that the transfer of the potential deteriorates and the data writing / erasing characteristic or the reading characteristic deteriorates.

In the case where the silicide layer is formed on the upper surface of the floating gate electrode FG, the potential is supplied through the silicide layer even if the pn junction surface is formed so as to intersect with the longitudinal direction of the capacitor electrode FGC1. can do. On the other hand, in the case of the tenth embodiment, since the silicide layer is not formed on the upper surface of the floating gate electrode FG as described above, the pn junction surface intersects the longer direction of the capacitor electrode FGC1. If formed, deterioration of transfer of the potential is likely to occur. Therefore, in the case of the tenth embodiment, it is particularly preferable that the pn junction surface formed on the capacitor electrode FGC1 does not intersect in the longitudinal direction of the capacitor electrode FGC1.

The floating gate electrode FG is formed of n + type polycrystalline silicon as described above before the impurity introduction step from the openings NA and PA.

The openings NB disposed in the capacitor portion are adjacent to each other in a state where both ends of the second direction X overlap with a part of two capacitor electrodes FGC2 (the floating gate electrode FG) adjacent to each other. It is arranged between two capacitor electrodes FGC2 (floating gate electrode FG).

The opening part NB is arranged to contain a portion of the active region L3 between two capacitor electrodes FGC2 adjacent to each other. The length of the second direction X of the opening NB is different from the desired position of the second direction X (single direction) of one capacitor electrode FGC2 among the two capacitor electrodes FGC2 adjacent to each other. It extends to the desired position of 2nd direction X (unidirectional) of FGC2. In addition, the length of the second direction Y of the opening portion NB is approximately equal to the length of the second direction Y of the p-type well HPW1.

For this reason, from the opening part NB, the whole part of the active area | region L3 between the capacitor electrodes FGC2 adjacent to each other, and most of each of the two capacitor electrodes FGC2 are exposed. Here, the neck portion FA of the floating gate electrode FG (the narrow portion, the wide portion of the floating gate electrode FG (capacitive electrode FGC2) and the boundary portion of the narrow width portion) also includes the opening portion ( NB).

On the other hand, each of the two opening portions PB disposed in the capacitor portion has a part of each of two capacitor electrodes FGC2 (the floating gate electrode FG) whose one end in the second direction X is adjacent to each other. Are arranged to overlap. From each of the two openings PB, each of the second directions X (unidirectional) of the two capacitor electrodes FGC2, which is different from the formation region (active region L3) of the p-type semiconductor region 13, is formed. Part of it is exposed.

For this reason, in each of the two capacitor electrodes FGC2 adjacent to each other, an n-type semiconductor region formed by introduction of an n-type impurity from the opening NB and a p-type impurity from the opening PB are introduced. P-type semiconductor regions formed by the sidewalls are formed side by side in an adjoining state along the second direction X (single direction). Further, the junction surface of the n-type semiconductor region and the p-type semiconductor region of the capacitor electrode FGC2 is formed in the capacitor electrode FGC2 along the longitudinal direction (second direction Y) of the floating gate electrode FG. do.

However, in the tenth embodiment, the junction surface (boundary surface) of the n-type semiconductor region and the p-type semiconductor region is not formed in the neck portion FA of the floating gate electrode FG. For this reason, the opening part NB is formed so that the long side (the side along the 2nd direction X which cross | intersects the longitudinal direction of the floating gate electrode FG) may cross | intersect at the width | variety of the width | variety of the floating gate electrode FG. do.

This is, for example, in the neck portion FA of the floating gate electrode FG, the joining surface of the n-type semiconductor region and the p-type semiconductor region is in the longer direction (second direction Y) of the floating gate electrode FG. This is because if the pn junction surface intersects the supply direction of the potential when the pn junction surface intersects with, the transfer of the potential deteriorates and the data writing / erasing characteristic or the reading characteristic deteriorates.

FIG. 53 shows an example where the pn junction surface is formed in the neck portion FA. Also in this case, the resist film serving as a mask for introducing the n-type impurity and the resist film serving as a mask for introducing the p-type impurity are individually applied to the resist film.

The opening part NC has shown the opening part for n-type impurity introduction. The opening part NC has two capacitor electrodes FGC2 adjacent to each other in a state where both ends of the second direction X overlap with a part of two capacitor electrodes FGC2 adjacent to each other (floating gate electrode FG). ) (Floating gate electrode FG). However, the length of the second direction Y of the opening portion NC is smaller than the length of the second direction Y of the active region L3, and the neck portion FA is not exposed from the opening portion NC.

In addition, the opening part PC has shown the opening part for introducing p-type impurity. The openings PC have two capacitor electrodes FGC2 adjacent to each other in a state where both ends of the second direction X overlap with a part of two capacitor electrodes FGC2 (the floating gate electrode FG) adjacent to each other. ) (Floating gate electrode FG). From the opening PC, the entirety of the active region L3 between the two capacitor electrodes FGC2 adjacent to each other and most of each of the second directions X (unidirectional) of the two capacitor electrodes FGC2 are exposed. In addition, the neck portion FA is also exposed.

In this example, an n-type semiconductor region 31 and a p-type semiconductor region 13 are formed in one active region L3 between two capacitor electrodes FGC2. For this reason, it is effective against the problem of the depletion layer of the said board | substrate 1S.

However, as described above, since the floating gate electrode FG is formed of n + type polycrystalline silicon, in the case of the example of FIG. 53, the pn junction surface is in the longitudinal direction of the floating gate electrode FG in the neck portion FA. It is formed to intersect with respect to. For this reason, since the pn junction surface is formed so that it may cross | intersect with the supply direction of electric potential, transfer of electric potential will deteriorate, and data recording / erasing characteristic or reading characteristic will deteriorate.

Here, in the case where the silicide layer is formed on the upper surface of the floating gate electrode FG, the supply of electric potential is supplied through the silicide layer even if the pn junction surface exists so as to intersect in the long direction of the floating gate electrode FG. There is no problem because you can. In contrast, in the tenth embodiment, since the silicide layer is not formed on the upper surface of the floating gate electrode FG as described above, the pn junction surface intersects the longer direction of the floating gate electrode FG. If formed, deterioration of transfer of the potential is likely to occur. Therefore, in the case of the tenth embodiment, it is particularly preferable that the pn junction surface is not formed in the neck portion FA.

54 shows another example in which the pn junction surface is not formed in the neck portion FA. In this case as well, the resist film serving as a mask for introducing the n-type impurity and the resist film serving as a mask for introducing the p-type impurity are respectively applied separately.

The opening ND represents an opening for introducing n-type impurities. The opening ND is disposed so as to overlap the upper portions of the two capacitor electrodes FGC2 (the floating gate electrode FG) and the active region L3 adjacent to each other. The length of the second direction Y of the opening ND is shorter than the length of the second direction Y of the active region L3, but the neck portion FA is exposed from the opening ND. On the other hand, the openings PD and PE represent openings for introducing p-type impurities.

In this example, the n-type semiconductor region 31 and the p-type semiconductor region 13 are formed in one active region L3 between the two capacitor electrodes FGC2, so that the substrate 1S is formed. It is effective for the problem of depletion layer. Further, since the pn junction surface is not formed in the neck portion FA, it is effective also in the problem of deterioration of the data writing / erasing characteristic or the reading characteristic due to the deterioration of the transfer of the electric potential.

However, as in this case, an n-type semiconductor region 31 and a p-type semiconductor region 13 are formed in one active region L3. In this case, there are the following problems. That is, during wet etching or cleaning, when light hits the pn junction formed by the n-type semiconductor region 31 and the p-type semiconductor region 13, photovoltaic power is generated, and the p-type semiconductor region 31 and The defect that the etching rate changes in the n-type semiconductor region 13 occurs. For this reason, in such a case, light does not come into contact with the pn junction portion formed by the n-type semiconductor region 31 and the p-type semiconductor region 13 of the substrate 1S during wet etching or cleaning. Although it is possible to make it as shown in FIG. 54 like this, it is preferable to prevent a pn junction part from forming in one active region L3.

(Embodiment 11)

In the eleventh embodiment, another configuration example in which another conductive region of a conductive type is formed in the floating gate electrode of the flash memory will be described.

Fig. 55 shows a mask for forming n-type semiconductor regions 30, 31 and p-type semiconductor regions 13, 15 in memory cells MC in the flash memory of the semiconductor device of the eleventh embodiment. A plan view of the memory cell MC is shown. In this case as well, the resist film serving as a mask for introducing the n-type impurity and the resist film serving as a mask for introducing the p-type impurity are respectively applied separately.

In the memory cell MC of the flash memory of the eleventh embodiment shown in FIG. 55, the configuration of the memory cell MC in FIG. 52 is different from that of the opening portion NB2 of the capacitor portion.

The opening part NB2 is a planar rectangular opening formed in the first resist film (mask) on the main surface of the substrate 1S (the wafer in this step) in the manufacturing process of the semiconductor device of the eleventh embodiment. It becomes an introduction region of n-type impurities for forming the n-type semiconductor region 31.

The dimension and arrangement in the second direction Y of the opening portion NB2 are the same as those described in FIG. 52. The other is that the length of the second direction X of the opening NB2 is from the center of the second direction X (unidirectional) of one of the capacitor electrodes FGC2 among the two capacitor electrodes FGC2 adjacent to each other. It extends to the center of the second direction X (single direction) of the other capacitor electrode FGC2. Therefore, from the opening portion NB2, half of the entire active region L3 portion between the capacitor electrodes FGC2 adjacent to each other, and half of each of the two capacitance electrodes FGC2 in each of the second directions X (unidirectional). (Iii) is exposed.

Next, FIG. 56 is a sectional view showing the principal parts of the substrate 1S of the charge injection-emitting portion of the memory cell MC in the flash memory of the semiconductor device of the eleventh embodiment in the second direction X, and FIG. 57 is the eleventh embodiment. Fig. 1 is a cross-sectional view of the main portion of the substrate 1S in the capacity portion of the memory cell MC in the flash memory of the semiconductor device according to the second direction X. FIG.

56 and 57, n + type semiconductor regions 40a and 40b and p + type semiconductor regions 41a and 41 are formed in each of the capacitor electrodes FGC1 and FGC2 of the charge injection discharge portion and the capacitor portion. It is formed side by side along the second direction X. In the floating gate electrode FG, portions other than the capacitor portions CWE and C are n + type. The other configuration is the same as that of the tenth embodiment.

The reason for this configuration is that if the conductive types of the capacitor electrodes FGC1 and FGC2 are single, the lower front surface of the capacitor electrodes FGC1 and FGC2 is depleted by the voltage applied to the p-type wells HPW1 and HPW2. This is because it is thrown away. For example, in the case where the entirety of the capacitor electrodes FGC1 and FGC2 is n + type, a positive voltage may be applied to the p-type wells HPW1 and HPW2, but a negative voltage is applied to the p-type wells HPW1 and HPW2. The depletion layer is formed over the entirety of the capacitor electrodes FGC1 and FGC2 (part side in contact with the gate insulating films 10c and 10d). As a result, the effective coupling capacitance decreases, so that the control efficiency of the potential of the capacitor electrodes FGC1 and FGC2 (floating gate electrode FG) decreases. Therefore, the time for writing and erasing data is delayed. In addition, the data writing speed and erasing speed become uneven.

In contrast, according to the eleventh embodiment, the conductive semiconductor regions of both the p-type and the n-type are formed in the capacitor electrodes FGC1 and FGC2, so that any of the positions in the p-type wells HPW1 and HPW2 are fixed. Even when the voltage of the side is applied, either half of the lower half of the capacitor electrodes FGC1 and FGC2 may not be depleted. As a result, the effective coupling capacitance can be increased, so that the potentials of the capacitor electrodes FGC1 and FGC2 (the floating gate electrode FG) can be efficiently controlled. Therefore, the writing speed and erasing speed of data can be improved. In addition, the nonuniformity of the data writing speed and erasing speed can also be reduced.

58 and 59 show an example of the shape of the capacitor portion at the time of data recording and erasing of the memory cell MC. In addition, although the shape of the capacitor | condenser C of the memory cell MC is demonstrated here, it is the same also in the charge injection discharge part (capacitive part CWE).

First, FIG. 58 is a sectional view showing the principal parts of the capacitor C in the data direction of the memory cell MC of the eleventh embodiment in the second direction X of the substrate 1S.

For data recording, for example, a constant voltage of about +9 V is applied to the p-type well HPW1 of the capacitor C. As shown in FIG. In this case, the depletion layer 43 is formed in the p + type semiconductor region 41b of the capacitor electrode FGC2, but the depletion layer 43 is formed in the n + type semiconductor region 40b of the capacitor electrode FGC2. It doesn't work. For this reason, since an effective coupling capacitance can be ensured, the potential of the capacitor electrode FGC2 (floating gate electrode FG) can be efficiently controlled.

Therefore, the data writing speed can be improved. In addition, the nonuniformity of the data recording speed can be reduced.

Next, FIG. 59 is a sectional view showing the principal parts of the substrate 1S in the second direction X of the capacitor C during data erasing of the memory cell MC of the eleventh embodiment.

For data erasing, a negative voltage of, for example, about -9V is applied to the p-type well HPW1 of the capacitor C. In this case, the depletion layer 43 is formed in the n + type semiconductor region 40b of the capacitor electrode FGC2, but the depletion layer 43 is formed in the p + type semiconductor region 41b of the capacitor electrode FGC2. It doesn't work. For this reason, since an effective coupling capacitance can be ensured, the potential of the capacitor electrode FGC2 (floating gate electrode FG) can be efficiently controlled. Therefore, the data erasing speed can be improved. In addition, the nonuniformity of the data erasing speed can be reduced.

As mentioned above, although the invention by this inventor was demonstrated concretely based on embodiment, this invention is not limited to the said embodiment, Needless to say that various changes are possible in the range which does not deviate from the summary.

In the above description, the present invention has been mainly described in the case where the invention by the present inventors is applied to the method of manufacturing a semiconductor device, which is the background of the use. However, the present invention is not limited thereto. can do.

In this case, by forming the flash memory on the semiconductor substrate on which the micro machine is formed, it is possible to store simple information of the micro machine.

The present invention can be applied to the manufacturing industry of semiconductor devices having a nonvolatile memory.

Among the inventions disclosed in the present application, the effects obtained by the representative ones are briefly described as follows.

That is, in a nonvolatile memory cell having a data writing and erasing element having a common floating gate electrode as a gate electrode and a transistor for data reading, the data writing and erasing element and the data reading transistor are mutually different. It is provided in the wells of the same conductivity type electrically isolated, and a pair of semiconductor areas of the element for data recording and erasing are formed by the same conductivity type semiconductor area as the well. As a result, in the device for data writing and erasing of the nonvolatile memory cell, data can be rewritten by the FN tunnel current on the entire channel.

Claims (29)

A semiconductor substrate having a first main surface and a second main surface behind it; A main circuit formation region disposed on the first main surface of the semiconductor substrate; A nonvolatile memory region disposed on the first main surface of the semiconductor substrate, The nonvolatile memory region may include a first well of a first conductivity type formed on a main surface of the semiconductor substrate; A second well having a conductivity type opposite to the first conductivity type, the second well disposed to be contained in the first well, A third well disposed as the well of the second conductivity type and disposed in the first well along the second well in a state electrically isolated from the second well; A fourth well that is of the second conductivity type and is disposed to be contained in the first well along the second well in a state of being electrically separated from the second well and the third well; A nonvolatile memory cell disposed to overlap the second well, the third well, and the fourth well in a planar manner, The nonvolatile memory cell may include a floating gate electrode disposed to extend in a first direction to overlap the second well, the third well, and the fourth well in a planar manner. An element for data writing and erasing, wherein said floating gate electrode is formed at a first position planarly overlapping said second well; A field effect transistor for reading data, wherein the floating gate electrode is formed at a second position overlapping the third well in a plane; The floating gate electrode includes a capacitor formed at a third position overlapping the fourth well in a plane; The data recording and erasing element includes a first electrode formed at the first position of the floating gate electrode, a first insulating film formed between the first electrode and the semiconductor substrate, and within the second well. And a pair of semiconductor regions of a second conductivity type formed at a position at which the first electrode is inserted, and the second well, The field effect transistor for data reading is A second electrode formed at the second position of the floating gate electrode, a second insulating film formed between the second electrode and the semiconductor substrate; A pair of semiconductor regions of a first conductivity type formed at a position in which the second electrode is inserted into the third well, The capacitor includes a third electrode formed at the third position of the floating gate electrode, a third insulating film formed between the third electrode and the semiconductor substrate; And a fourth pair of semiconductor regions of a second conductivity type formed at a position in which the third electrode is inserted in the fourth well, and the fourth well. The method of claim 1, And rewriting data in the data recording and erasing element by the FN tunnel current in the entire channel. The method of claim 1, And an external power source supplied from the outside of the semiconductor substrate is a single power source. The method of claim 1, And a length in the second direction crossing the third electrode in the first direction is longer than a length in the second direction of the first electrode and the second electrode. The method of claim 1, And a thickness of said first insulating film of said data recording and erasing element is 10 nm or more and 20 nm or less. The method of claim 1, In the main circuit forming region, a low breakdown field effect transistor driven at a first operating voltage and a high breakdown field effect transistor driven at a second operating voltage higher than the first operating voltage are disposed. And the gate insulating film of the low withstand voltage field effect transistor is formed to have the same thickness as the first insulating film. The method of claim 1, And a field effect transistor for selection is electrically connected to the field effect transistor for data reading of the nonvolatile memory cell so that the nonvolatile memory cell can be selected. A semiconductor substrate having a first main surface and a second main surface behind it; A main circuit formation region disposed on the first main surface of the semiconductor substrate; A nonvolatile memory region disposed on the first main surface of the semiconductor substrate, In the nonvolatile memory area, A first well of a first conductive type formed on a main surface of the semiconductor substrate and a well of a second conductive type opposite to the first conductive type, A second well disposed to be contained in the first well and a second conductive well opposite to the first conductive type, and electrically separated from the second well, along the second well; A third well disposed to be contained in the first well, A fourth well disposed as the second conductive well and disposed in the first well along the second well in an electrically separated state from the second well and the third well; And a plurality of nonvolatile memory cells arranged to overlap the second well, the third well, and the fourth well in a planar manner. Each of the plurality of nonvolatile memory cells, A floating gate electrode disposed to extend in a first direction to overlap the second well, the third well, and the fourth well in a planar manner; An element for data writing and erasing, wherein said floating gate electrode is formed at a first position planarly overlapping said second well; A field effect transistor for reading data, wherein the floating gate electrode is formed at a second position overlapping the third well in a plane; The floating gate electrode includes a capacitor formed at a third position overlapping the fourth well in a planar manner, and the data recording and erasing element comprises: a first electrode formed at the first position of the floating gate electrode; A first insulating film formed between the first electrode and the semiconductor substrate, a pair of semiconductor regions of a second conductive type formed at a position to insert the first electrode in the second well, and the first insulating film formed between the first electrode and the semiconductor substrate. With two wells, The field effect transistor for data reading is A second electrode formed at the second position of the floating gate electrode, a second insulating film formed between the second electrode and the semiconductor substrate, and a position at which the second electrode is inserted in the third well; And a pair of semiconductor regions of the first conductive type formed, The capacitor device, A third electrode formed at the third position of the floating gate electrode, a third insulating film formed between the third electrode and the semiconductor substrate, and a position at which the third electrode is inserted in the fourth well; A semiconductor device comprising a pair of semiconductor regions of a second conductive type formed and said fourth well. The method of claim 8, In the field effect transistors for reading data of each of the plurality of nonvolatile memory cells, And a field effect transistor for selection is electrically connected to select each of the plurality of nonvolatile memory cells. A semiconductor substrate having a first main surface and a second main surface behind it; A main circuit forming region disposed on the first main surface of the semiconductor substrate; A nonvolatile memory region disposed on the first main surface of the semiconductor substrate, In the nonvolatile memory area, A first well of a first conductivity type formed on a main surface of the semiconductor substrate, a well of a second conductivity type having a conductivity type opposite to that of the first conductivity type, and a second well disposed to be contained in the first well; A third well disposed to be contained in the first well along the second well in a state in which the well of the second conductivity type is electrically separated from the second well; A fourth well disposed as the second conductive well and disposed in the first well along the second well in an electrically separated state from the second well and the third well; A nonvolatile memory cell disposed to overlap the second well, the third well, and the fourth well in a planar manner, The nonvolatile memory cell may include a floating gate electrode disposed to extend in a first direction to overlap the second well, the third well, and the fourth well in a planar manner. An element for data writing and erasing formed at a first position where said floating gate electrode overlaps planarly with said second well, and an electric field for reading data formed at a second position with said floating gate electrode planarly overlapping with said third well With effect transistors, The floating gate electrode includes a capacitor formed at a third position overlapping the fourth well in a plane; The data recording and erasing element is A first electrode formed at the first position of the floating gate electrode, a first insulating film formed between the first electrode and the semiconductor substrate, and a position at which the first electrode is inserted in the second well; A pair of semiconductor regions of a second conductivity type to be formed, and the second well, The field effect transistor for data reading is A second electrode formed at the second position of the floating gate electrode; A second insulating film formed between the second electrode and the semiconductor substrate; A pair of semiconductor regions of a first conductivity type formed at a position in which the second electrode is inserted into the third well, The capacitor includes a third electrode formed at the third position of the floating gate electrode, a third insulating film formed between the third electrode and the semiconductor substrate; A pair of semiconductor regions of a second conductivity type formed at a position to insert the third electrode in the fourth well, and the fourth well; In the main circuit forming region, a low breakdown voltage effect transistor driven at a first operating voltage and a high breakdown field effect transistor driven at a second operating voltage higher than the first operating voltage are disposed. A field effect transistor for selection is electrically connected to the field effect transistor for data reading of the nonvolatile memory cell so that the nonvolatile memory cell can be selected. And the thickness and gate length of the gate insulating film of the field effect transistor for selection are equal to the thickness and gate length of the gate insulating film of the low-voltage field effect transistor. The method of claim 10, And the well in which the field effect transistor for selection is formed is formed by the same process as the well in which the low withstand voltage effect transistor is formed. A semiconductor substrate having a first main surface and a second main surface behind it; A main circuit formation region disposed on the first main surface of the semiconductor substrate; A nonvolatile memory region disposed on the first main surface of the semiconductor substrate, In the nonvolatile memory area, A first well of a first conductivity type formed on a main surface of the semiconductor substrate, A second well having a conductivity type opposite to the first conductivity type, the second well disposed to be contained in the first well, A third well disposed as the well of the second conductivity type and disposed in the first well along the second well in a state electrically isolated from the second well; A fourth well disposed as the second conductive well and disposed in the first well along the second well in an electrically separated state from the second well and the third well; A nonvolatile memory cell disposed to overlap the second well, the third well, and the fourth well in a planar manner, The nonvolatile memory cell, A floating gate electrode disposed to extend in a first direction to overlap the second well, the third well, and the fourth well in a planar manner; An element for data writing and erasing, wherein said floating gate electrode is formed at a first position planarly overlapping said second well; A field effect transistor for reading data, wherein the floating gate electrode is formed at a second position overlapping the third well in a plane; The floating gate electrode includes a capacitor formed at a third position overlapping the fourth well in a plane; The data recording and erasing element is A first electrode formed at the first position of the floating gate electrode, a first insulating film formed between the first electrode and the semiconductor substrate, and a position at which the first electrode is inserted in the second well; A pair of semiconductor regions to be formed and the second well, The field effect transistor for data reading is A second electrode formed at the second position of the floating gate electrode, a second insulating film formed between the second electrode and the semiconductor substrate, and a position at which the second electrode is inserted in the third well; And a pair of semiconductor regions of the first conductive type formed, The capacitor device, A third electrode formed at the third position of the floating gate electrode, a third insulating film formed between the third electrode and the semiconductor substrate, and a position at which the third electrode is inserted in the fourth well; The pair of semiconductor regions to be formed and the semiconductor region including the fourth well and the pair of semiconductor regions for the data recording and erasing elements are of opposite conductivity types. The semiconductor device as set forth in claim 2, wherein both of the pair of semiconductor regions of the capacitor are the second conductive type. The method of claim 12, A semiconductor device characterized in that both of the first conductive semiconductor region and the second conductive semiconductor region are formed in the floating gate electrode of the arrangement region of the data recording and erasing element. The method of claim 13, The semiconductor region of the first conductive type and the semiconductor region of the second conductive type of the floating gate electrode of the arrangement region of the element for data writing and erasing are The conductive type of the floating gate electrode is separated into the first conductive type and the second conductive type along a second direction crossing in the first direction, And the conductive type of the floating gate electrode is arranged so as not to be separated into the first conductive type and the second conductive type in the first direction. The method of claim 14, A boundary between the first conductive semiconductor region and the second conductive semiconductor region of the floating gate electrode in the arrangement region of the data recording and erasing element is And a semiconductor device arranged in the center of the second direction. The method of claim 13, A silicide layer is formed on an upper surface of the pair of semiconductor regions of the data recording and erasing element and the pair of semiconductor regions of the capacitor; And a silicide layer is not formed on an upper surface of the floating gate electrode. The method of claim 12, Each of the pair of semiconductor regions of the data recording and erasing element is formed of one conductive type so that the boundary between the first conductive type and the second conductive type is not formed in each of the pair. A semiconductor device. A semiconductor substrate having a first main surface and a second main surface behind it; A main circuit formation region disposed on the first main surface of the semiconductor substrate; A nonvolatile memory region disposed on the first main surface of the semiconductor substrate, In the nonvolatile memory area, A first well of a first conductivity type formed on a main surface of the semiconductor substrate, A second well having a conductivity type opposite to the first conductivity type, the second well disposed to be contained in the first well, A third well disposed as the well of the second conductivity type and disposed in the first well along the second well in a state electrically isolated from the second well; A fourth well disposed as the second conductive well and disposed in the first well along the second well in an electrically separated state from the second well and the third well; A nonvolatile memory cell disposed to overlap the second well, the third well, and the fourth well in a planar manner, The nonvolatile memory cell, A floating gate electrode disposed to extend in a first direction to overlap the second well, the third well, and the fourth well in a planar manner; An element for data writing and erasing, wherein said floating gate electrode is formed at a first position planarly overlapping said second well; A field effect transistor for reading data, wherein the floating gate electrode is formed at a second position overlapping the third well in a plane; The floating gate electrode includes a capacitor formed at a third position overlapping the fourth well in a plane; The data recording and erasing element is A first electrode formed at the first position of the floating gate electrode, a first insulating film formed between the first electrode and the semiconductor substrate, and a position at which the first electrode is inserted in the second well; A pair of semiconductor regions to be formed and the second well, The field effect transistor for data reading is A second electrode formed at the second position of the floating gate electrode, a second insulating film formed between the second electrode and the semiconductor substrate, and a position at which the second electrode is inserted in the third well; And a pair of semiconductor regions of the first conductive type formed, The capacitor device, A third electrode formed at the third position of the floating gate electrode, a third insulating film formed between the third electrode and the semiconductor substrate, and a position at which the third electrode is inserted in the fourth well; A pair of semiconductor regions to be formed and the fourth well, The pair of semiconductor regions of the capacitive element are of opposite conductivity types, 2. The semiconductor device according to claim 2, wherein any one of the pair of semiconductor regions of the data recording and erasing element is the second conductive type. The method of claim 18, And a semiconductor region of the first conductive type and a semiconductor region of the second conductive type are formed in the floating gate electrode in the arrangement region of the capacitor. The method of claim 19, The first conductive semiconductor region and the second conductive semiconductor region of the floating gate electrode in the arrangement region of the capacitor are The conductive type of the floating gate electrode is separated into the first conductive type and the second conductive type in a second direction crossing in the first direction, And the conductive type of the floating gate electrode is arranged so as not to be separated into the first conductive type and the second conductive type in the first direction. The method of claim 20, The boundary between the first conductive semiconductor region and the second conductive semiconductor region of the floating gate electrode in the arrangement region of the capacitor is arranged in the center of the second direction. The method of claim 19, A silicide layer is formed on an upper surface of the pair of semiconductor regions of the data recording and erasing element and the pair of semiconductor regions of the capacitor; And a silicide layer is not formed on an upper surface of the floating gate electrode. The method of claim 18, Each of the pair of semiconductor regions of the capacitor is formed of a single conductive type such that no boundary between the first conductive type and the second conductive type is formed in each of the pair of semiconductor regions. A semiconductor substrate having a first main surface and a second main surface behind it; A main circuit formation region disposed on the first main surface of the semiconductor substrate; A nonvolatile memory region disposed on the first main surface of the semiconductor substrate, In the nonvolatile memory area, A first well of a first conductivity type formed on a main surface of the semiconductor substrate, A second well having a conductivity type opposite to the first conductivity type, the second well disposed to be contained in the first well, A third well disposed as the well of the second conductivity type and disposed in the first well along the second well in a state electrically isolated from the second well; A fourth well disposed as the second conductive well and disposed in the first well along the second well in an electrically separated state from the second well and the third well; A nonvolatile memory cell disposed to overlap the second well, the third well, and the fourth well in a planar manner, The nonvolatile memory cell, A floating gate electrode disposed to extend in a first direction to overlap the second well, the third well, and the fourth well in a planar manner; An element for data writing and erasing, wherein said floating gate electrode is formed at a first position planarly overlapping said second well; A field effect transistor for reading data, wherein the floating gate electrode is formed at a second position overlapping the third well in a plane; The floating gate electrode includes a capacitor formed at a third position overlapping the fourth well in a plane; The data recording and erasing element is A first electrode formed at the first position of the floating gate electrode, a first insulating film formed between the first electrode and the semiconductor substrate, and a position at which the first electrode is inserted in the second well; A pair of semiconductor regions to be formed and the second well, The field effect transistor for data reading is A second electrode formed at the second position of the floating gate electrode, a second insulating film formed between the second electrode and the semiconductor substrate, and a position at which the second electrode is inserted in the third well; And a pair of semiconductor regions of the first conductive type formed, The capacitor includes a third electrode formed at the third position of the floating gate electrode, a third insulating film formed between the third electrode and the semiconductor substrate, and the third electrode in the fourth well. A pair of semiconductor regions formed at positions to sandwich the first and fourth wells, The pair of semiconductor areas of the capacitive element are of opposite conductivity types, and the pair of semiconductor areas of the data recording and erasing elements are of opposite conductivity types. Semiconductor device. The method of claim 24, Both the first conductive semiconductor region and the second conductive semiconductor region are formed in the floating gate electrode in the arrangement region of the data recording and erasing element and the capacitor element. Semiconductor device. The method of claim 25, The semiconductor region of the first conductive type and the semiconductor region of the second conductive type of the floating gate electrode in the arrangement region of the data recording and erasing element and the capacitor element, The conductive type of the floating gate electrode is separated into the first conductive type and the second conductive type in a second direction crossing in the first direction, And the conductive type of the floating gate electrode is arranged so as not to be separated into the first conductive type and the second conductive type in the first direction. The method of claim 26, The boundary between the first conductive semiconductor region and the second conductive semiconductor region of the floating gate electrode in the arrangement region of the data recording and erasing element and the capacitor element is And a semiconductor device arranged in the center of the second direction. The method of claim 25, A silicide layer is formed on an upper surface of the pair of semiconductor regions of the data recording and erasing element and the pair of semiconductor regions of the capacitor; And a silicide layer is not formed on an upper surface of the floating gate electrode. The method of claim 24, Each of the pair of semiconductor regions of the data recording and erasing element is formed of one conductive type so that the boundary between the first conductive type and the second conductive type is not formed in each of the pairs. Each of the pair of semiconductor regions of the capacitor is formed of a single conductive type such that no boundary between the first conductive type and the second conductive type is formed in each of the pair of semiconductor regions.

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