KR20070011953A - Shift register - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register capable of preventing multiple outputs due to a coupling phenomenon.

The shift register according to the present invention includes a first node and a second node, and selectively outputs a first voltage source or a second voltage source input from the outside to the first node and the second node to provide the first node and the second node. A node controller for charging or discharging; A pull-up switching device configured to output a clock pulse input to the gate line as a scan pulse according to a charge or discharge state of the first node; And a pull-down switching element configured to output a third voltage source to the gate line according to the charging or discharging state of the second node, wherein the second voltage source is different from the third voltage source.

By such a configuration, the shift register according to the present invention provides a shift register which can reduce the occurrence of multi output by varying the magnitude of the voltage for discharging the first and second nodes and the voltage supplied to the source terminal of the pull-down transistor. The purpose is.

Description

Shift Register

1 is a diagram illustrating a conventional shift register.

2 illustrates a shift register of the present invention.

3 is a configuration diagram of a second stage of the present invention.

FIG. 4A is a diagram for describing that when the first node is discharged and the second node is charged, the multi output due to the coupling phenomenon is prevented.

FIG. 4B is a view for explaining that when the first node of FIG. 3 is in a charged state and the second node is in a discharge state, multi-output due to a coupling phenomenon is prevented.

5 is a diagram illustrating a circuit configuration of a node controller and an output unit provided in the second stage.

         <Explanation of symbols for main parts of drawing>

300a: node control unit 300b: output unit

SP: Start pulse V _DD : First voltage source

V _SS : Second voltage source V _GL : third voltage source

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display device, and more particularly to a shift register capable of preventing multiple outputs due to a coupling phenomenon.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The timing controller controls driving timing of the gate driver and the data driver and supplies a pixel data signal to the data driver. The power supply unit boosts or decompresses an input power to generate driving voltages such as a common voltage V _COM , a gate high voltage signal V _GH , and a gate low voltage signal V _GL required by the liquid crystal display. do. The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a shift register to sequentially output the scan pulses as described above. This will be described in more detail with reference to the accompanying drawings.

1 is a diagram illustrating a conventional shift register.

As shown in FIG. 1, the conventional shift register includes n stages AST1 to ASTn and one dummy stage ASTn + 1 connected to each other in a dependent manner. Each of the stages AST1 to ASTn + 1 outputs one scan pulse Vout1 to Voutn + 1, and in this case, the scan pulses Vout1 to Voutn sequentially from the first stage AST1 to the dummy stage ASTn + 1. Output +1) Here, scan pulses Vout1 to Voutn output from the stages AST1 to ASTn except for the dummy stage ASTn + 1 are sequentially supplied to gate lines of the liquid crystal panel, thereby sequentially ordering the gate lines. Scanning is done with.

The entire stages AST1 to ASTn + 1 of the shift registers configured as described above are first to fourth clock pulses CLK1 to sequential phase difference with the first voltage source V _DD and the second voltage source V _SS and with each other. Two clock pulses of CLK4) are applied. Here, the first voltage source (V _DD ) means a voltage source of high potential, and means a voltage of the second voltage source (V _SS ) and a low potential.

Meanwhile, the first stage located on the uppermost side of the stages AST1 to ASTn + 1 may include a start pulse SP in addition to the first voltage source V _DD , the second voltage source V _SS , and the two clock pulses. Is supplied).

The operation of the conventional shift register configured as described above will be described in detail as follows.

First, when a start pulse SP from a timing controller (not shown) is applied to the first stage AST1, the first stage AST1 is enabled in response to the start pulse SP.

Subsequently, the enabled first stage AST1 receives the first and second clock pulses CLK1 to CLK2 from the timing controller, and outputs a first scan pulse Vout1. It is supplied together to the 2 stage AST2. Then, the second stage AST2 is enabled in response to the first scan pulse Vout1.

Subsequently, the enabled second stage AST2 receives the second and third clock pulses CLK2 and CLK3 from the timing controller and outputs a second scan pulse Vout2, and the second gate line, The third stage AST3 and the first stage AST1 are supplied together. Then, the third stage AST3 is enabled in response to the second scan pulse Vout2, and the first stage AST1 is disabled in response to the second scan pulse Vout2. A second voltage source V _SS is supplied to the first gate line.

Subsequently, the enabled third stage AST3 receives the third and fourth clock pulses CLK3 and CLK4 from the timing controller (not shown), and outputs a third scan pulse Vout3. The third gate line, the fourth stage AST4 and the second stage AST2 are supplied together. Then, the fourth stage AST4 is enabled in response to the third scan pulse Vout3, and the second stage AST2 is disabled in response to the third scan pulse Vout3. A second voltage source V _SS is supplied to the second gate line.

In this manner, the first to nth scans are sequentially output to the fourth to nth gate lines by outputting the fourth to nth scan pulses Voutn to the remaining fourth to nth stages AST4 to ASTn. Scanned in turn by pulses Vout1 through Voutn.

Meanwhile, the dummy stage ASTn + 1 is enabled in response to the nth scan pulse Voutn from the nth stage ASTn, and then receives two clock pulses from the timing controller. The first scan pulse Voutn + 1 is supplied to the nth stage ASTn so that the nth stage ASTn is disabled to provide the second voltage source V _SS to the nth gate line. . In other words, the dummy stage ASTn + 1 merely provides the n + 1 scan pulse Voutn + 1 so that the nth stage ASTn can output the second voltage source V _SS . The n + th scan pulse Voutn + 1 is not supplied to the gate line.

In general, the first to nth stages AST1 to ASTn may include a node controller for controlling the charge and discharge states of the first and second nodes, and a scan pulse or a first according to the states of the first and second nodes. It has an output part which outputs 2 voltage sources _VSS , and supplies it to the gate line of a liquid crystal panel.

Here, the first node and the second node are alternately charged and discharged. Specifically, when the first node is in a charged state, the second node is maintained in a discharged state, and the second node is charged. In this state, the first node maintains a discharged state.

At this time, the first node from the pull-up switching device the output of when the state of charge is a scan pulse is output, when the second node is charged to the second voltage source (V _ss) from the pull-down switching element of the output section Is output. Here, the scan pulse output from the pull-up switching element and the second voltage source V _SS output from the pull-down switching element Trd are supplied to the corresponding gate line. The gate terminal of the pull-up switching element is connected to the first node Q, the drain terminal is connected to a clock line to which a clock pulse is applied, and the source terminal is connected to the gate line. In this case, the pull-up switching device outputs any one of the clock pulses input for each period at a specific time point. The clock pulse output at this particular time point is a scan pulse for driving the gate line. This specific time point means a time point at which the first node is charged. That is, the pull-up switching element outputs, as a scan pulse, a clock pulse input at the specific time point (that is, the time point at which the first node is charged) among the clock pulses which are periodically input to its drain terminal. Done. After the output of the scan pulse, the pull-up switching element outputs one scan pulse per frame as the first node is kept in a discharge state until another frame starts. However, since the clock pulse is output several times during one frame, even when the pull-up switching element is turned off, that is, even when the first node is discharged, the clock pulse continues to the drain terminal of the pull-up switching element. Will be entered.

In other words, the pull-up switching device is turned on only once for one frame, and outputs a clock pulse input to its drain terminal as a scan pulse during this turn-on period. Thereafter, even when a clock pulse is input to its drain terminal during the turn-off period, the pull-up switching device cannot output it as a scan pulse. However, as the clock pulse is periodically applied to the drain terminal of the pull-up switching device, a coupling phenomenon occurs between the first node to which the gate terminal of the pull-up switching device is connected and the drain terminal of the pull-up switching device. . By this coupling phenomenon, the first node may be maintained in a charged state. That is, the first node may be kept in a charged state at an unwanted timing. In this case, the first node may be maintained in the charging state more than once in one frame, whereby the pull-up switching element may be turned on more than once in one frame. As a result, a multi-output phenomenon in which one stage outputs two or more scan pulses during one frame may occur due to the coupling phenomenon as described above.

 SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and prevents multiple outputs due to a coupling phenomenon by varying the magnitudes of the voltages that discharge the first and second nodes and the voltages supplied to the source terminals of the pull-down transistors. Its purpose is to provide a shift register.

The shift register according to the present invention for achieving the above object, having a first and second nodes, by selectively outputting a first voltage source or a second voltage source input from the outside to the first and second nodes A node controller configured to charge or discharge the first and second nodes; A pull-up switching device configured to output a clock pulse input to the gate line as a scan pulse according to a charge or discharge state of the first node; And a pull-down switching element configured to output a third voltage source to the gate line according to the charging or discharging state of the second node, wherein the second voltage source is different from the third voltage source.

Hereinafter, a shift register value according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register of the present invention.

As illustrated in FIG. 2, the shift register according to the present invention includes n stages BST1 to BSTn and one dummy stage BSTn + 1 connected to each other. Each of the stages BST1 to BSTn + 1 outputs one scan pulse Vout1 to Voutn + 1, and in this case, the scan pulses Vout1 to Voutn sequentially from the first stage BST1 to the dummy stage BSTn + 1. Output +1) Here, scan pulses Vout1 to Voutn output from the stages BST1 to BSTn except for the dummy stage BSTn + 1 are sequentially supplied to gate lines of the liquid crystal panel, thereby sequentially ordering the gate lines. Scanning is done with.

Meanwhile, the entire stages BST1 to BSTn + 1 of the shift register configured as described above have a first voltage source V _DD , a second voltage source V _SS , a third voltage source V _GL , and a sequential phase difference with each other. Two clock pulses are applied among the first to fourth clock pulses CLK1 to CLK4. Here, the first voltage source V _DD means a positive voltage source as a high potential voltage source, and the second voltage source V _SS and the third voltage source V _GL mean a negative voltage source as a low potential voltage source. .

Here, the first stage BST1 positioned at the uppermost side of the stages BST1 to BSTn + 1 may include the first voltage source V _DD , the second voltage source V _SS , the third voltage source V _GL , and the In addition to two clock pulses among the first to fourth clock pulses CLK1 to CLK4, a start pulse SP is supplied.

On the other hand, as described above, the first to fourth clock pulses CLK1 to CLK4 are phase-delayed by one pulse width and output. That is, the second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is one pulse than the second clock pulse CLK2. Phase delayed by a width is output, the fourth clock pulse (CLK4) is phase-delayed by one pulse width than the third clock pulse (CLK3) and output, the first clock pulse (CLK1) is the fourth clock pulse The signal is delayed in phase by one pulse width from CLK4.

On the other hand, the start pulse SP applied to the first stage BST1 is output earlier than the clock pulses CLK1 to CLK4. That is, the start pulse SP is output by one clock pulse width ahead of the first clock pulse CLK1. In addition, the start pulse SP is output only once in one frame. That is, after the start pulse SP is first outputted every frame, the first to fourth clock pulses CLK1 to CLK4 are sequentially output. In this case, the first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output while cycling. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2. The fourth clock pulse CLK4 and the start pulse SP may be output in synchronization with each other. In this case, the fourth clock pulse CLK4 is first outputted among the first to fourth clock pulses CLK1 to CLK4.

Meanwhile, the shift register according to the present invention may use two or more clock pulses. That is, the shift register according to the present invention may use only the first and second clock pulses CLK1 and CLK2 among the first to fourth clock pulses CLK1 to CLK4, and the first to third clock pulses CLK1. To CLK3) only. In addition, the shift register according to the present invention may use four or more clock pulses sequentially output.

The operation of the shift register configured as described above will be described in detail as follows.

First, when a start pulse SP is applied to a first stage BST1 from a timing controller (not shown), the first stage BST1 is enabled in response to the start pulse SP.

Subsequently, the enabled first stage BST1 receives the first and second clock pulses CLK1 and CLK2 from a timing controller (not shown), and outputs a first scan pulse Vout1, which is then applied to the first stage BST1. The gate line and the second stage BST2 are supplied together. Then, the second stage BST2 is enabled in response to the first scan pulse Vout1.

Subsequently, the enabled second stage BST2 receives the second and third clock pulses CLK2 and CLK3 from the timing controller (not shown), and outputs a second scan pulse Vout2. The second gate line, the third stage BST3 and the first stage BST1 are supplied together. Then, the third stage BST3 is enabled in response to the second scan pulse Vout2, and the first stage BST1 is disabled in response to the second scan pulse Vout2. Three voltage sources V _GL are supplied to the first gate line.

Subsequently, the enabled third stage BST3 receives the third and fourth clock pulses CLK3 and CLK4 from the timing controller, and outputs a third scan pulse Vout3, and the third gate line, The fourth stage BST4 and the second stage BST2 are supplied together. Then, the fourth stage BST4 is enabled in response to the third scan pulse Vout3, and the second stage BST2 is disabled in response to the third scan pulse Vout3. Three voltage sources V _GL are supplied to the second gate line.

In this manner, the fourth to nth scan pulses Vout4 to Voutn are sequentially output to the remaining fourth to nth stages BST4 to BSTn and sequentially applied to the fourth to nth gate lines. As a result, the first to nth gate lines are sequentially scanned by the sequentially output first to nth scan pulses Vout1 to Voutn.

In this case, the dummy stage BSTn + 1 is enabled in response to an nth scan pulse Voutn from the nth stage BSTn, and then, the first and second clocks from the timing controller (not shown). The pulses CLK1 and CLK2 are input to output the n + 1th scan pulse Voutn + 1 and are supplied to the nth stage BSTn. Then, in response to the n + 1 th scan pulse Voutn + 1, the n th stage BSTn is disabled to supply a third voltage source V _GL to the n th gate line.

Meanwhile, the configuration of each stage BST1 to BSTn + 1 provided in the shift register according to an embodiment of the present invention will be described in more detail as follows. Here, since the configurations of the second to nth stages BST2 to BSTn and the dummy stages BSTn + 1 are the same, only the second stage BST2 will be representatively described.

3 is a diagram illustrating a configuration of a second stage of the present invention.

 That is, the node controller 300a includes a plurality of switching elements (not shown) for charging and discharging the first and second nodes Q and QB. Here, the node controller 300a alternately charges and discharges the first and second nodes Q and QB. That is, the node controller 300a maintains the second node QB in a discharged state and maintains the first node Q in a discharged state when the first node Q is kept in a charged state. When the second node (Q) is kept in a charged state.

In order to charge or discharge the first and second nodes Q and QB, the node controller 300a uses first and second voltage sources V _DD and V _SS . That is, the node controller 300a supplies the first node Q or the second node QB by supplying the first voltage source V _DD to the first node Q or the second node QB. The first node Q or the second node QB is discharged by supplying the second voltage source VSS to the first node Q or the second node QB.

The output unit 300b outputs a third voltage source VGL or a scan pulse SP according to the states of the first and second nodes Q and QB. For this operation, the output unit 300b includes a pull-up switching device Tru and a pull-down switching device Trd. The pull-up switching device Tru outputs a clock pulse supplied to its drain terminal through its source terminal in response to the first voltage source V _DD charged in the first node Q. This source terminal is connected to the corresponding gate line. In response to the first voltage source V _DD charged in the second node QB, the pull-down switching element Trd uses its drain terminal as the third voltage source V _GL supplied to its source terminal. Output through The drain terminal is connected to the source terminal of the pull-up switching element Tru and simultaneously connected to the gate line.

Here, the sizes of the second voltage source V _SS and the third voltage source V _GL are different from each other. In detail, the size of the second voltage source V _SS is smaller than that of the third voltage source V _GL . In the conventional shift register, the size of the second voltage source V _SS and the size of the third voltage source V _GL are the same. That is, the size of the second voltage source V _SS for discharging the first node and the second node Q and QB of the conventional shift register is a third voltage source (supplied to the source terminal of the pull-down switching element Trd). V _GL ). Therefore, the multi-output is easy to occur, the shift resistor of the present invention can improve the conventional problem by varying the size of the second voltage source (V _SS ) and the third voltage source (V _GL ).

If this is explained in more detail as follows.

FIG. 4A is a diagram for explaining that when the first node Q of FIG. 3 is in a discharge state and the second node QB is in a charged state, multi-output due to a coupling phenomenon is prevented.

That is, as shown in FIG. 4A, the second voltage source V _SS is supplied to the first node Q to maintain the discharge state of the first node Q, and the first voltage source V _DD is discharged. The second node QB is supplied to the second node QB to maintain the charging state.

Accordingly, the pull-up switching device Tru having the gate terminal connected to the first node Q is turned off, and the pull-down switching device Trd having the gate terminal connected to the second node QB is turned on. -Turned on. Therefore, the third voltage source V _GL is supplied to the corresponding gate line through the turned-on pull-down switching element Trd.

In this case, the second voltage source V _SS is supplied to the gate terminal of the pull-up switching element Tru, the second clock pulse is supplied to the drain terminal, and the third voltage source V _GL is supplied to the source terminal. This is the supplied state. Here, since the second voltage source V _SS is smaller than the third voltage source V _GL , the gate-source terminal voltage V _{GS of} the pull-up switching device Tru represents a value less than zero. Meanwhile, since the second voltage source V _SS and the third voltage source V _GL have the same size, the voltage V _GS between the gate and source terminals of the pull-up switching device Tru is maintained at zero. . As a result, the gate of the pull-up switching device (Tru) according to the present invention - the source terminal between the voltage (V _GS) is a gate of a conventional pull-up switching device (Tru) - it shows a value smaller than the inter-source terminal voltage (V _GS).

In this state, it is assumed that the gate terminal of the pull-up switching device Tru increases to a coupling voltage of a predetermined magnitude according to the coupling phenomenon. Since the source terminal between the voltage (V _GS) is zero, the gate, by the coupling voltage-Conventionally, the gate of the pull-up switching device (Tru) voltage (V _GS) between the source terminal of said pull-up switching device (Tru) Easily exceeds the threshold voltage. However, in the present invention, since the voltage V _GS between the gate and source terminals of the pull-up switching element is maintained as negative, the voltage V _GS between the gate and source terminals is caused by the coupling voltage. It cannot easily exceed the threshold voltage of (Tru). That is, when a coupling voltage having the same magnitude is supplied to the first node Q by the coupling phenomenon, the pull-up switching device Tru of the present invention is turned on even if the conventional pull-up switching device Tru is turned on. -It won't come on.

FIG. 4B is a view for explaining that when the first node Q of FIG. 3 is in a charged state and the second node QB is in a discharged state, multi-output due to a coupling phenomenon is prevented.

That is, as shown in FIG. 4B, the first voltage source V _DD is supplied to the first node Q so that the first node Q is maintained in a charged state, and the second voltage source V _SS is _discharged . The second node QB is supplied to the second node QB to maintain the discharge state.

Accordingly, the pull-up switching device Tru having the gate terminal connected to the first node Q is turned on, and the pull-down switching device Trd having the gate terminal connected to the second node QB is turned on. -Is off. Therefore, the second clock pulse CLK2 is supplied as a scan pulse to the corresponding gate line through the turned-on pull-up switching device Tru.

Here, since the pull-up switching device Tru source source terminal is connected to the source terminal of the pull-down switching device Trd, the second clock pulse CLK2 is also supplied to the drain terminal of the pull-down switching device Trd. Accordingly, the second voltage source V _SS is supplied to the gate terminal of the pull-down switching device Trd, the second clock pulse CLK2 is supplied to the drain terminal, and the third voltage source V _GL ) is supplied. Here, since the second voltage source V _SS is smaller than the third voltage source V _GL , the gate-source terminal voltage V _{GS of} the pull-down switching device Trd represents a value less than zero. Meanwhile, since the second voltage source V _SS and the third voltage source V _GL have the same size, the voltage V _GS between the gate and source terminals of the pull-down switching device Trd is maintained at 0. . As a result, the gate of the pull-down switching element (Trd) of the present invention - the source terminal between the voltage (V _GL) is the gate of a conventional pull-up switching device (Tru) - it indicates a value smaller than the inter-source terminal voltage (V _GL).

In this state, it is assumed that the gate terminal of the pull-down switching device Trd is raised to a coupling voltage of a predetermined magnitude according to the coupling phenomenon. In the related art, since the voltage V _GS between the gate and source terminals of the pull-down switching device Trd is 0, the voltage V _GS between the gate and source terminals is thresholded by the pull-down switching device Trd by the voltage. The voltage is easily exceeded. However, in the present invention, since the voltage V _GS between the gate and source terminals of the pull-down switching element Trd remains negative, the voltage V _GS between the gate and source terminals is maintained in the pull-down switching element Trd. Does not easily exceed the threshold voltage. That is, when the coupling voltage of the same magnitude is supplied to the second node QB by the coupling phenomenon, the pull-down switching device Trd of the present invention is turned on even though the conventional pull-down switching device Trd is turned on. -It won't come on.

Meanwhile, referring to FIG. 5, the circuit configurations of the node controller 300a and the output unit 300b included in the second stage BST2 will be described below.

The node control unit 300a includes first to sixth switching elements Tr1 to Tr6.

The first switching element Tr1 charges the first node Q to the first voltage source V _DD in response to the scan pulse from the previous stage. That is, the first switching element Tr1 of the second stage BST2 may turn the first node Q to the first voltage source V _DD in response to the first scan pulse Vout1 from the first stage BST1. ) To this end, the gate terminal of the first switching element Tr1 is connected to the output part 300b of the first stage BST1, and the drain terminal is connected to a power line for transmitting the first voltage source V _DD . The source terminal is connected to the first node Q.

The second switching element Tr2 discharges the second node QB to the second voltage source V _SS in response to the scan pulse from the previous stage. That is, in response to the first scan pulse Vout1 from the first stage BST1, the second switching element Tr2 of the second stage BST2 connects the second node QB to the second voltage source ( V _SS ). To this end, the gate terminal of the second switching element Tr2 is connected to the output part 300b of the first stage BST1, the drain terminal is connected to the second node QB, and the source terminal is connected to the second terminal QB. It is connected to a power supply line that transmits a voltage source V _SS .

The third switching element Tr3 charges the second node QB to the first voltage source V _DD in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the third switching element Tr3 of the second stage BST2 is connected to the third clock pulse CLK3 (a clock pulse synchronized with the third scan pulse Vout3 output from the third stage BST3). In response, the second node QB is charged with the first voltage source V _DD . To this end, a gate terminal of the third switching element Tr3 is connected to a clock line for transmitting the third clock pulse CLK3, and a drain terminal is connected to a power line for transmitting the first voltage source V _DD . The source terminal is connected to the second node QB.

The fourth switching element Tr4 discharges the first node Q to the second voltage source V _SS in response to the first voltage source V _DD charged in the second node QB. To this end, the gate terminal of the fourth switching element Tr4 is connected to the second node QB, the drain terminal is connected to the first node Q, and the source terminal is the second voltage source V _SS . It is connected to the power line to transmit it.

The fifth switching element Tr5 discharges the second node QB to the second voltage source V _SS in response to the first voltage source V _DD charged in the first node Q. To this end, the gate terminal of the fifth switching element Tr5 is connected to the first node Q, the drain terminal is connected to the second node QB, and the source terminal is connected to the second voltage source V _SS . It is connected to the power line to transmit.

The sixth switching element Tr6 discharges the first node Q to the second voltage source V _SS in response to the scan pulse output from the next stage. That is, the sixth switching device Tr6 discharges the first node Q to the second voltage source V _SS in response to the third scan pulse from the third stage BST3. To this end, the gate terminal of the sixth switching element Tr6 is connected to the output part 300b of the third stage BST3, the drain terminal is connected to the first node Q, and the source terminal is connected to the first node. 2 is connected to a power supply line that transmits a voltage source V _SS .

The output unit 300b includes a pull-up switching element Tru and a pull-down switching element Trd.

The pull-up switching device Tru has a clock pulse width greater than that of the clock pulse applied to the gate terminal of the third switching device Tr3 in response to the first voltage source V _DD charged in the first node Q. Output the preceding clock pulse. That is, the pull-up switching device Tru outputs the second clock pulse CLK2 that is one pulse width ahead of the third clock pulse CLK3. The output second clock pulse CLK2 is supplied to the gate line connected to the stage to which it belongs, the stage of the previous stage, and the stage of the next stage. That is, the pull-up switching device Tru of the second stage BST2 outputs the second clock pulse CLK2 as a second scan pulse Vout2 for driving the second gate line. The second scan pulse Vout2 is supplied to the second gate line, the first stage BST1, and the third stage BST3. For this purpose, the gate terminal of the pull-up switching device Tru is connected to the first node Q, the source terminal is connected to the clock line for transmitting the second clock pulse CLK2, and the source terminal is connected to the second terminal. The gate line, the first stage BST1, and the third stage BST3 are commonly connected. Here, the second scan pulse Vout2 supplied to the first stage BST1 disables the first stage BST1, and the second scan pulse Vout2 supplied to the third stage BST3 is The third stage BST3 is enabled.

The pull-down switching device Trd outputs a third voltage source V _GL in response to the first voltage source V _DD charged in the second node QB. The third voltage source V _{GL is} supplied to the gate line connected to the stage to which it belongs, the stage of the previous stage, and the stage of the next stage. That is, the pull-down switching device Trd supplies the third voltage source V _GL to the second gate line, the first stage BST1, and the third stage BST3. The third voltage source V _GL supplied to the second gate line functions as a signal for deactivating the second gate line. To this end, a gate terminal of the pull-down switching device Trd is connected to the second node QB, and a source terminal is common to the second gate line, the first stage BST1, and the third stage BST3. The drain terminal is connected to a power supply line for transmitting the third voltage source V _GL .

On the other hand, the first stage BST1, the third to nth stages BST3 to BSTn, and the dummy stage BSTn + 1 also have the same configuration as the above-described second stage BST2.

However, since the stage before the first stage BST1 does not exist from the first stage BST1, the first switching element Tr1 included in the first stage BST1 receives the start pulse SP from the timing controller. To be supplied. That is, the first switching device Tr1 provided in the first stage BST1 transfers the first node Q to the first voltage source V _DD in response to the start pulse SP from the timing controller. Charge it. In addition, the second switching element Tr2 included in the first stage BST1 also receives the start pulse SP from the timing controller. That is, the second switching element Tr2 included in the first stage BST1 transfers the second node QB to the second voltage source V _SS in response to the start pulse SP from the timing controller. Discharge.

Further, for the same reason as described above, the drain terminal of the pull-up switching device Tru provided in the first stage BST1 is commonly connected to the first gate line and the first stage BST1, and the pull-down switching device Trd Is connected to the first gate line and the second stage BST2 in common.

There is no stage in the next stage of the dummy stage BSTn + 1. In addition, the dummy stage BSTn + 1 supplies the n + 1th scan pulse outputted from the dummy stage BSTn + 1 to a previous stage (that is, the nth stage BSTn) to disable the nth stage BSTn. Function Accordingly, the drain terminal of the pull-up switching device Tru provided in the dummy stage BSTn + 1 is connected to the nth stage BSTn, and the source terminal of the pull-down switching device Trd provided in the dummy stage is also the same. It is connected to the nth stage BSTn.

And. Bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), and the like may be used as the switching device.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

As described above, the shift register according to the present invention has the following effects.

The shift register according to the present invention can reduce the occurrence of multiple outputs in the pull-up and pull-down switching elements by varying the magnitudes of the voltages for discharging the first and second nodes and the voltages supplied to the source terminals of the pull-down transistors.

Claims (5)

  A shift register having a plurality of stages that sequentially output scan pulses for driving a gate line of a liquid crystal panel, Each stage, A node controller having a first node and a second node, and selectively outputting a first voltage source or a second voltage source externally input to the first and second nodes to charge or discharge the first and second nodes; A pull-up switching device configured to output a clock pulse input to the gate line as a scan pulse according to a charge or discharge state of the first node; And, And a pull-down switching element configured to output a third voltage source to the gate line according to a charging or discharging state of the second node, wherein the second voltage source is different from the third voltage source. The method of claim 1, And the voltage of the second voltage source is smaller than the voltage of the third voltage source. The method of claim 1, And a first stage outputting a scan pulse first among the stages outputs the scan pulse in response to a start pulse outputted once per frame from a timing controller. The method of claim 1, Node control unit of each stage, A first switching element for charging a first node with a first voltage source in response to the start pulse or a scan pulse from a previous stage; A second switching element for discharging a second node to a second voltage source in response to the start pulse or a scan pulse from a previous stage; A third switching element configured to charge the second node with a first voltage source in response to a first clock pulse synchronized with a scan pulse output from the next stage; A fourth switching element configured to discharge the first node to a second voltage source in response to the first voltage source charged in the second node; A fifth switching element configured to discharge the second node to a second voltage source in response to the first voltage source charged in the first node; And, And a sixth switching element for discharging said first node to a second voltage source in response to a scan pulse from a next stage. The method of claim 4, wherein And the pull-up switching element, the pull-down switching element, and the first to sixth switching elements are one of a bipolar junction transistor (BJT) and a metal oxide semiconductor field effect transistor (MOSFET).

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