KR20070007468A - The manufacturing method of a semiconductor device. - Google Patents

Abstract

In the method of manufacturing a semiconductor device, a mask pattern having a first pitch is first formed on a substrate. A dummy pattern is formed on sidewalls of the first mask pattern. A second mask layer is formed to fill the first mask pattern and the dummy pattern. A second mask pattern is formed by polishing the second mask layer to expose the first mask pattern and the dummy pattern upper surface. The dummy pattern is removed to expose a portion of the substrate. A recess is formed by partially etching the exposed substrate using the first and second mask patterns as an etching mask. A gate oxide film is formed continuously on the surface of the substrate and the recess portion. A gate electrode is formed on the gate oxide layer and has a second pitch that is 1/2 of the first pitch to fill the recess. In the case of the transistor manufactured by the above method, the channel length is longer than the gate line width, and the operation characteristics are good.

Description

A method for manufacturing a semiconductor device.

1 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

100 semiconductor substrate 106 first mask film

106a: first mask pattern 107: first photoresist pattern

108: dummy film 108a: dummy pattern

110: second mask film 110a: second mask pattern

112: opening 113: recessed portion

114: gate oxide film 116a: first conductive film pattern

118: second conductive film pattern 119: gate electrode

120a: hard mask pattern 122: second hard mask pattern

124: spacer 124: source / drain

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a recessed gate electrode.

In recent years, as semiconductor devices have become highly integrated, the line width of the pattern and the distance between the pattern and the pattern have also become very small. In particular, the line width of the gate electrode of a transistor mainly formed on a substrate during manufacture of a semiconductor device is very small.

Due to the reduction in the line width of the gate electrode, it is more difficult to secure the operating characteristics of the transistor. In particular, in the case of the DRAM device, a problem such as the deterioration of the refresh characteristics due to the increase of the leakage current is seriously generated.

In order to overcome the above problems, researches such as changing the structure of the gate electrode from the planar type to the recess type have been continuously conducted. As described above, when the structure of the gate electrode is formed in the recess type, the channel path between the source and the drain becomes long, so that the leakage current may be reduced, thereby improving the refresh characteristic.

Meanwhile, in order to form the recessed gate electrode structure, a recess portion having an inner width smaller than the line width of the gate electrode should be formed. However, since the line width of the gate electrode is close to the limit of the current exposure equipment, in order to form a recess having an inner width smaller than the line width of the gate electrode, the thermal resistance of the photoresist is patterned after patterning with the current exposure equipment. A process is advanced by performing a flow process, a chemical addition process, etc. However, when the inner width of the recess portion is reduced through the subsequent processing as described above, it is difficult to expect reproducibility of the inner width of the recess portion, and problems such as the recess portion not being formed normally or the position of the recess portion are shifted continuously. Will occur.

Accordingly, there is a need for a method of manufacturing a semiconductor device having a recessed gate electrode capable of securing leakage current characteristics and refresh characteristics while reducing defects caused by a photo process.

It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device having a recessed gate electrode which can increase the process margin.

As a method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object, a first mask pattern having a first pitch is first formed on a substrate. A dummy pattern is formed on sidewalls of the first mask pattern. A second mask layer is formed to fill the first mask pattern and the dummy pattern. A second mask pattern is formed by polishing the second mask layer to expose the first mask pattern and the dummy pattern upper surface. The dummy pattern is removed to expose a portion of the substrate. A recess is formed by partially etching the exposed substrate using the first and second mask patterns as an etching mask. A gate oxide film is formed continuously on the surface of the substrate and the recess portion. Next, a gate electrode is formed on the gate oxide film to fill the recess with a second pitch that is 1/2 of the first pitch.

According to the above process, by forming the first mask pattern having a pitch of 1/2 of the pitch of the gate electrode, a recess portion having an inner width smaller than that of the gate electrode can be formed.

In addition, since the inner width of the recess is determined by the line width of the dummy pattern, the inner width of the recess may be adjusted by adjusting the deposition thickness of the dummy pattern. For this reason, the recessed part which has an internal width smaller than the limit line width of the photoresist pattern which can be formed by a current photography process can be formed.

In addition, by forming the recess portion, the channel path becomes longer than the line width of the gate electrode, thereby reducing leakage current, thereby improving refresh characteristics.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, patterns or structures are shown in greater detail than actual for clarity of the invention. In the present invention, when referred to as being formed "on", "upper" or "under", "lower" of an object, it may be formed while directly contacting the upper or lower surface of the object. In the state where additional structures are formed on the object, the object may be formed above or below the object.

1 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. In this embodiment, a method of manufacturing a cell transistor of a DRAM device will be described.

Referring to FIG. 1, an isolation region pattern 102 is formed on a semiconductor substrate 100 to distinguish between an active region and a field region.

More specifically, first, a pad oxide film (not shown) and a device isolation hard mask film (not shown) are formed on a semiconductor substrate. The pad oxide film is interposed between the device isolation hard mask film and the substrate to relieve stress generated when the device isolation hard mask film contacts the substrate. The pad oxide layer may be formed using silicon oxide. The hard mask layer for device isolation may be formed using silicon nitride.

Next, a photolithography process is performed to pattern the device isolation hard mask layer to form a device isolation hard mask pattern (not shown). The semiconductor substrate 100 is etched using the device isolation hard mask pattern as an etching mask to form the device isolation trench 103.

A trench inner wall oxide film (not shown) is formed on side and bottom surfaces of the device isolation trench 103. A nitride film liner (not shown) is formed on surfaces of the trench inner wall oxide layer (not shown) and the device isolation hard mask pattern.

Next, an insulating film is deposited to fill the inside of the isolation trench 103, and the insulating film pattern 102 is completed by polishing the insulating film. Examples of the insulating film that can be used include HDP oxide film, thermal oxide film, TEOS film or USG film. The insulating film may be formed alone, or may be formed by stacking two or more.

Thereafter, the hard mask pattern for device isolation is removed. Through the above process, the substrate is divided into an active region and a field region.

The first mask film 106 is formed on the substrate. The first mask layer 106 is formed using a material having an etching selectivity different from that of the semiconductor substrate 100. The first mask layer 106 is formed using a material having a property that the first mask layer 106 is hardly etched when the semiconductor substrate is etched. In detail, the first mask layer 106 may be formed using silicon oxide or silicon nitride.

A photoresist film (not shown) is coated on the first mask film 106. An exposure and development process is performed on the photoresist film to form a first photoresist pattern 107 that selectively masks a region where a first mask pattern is to be formed. Here, the first mask pattern defines the position of the recess portion of the gate electrode. In detail, the recesses are positioned at both sides of the first mask pattern.

The first photoresist pattern 107 is disposed to have a first pitch P1. The first pitch is twice the pitch of the target gate electrode (hereinafter referred to as second pitch). As described above, since the first photoresist pattern 107 is formed at twice the pitch of the gate electrode, the process margin during the photolithography process for forming the recess portion is greatly increased.

Referring to FIG. 2, a first mask pattern 106a is formed by etching the first mask layers (FIGS. 1 and 106) using the first photoresist pattern 107 as an etching mask. In this case, the first mask pattern 106a is disposed to have the first pitch P1.

Next, the first photoresist pattern 107 is removed through an ashing and stripping process.

In the present embodiment, the first mask pattern 106a is formed to have a line shape that crosses the active region in the first direction. However, it is noted that the first mask pattern 106a may be formed to have an isolated pattern shape that traverses the active region in the first direction.

Referring to FIG. 3, a dummy layer 108 is formed on the surface of the first mask pattern 106a and the semiconductor substrate 100 in succession. The dummy layer 108 is formed using a material having an etching selectivity different from that of the first mask pattern 106a. In detail, in the process of etching the dummy film 108, the first mask pattern 106a is formed using a material having a property that is hardly etched.

For example, when the first mask pattern 106a is formed of silicon oxide, the dummy film 108 may be formed of silicon nitride. Meanwhile, when the first mask pattern 106a is formed of silicon nitride, the dummy film 108 may be formed of silicon oxide.

In this case, the dummy film 108 deposited on the sidewall of the first mask pattern 106a is preferably deposited to have a thickness substantially equal to the inner width of the target recess. That is, the inner width of the recess portion is determined according to the thickness of the dummy film 108. Therefore, by reducing the thickness of the dummy layer 108, the inner width of the recess portion may be adjusted to be smaller than the limit line width of the photoresist pattern.

Referring to FIG. 4, the dummy layers 108 are formed on sidewalls of the first mask pattern 106a by anisotropically etching the dummy layers FIGS. 3 and 108. The lower line width of the dummy pattern 108a is substantially the same as the deposition thickness of the dummy film 108.

Referring to FIG. 5, a second mask layer is completely embedded in the dummy pattern 108a, the first mask pattern 106a, and the semiconductor substrate 100 to completely fill the dummy pattern 108a and the first mask pattern 106a. Form 110. Preferably, the low stepped portion of the second mask layer 110 is formed to be higher than the top surface of the first mask pattern 106a. In addition, the second mask layer 110 is formed of a material substantially the same as that of the first mask pattern 106a.

Referring to FIG. 6, the second mask pattern may be polished by chemical mechanical polishing to expose the upper surfaces of the dummy pattern 108a and the first mask pattern 106a through a chemical mechanical polishing process. To form 110a. According to the above process, the first mask pattern 106a and the second mask pattern 110a formed of substantially the same material are repeatedly formed, and between the first mask pattern 106a and the second mask pattern 110a are formed. The dummy pattern 108a is interposed in the gap portion.

Referring to FIG. 7, an opening 112 exposing the surface of the semiconductor substrate 100 is formed by selectively removing the dummy pattern 108a.

In the present exemplary embodiment, the first mask pattern 106a, the dummy pattern 108a, and the second mask pattern 110a are formed to have a line shape crossing the active region in the first direction. Therefore, the opening 112 formed by removing the dummy pattern 108a also has a trench shape that crosses the first direction. In this case, as shown in the drawing, not only the active region but also the field region may be partially exposed on the bottom surface of the opening 112.

Referring to FIG. 8, the recess 113 is formed by partially etching the exposed semiconductor substrate 100 using the first and second mask patterns 106a and 110a as an etching mask. The recess 113 has an internal width that is substantially the same as the line width of the dummy pattern 108a. The recess 113 is disposed to have the same pitch as the pitch of the gate electrode (ie, the second pitch).

Next, the first and second mask patterns 106a and 108a are removed. In order to minimize damage to the surface of the semiconductor substrate 100, the removal may be performed by a wet etching process.

Referring to FIG. 9, a gate oxide film 114 is formed on a semiconductor substrate 100 on which a recess 113 is formed.

The gate oxide layer 114 may be formed through a thermal oxidation process. In this case, the gate oxide film 114 is continuously formed on the upper surface of the substrate and the side and bottom surfaces of the recess 113 in the active region, and the gate oxide film 114 is not formed in the field region.

Alternatively, the gate oxide layer 114 may be formed by depositing a metal oxide having a higher dielectric constant than the silicon oxide. At this time, the deposition process may be applied to the chemical vapor deposition process, atomic layer deposition process and the like. In this case, although not shown, the gate oxide film 114 is continuously formed on the upper surface of the substrate and the side and bottom surfaces of the recess 113 in the active region and the field region.

A preliminary first conductive layer (not shown) is deposited on the substrate on which the gate oxide layer 114 is formed so as to completely fill the recess 113. The preliminary first conductive layer may be formed by depositing a polysilicon material doped with impurities through a low pressure chemical vapor deposition (LPCVD) process. The impurity doping may be performed by POCl ₃ diffusion, ion implantation, or in-situ doping. When the polysilicon is deposited through a low pressure chemical vapor deposition (LPCVD) process, the step coverage property is good to fill the preliminary first conductive layer without generating voids in the recess. can do.

Next, by grinding the upper surface of the preliminary first conductive film through a chemical mechanical polishing process, a first conductive film 116 having a flat upper surface is formed.

A second conductive layer 118 having a lower resistance than the first conductive layer 116 is deposited on the first conductive layer 116. In detail, the second conductive layer 118 may be formed using a metal or a metal silicide material.

Next, a hard mask film 120 is formed on the second conductive film 118. The hard mask layer 120 may be formed by depositing silicon nitride.

Referring to FIG. 10, a photoresist film (not shown) is coated on the hard mask layer 120. Next, the second photoresist pattern 122 for patterning the gate electrode is formed by exposing and developing the photoresist film. The hard mask pattern 120a is formed by etching the hard mask layers (FIGS. 9 and 120) using the second photoresist pattern 122 as an etching mask. At this time, the pitch of the hard mask patterns 120a, that is, the second pitch P2 is 1/2 of the first pitch P1.

After this, although not shown, the second photoresist pattern 122 is removed through an ashing and stripping process.

Referring to FIG. 11, the recesses are sequentially etched using the hard mask pattern 120a as an etch mask to sequentially etch the second conductive layers 10 and 118 and the first conductive layers 10 and 116. A gate electrode 119 is formed to fill the inside of the portion 113.

The gate electrode 119 has a shape in which a first conductive layer pattern 116a and a second conductive layer pattern 118a having a lower resistance than the first conductive layer pattern 116a are stacked. At this time, the pitch between the gate electrodes 119, that is, the second pitch P2 is 1/2 of the first pitch.

When the gate electrode 119 is formed as described above, a channel is formed in the completed MOS transistor along sidewalls and bottom surfaces of the recess 113. Therefore, it has a long channel length compared to the line width of the gate electrode, which reduces the short channel effect and leakage current.

Referring to FIG. 12, a spacer nitride layer (not shown) is deposited on the gate electrode 119, the hard mask pattern 120a, and the gate oxide layer 114, and then anisotropically etched to form the gate electrode 119. And a spacer 124 is formed on sidewalls of the hard mask pattern 120a.

Next, by implanting impurities into the substrate on which the gate electrode 119 and the spacer 124 are formed, the source and the drain 126 are formed under the substrate surface on both sides of the gate electrode 119. The source and drain 126 may be disposed to face each other in a second direction perpendicular to the first direction.

According to the method of the present embodiment, a recess portion having an inner width smaller than the line width of the gate electrode can be formed using a mask pattern having a pitch twice the pitch of the gate electrode. Therefore, the margin of the photolithography process can be increased to reduce process defects that may occur at the time of recess formation.

As described above, according to the present invention, a semiconductor device having a long channel length compared to the line width of the gate electrode can be manufactured. As a result, the short channel effect and the leakage current in the MOS transistor of the semiconductor device can be reduced to improve operating characteristics.

In addition, when manufacturing a mask for forming the recess, the photo process margin may be increased, thereby reducing process defects. For this reason, the improvement of the manufacturing yield of a semiconductor device can be anticipated.

Moreover, since the recess portion having an inner width smaller than the limit line width of the photoresist pattern that can be formed by the photolithography process can be formed, a more highly integrated semiconductor device can be manufactured.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (6)

Forming a first mask pattern having a first pitch on the substrate; Forming a dummy pattern on sidewalls of the first mask pattern; Forming a second mask layer to fill the first mask pattern and the dummy pattern; Forming a second mask pattern by polishing the second mask layer to expose the first mask pattern and the dummy pattern upper surface; Removing the dummy pattern to expose a portion of the substrate; Forming a recess by partially etching the exposed substrate using the first and second mask patterns as an etching mask; Continuously forming a gate oxide film on surfaces of the substrate and the recess portion; And And forming a gate electrode on the gate oxide film, the gate electrode having a second pitch of 1/2 of the first pitch and filling the recess. The method of claim 1, wherein the forming of the first mask pattern comprises: Forming a first mask film on the substrate; Forming a photoresist pattern having a first pitch on the first mask film; And And etching the first mask layer by using the photoresist pattern as an etching mask. The method of claim 1, wherein the forming of the dummy pattern comprises: Continuously forming a dummy film on the first mask pattern and the bare semiconductor substrate; And And anisotropically etching the dummy film. The method of claim 1, wherein the dummy film is formed to a thickness thinner than a limit line width of a photoresist pattern that can be formed by a photolithography process. The method of claim 1, wherein the second mask layer is formed of the same material layer as the first mask pattern. The method of claim 1, wherein the forming of the gate electrode comprises: Forming a preliminary first conductive layer filling the recess portion on the substrate; Polishing the preliminary first conductive film to form a first conductive film having an upper surface flattened thereon; Forming a second conductive film having a lower resistance than the first conductive film on the first conductive film; And And patterning the second conductive film and the first conductive film while leaving the conductive film filled in the recess.

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