KR20070003317A - Thin film transistor array panel and liquid crystal display including the same - Google Patents

Abstract

The present invention provides a first and second signal lines that cross each other, a first switching element connected to the first and second signal lines, a first liquid crystal capacitor connected to the first switching element, and the first liquid crystal capacitor. A first storage capacitor connected to the first switching element in parallel, a second switching element connected to the first and second signal lines, a second liquid crystal capacitor connected to the second switching element, and the second A second holding capacitor connected to the second switching element in parallel with the liquid crystal capacitor, wherein the first and second holding capacitors are respectively connected to the first terminal and to the opposite side of the first terminal. A second terminal positioned between said first terminal and said second terminal, said dielectric comprising an insulating film and a semiconductor, said first terminal of said first holding capacitor being said second holding Compared to the first terminal of the electricity it is closer to the liquid crystal display device in the semiconductor. While simplifying the manufacturing process, it is possible to improve visibility by using the change of luminance of each subpixel according to the change of the capacity of the first and second holding capacitors, and the luminance of the two subpixels cancel each other to eliminate the flicker phenomenon to improve the image quality. Can be. In addition, visibility can be improved with existing driving frequencies.

Description

Thin film transistor array panel and liquid crystal display including the same {THIN FILM TRANSISTOR ARRAY PANEL AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of two subpixels of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a layout view of a common electrode panel according to an exemplary embodiment of the present invention.

FIG. 6 is a layout view of a liquid crystal display including the two display panels of FIGS. 4 and 5.

FIG. 7 is a cross-sectional view of the liquid crystal display of FIG. 6 taken along the line VII-VII. FIG.

<Description of Drawing>

11, 21: alignment film 12, 22: polarizing plate

71, 72a, 72b: common electrode cutout 91: gap

81, 82: contact auxiliary member 100: thin film transistor array panel

110 and 210: substrate 121 and 129: gate line

124: gate electrode 131: sustain electrode line

137a and 137b: sustain electrode 140: gate insulating film

154: semiconductor

161, 163, 165a, 165b, 167a, 167b: resistive contact member

171 and 179: data lines 173a and 173b: source electrode

175a, 175b, 177a, 177b: drain electrode

180: shield

18, 182, 185a, 185b, 186, 187: contact holes

188: through hole 191, 191a, 191b: pixel electrode

220: light blocking member 230: color filter

250: overcoat 270: common electrode

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices, and includes two display panels on which an electric field generating electrode such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. The liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to the field generating electrode, thereby determining an orientation of the liquid crystal molecules of the liquid crystal layer and displaying an image by controlling polarization of incident light.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode.

Among such liquid crystal display devices, a liquid crystal display device having a vertically aligned mode in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the liquid crystal display device is gaining attention due to its large contrast ratio and wide reference viewing angle. . Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Specific methods for implementing a wide reference viewing angle in a vertical alignment liquid crystal display include a method of forming an incision in the field generating electrode and a method of forming protrusions on or under the field generating electrode. Since the cutout and the protrusion determine the tilt direction of the liquid crystal molecules, the reference viewing angle can be widened by appropriately arranging them to disperse the inclined directions of the liquid crystal molecules in various directions.

The display panel of such a liquid crystal display may have a layered structure in which a plurality of conductive layers and an insulating layer are stacked. The gate line and the sustain electrode, the amorphous silicon layer of the thin film transistor, the data line, the pixel electrode and the like are made of different conductive layers and separated into insulating layers, and are usually arranged in order from the bottom. The layered structure is manufactured by several photo lithography processes. It is desirable to reduce the number of photo processes to reduce the production cost. To this end, a technology for forming a photosensitive film having a medium thickness and patterning the data line and the amorphous silicon layer together using an etch mask has been developed.

In the display panel made by such a manufacturing method, a conductor mainly made of the same layer as the data line is connected to the pixel electrode and overlapped with the storage electrode made of the same layer as the gate line to form the storage capacitor.

However, since the data line and the amorphous silicon layer are patterned together, it becomes a MOS capacitor (metal oxide semiconductor capacitor) in which amorphous silicon remains under the conductor. These MOS capacitors are characterized in that the capacity of the capacitor is changed according to the polarity and magnitude of the applied voltage, which causes flickering and flickering of the screen and deterioration of image quality.

In addition, the liquid crystal display of the vertical alignment mode is less lateral visibility than the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in severe cases, the luminance difference between the high grays is disappeared, and the picture may be clumped.

One technical problem to be achieved by the present invention is to improve the image quality by eliminating the flicker phenomenon while simplifying the manufacturing process of the display panel of the liquid crystal display device.

Another technical problem to be achieved by the present invention is to improve side visibility.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes first and second signal lines crossing each other, a first switching element connected to the first and second signal lines, and a first liquid crystal connected to the first switching element. A capacitor, a first sustain capacitor connected to the first switching element in parallel with the first liquid crystal capacitor, a second switching element connected to the first and second signal lines, and a second connected to the second switching element A second liquid crystal capacitor, and a second storage capacitor connected to the second switching element in parallel with the second liquid crystal capacitor, wherein the first and second storage capacitors are respectively connected to the switching element. And a second terminal positioned opposite the first terminal, and a dielectric disposed between the first terminal and the second terminal and including an insulating film and a semiconductor, wherein the first holding A first terminal of the electricity is closer to the semiconductor compared to the first terminal of the second storage capacitor.

Second terminals of the first and second storage capacitors may be connected to the same voltage.

The signal applied to the second signal line may be inverted in polarity with respect to the same voltage.

A thin film transistor array panel according to another exemplary embodiment of the present invention includes a substrate, a gate electrode formed on the substrate, a storage electrode formed on the substrate and separated from the gate line, and a capacitance separated from the gate electrode and the storage electrode. A first insulating film formed over an electrode, the sustain electrode, the capacitor electrode, and the first signal line and having a first contact hole for exposing the capacitor electrode; first, second, and third semiconductors formed over the first insulating film A source electrode formed on the first semiconductor; a first drain electrode formed on the first and second semiconductors and separated from the source electrode; and a second drain electrode formed on the first semiconductor. A storage conductor formed over the semiconductor and overlapping the capacitor electrode, and connected to the first drain electrode A first subpixel electrode connected to the second subpixel electrode and a second subpixel electrode connected to the capacitor electrode through the first contact hole, wherein the first sustain electrode and the sustain conductor are connected to each other. Is applied to the common voltage.

The first semiconductor and the second semiconductor may be connected to each other.

The first and second semiconductors have substantially the same planar shape as the source electrode and the first and second drain electrodes except for a portion positioned between the source electrode and the first and second drain electrodes. The three semiconductors may have substantially the same planar shape as the storage conductor.

And a second insulating film formed on the source electrode and the first and second drain electrodes, wherein the second insulating film includes second and third contact holes and the second contact hole exposing the first and second drain electrodes, respectively. And a fourth contact hole connected to a first contact hole, wherein the first and second subpixel electrodes are formed on the second insulating film, and respectively through the second and third contact holes, the first and second drains. The second subpixel electrode may be connected to the capacitive electrode through the first and fourth contact holes.

The holding conductor may have a through hole through which the fourth contact hole passes.

The display device may further include a gate line formed on the substrate and connected to the gate electrode, and a data line formed on the first insulating layer and connected to the source electrode.

The display device may further include a shielding electrode formed on the second insulating layer and overlapping the data line.

The second insulating layer may further have a fifth contact hole exposing the storage conductor, and the shielding electrode may be connected to the storage conductor through the fifth contact hole.

The signal applied to the source electrode may reverse polarity with respect to the common voltage.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. Is an equivalent circuit diagram of two subpixels of the liquid crystal display according to the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of signal lines (not shown) and a plurality of pixels PX connected to the plurality of signal lines (not shown) and arranged in a substantially matrix form when viewed in an equivalent circuit. In contrast, in the structure shown in FIG. 3, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines (not shown) that transmit gate signals (also referred to as "scan signals") and a plurality of data lines (not shown) that transmit data signals. The gate lines extend substantially in the row direction and are substantially parallel to each other, and the data lines extend substantially in the column direction and are substantially parallel to each other.

Referring to FIG. 2, the liquid crystal panel assembly 300 includes a signal line including a plurality of gate lines GL, a plurality of data lines DL, and a plurality of storage electrode lines SL, and a plurality of pixels PX connected thereto. Include.

Each pixel PX includes a pair of subpixels PXa and PXb, and each subpixel PXa / PXb is a switching element Qa / Qb connected to a gate line GL and a data line DL. ) And the liquid crystal capacitor C _LC a / C _LC b connected thereto, and the storage capacitor C _ST a / C _ST b connected to the switching element Qa / Qb and the storage electrode line SL. Include.

Each switching element Qa / Qb is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, and a control terminal thereof is connected to a gate line GLa, and an input terminal is connected to a data line DL. The output terminals are connected to the liquid crystal capacitors C _LC a / C _LC b and the storage capacitors C _ST a / C _ST b.

Referring to FIG. 3, the liquid crystal capacitor C _LC a / C _LC b has a sub-pixel electrode PEa / PEb of the lower panel 100 and a common electrode CE of the upper panel 200 as two terminals. The liquid crystal layer 3 between the pixel electrodes PEa / PEb and the common electrode CE functions as a dielectric. The pair of subpixel electrodes PEa and PEb are separated from each other and form one pixel electrode PE. The common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom. The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

The storage capacitors C _ST a / C _ST b, which serve as an auxiliary role of the liquid crystal capacitors C _LC a / C _LC b, may include the storage electrode lines SL and the subpixel electrodes PEa / PEb provided in the lower display panel 100. ) Is overlapped with the insulator, and a predetermined voltage such as the common voltage Vcom is applied to the storage electrode line SL. However, the storage capacitors C _ST a and C _ST b may be formed such that the subpixel electrodes PEa and PEb overlap the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. 3 illustrates that each pixel PX includes a color filter CF representing one of the primary colors in an area of the upper panel 200 as an example of spatial division. Unlike FIG. 3, the color filter CF may be formed above or below the subpixel electrodes PEa and PEb of the lower panel 100.

Referring back to FIG. 1, the gray voltage generator 800 generates a plurality of gray voltages (or reference gray voltages) related to the transmittance of the pixel PX.

The gate driver 400 is connected to the gate line of the liquid crystal panel assembly 300 to apply a gate signal Vg, which is a combination of a gate-on voltage Von and a gate-off voltage Voff, to the gate line.

The data driver 500 is connected to the data line of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and applies the gray voltage to the data line as a data signal. However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the liquid crystal panel assembly 300 will be described in detail with reference to FIGS. 4 to 7.

4 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 5 is a layout view of a common electrode panel according to an exemplary embodiment of the present invention, and FIG. FIG. 7 is a layout view of a liquid crystal display including a display panel, and FIG. 7 is a cross-sectional view of the liquid crystal display of FIG. 6 taken along the line VII-VII.

4 to 7, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 3 interposed between the two display panels 100 and 200. It includes.

First, the lower panel 100 will be described with reference to FIGS. 4, 6, and 7.

A plurality of gate lines 121, a plurality of storage electrode lines 131, and a plurality of storage electrodes 137b are disposed on an insulating substrate 110 made of transparent glass or plastic. A plurality of gate conductors are formed.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding upward and downward and a wide end portion 129 for connection with another layer or gate driver 400. Each gate electrode 124 includes a first gate electrode 124a protruding upward and a second gate electrode 124b protruding downward. When the gate driver 400 is integrated on the substrate 110, the gate line 121 may extend to be directly connected thereto.

The storage electrode line 131 receives a predetermined voltage such as the common voltage Vcom and extends substantially in parallel with the gate line 121. Each storage electrode line 131 is positioned between two adjacent gate lines 121 and is closer to a lower side of the two gate lines 121. The storage electrode line 131 includes a storage electrode 137a extending up and down. The capacitor electrode 137b is positioned substantially symmetrical with the storage electrode 137a with respect to the gate line 121, and has the same shape and area as the storage electrode 137a. However, shapes and arrangements of the capacitor electrode 137b and the storage electrode line 131 may be modified in various forms.

The gate conductors 121, 131, and 137b may be aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, and molybdenum (Mo). ) And molybdenum-based metals such as molybdenum alloys, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 121, 131, and 137b may be made of various metals or conductors.

Side surfaces of the gate conductors 121, 131, and 137b are inclined with respect to the surface of the substrate 110, and an inclination angle thereof is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 121, 131, and 137b.

On the gate insulating layer 140, a plurality of linear semiconductors 151 and a plurality of island semiconductors 157b made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) or polysilicon, etc. Formed. The linear semiconductor 151 mainly extends in the longitudinal direction and includes a plurality of protrusions 154 extending toward the gate electrode 124, each protrusion 154 having an upper first protrusion 154a and a lower first protrusion 154. Two projections 154b. The island-like semiconductor 157b mostly overlaps the capacitor electrode 137b.

A plurality of linear and island ohmic contacts 161, 165a, 165b, and 167b are formed on the semiconductors 151 and 157b. The ohmic contacts 161, 165a, 165b, and 167b may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide.

The linear ohmic contact 161 mainly extends in the vertical direction and intersects the gate line 121 and the storage electrode line 131. Each linear ohmic contact 161 has a plurality of protrusions 163 extending toward the gate electrode 124. Each of the protrusions 163 protrudes up and down again to form an English letter H and is approximately vertically symmetrical.

The islands of ohmic contact 165a and 165b face the protrusion 163 of the linear ohmic contact 161 about the first and second protrusions 154a and 154b of the semiconductor 151. The island-like ohmic contact 165a extends upward toward the sustain electrode 137a starting from one rod-shaped end surrounded by the protrusion 163, and includes an extension 167a overlapping the sustain electrode 137a. The island-like ohmic contact 165b includes a wide end and a rod-shaped other end surrounded by the protrusion 163 of the linear ohmic contact 161. The islands of ohmic contact 167b are separated from the islands of linear and islands ohmic contact 161, 165a, and 165b, and are located on islands of semiconductor 157b.

Side surfaces of the semiconductors 151 and 157b and the ohmic contacts 161, 165a, 165b, and 167b are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175a and 175b are disposed on the ohmic contacts 161, 165a, 165b, and 167b and the gate insulating layer 140. And a plurality of sustain conductors 177b.

The data line 171 transmits a data signal, overlaps the linear ohmic contact 161, mainly extends in a vertical direction, and crosses the gate line 121 and the storage electrode line 131. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and a wide end portion 179 for connection with another layer or the data driver 500. Each source electrode 173 includes first and second source electrodes 173a and 173b that protrude upward and downward to form the letter H. When the data driver 500 is integrated on the substrate 110, the data line 171 may extend to be directly connected to the data driver 500.

The first and second drain electrodes 175a and 175b and the storage conductor 177b are separated from each other and also separated from the data line 171.

The first and second drain electrodes 175a and 175b face the first and second source electrodes 173a and 173b with respect to the first and second gate electrodes 124a and 124b. The first drain electrode 175a extends upward toward the storage electrode 137a starting from one rod-shaped end surrounded by the first source electrode 173a, and extends an extension 177a overlapping the storage electrode 137a. Include. The second drain electrode 175b includes one wide end portion and the other rod-shaped end portion surrounded by the second source electrode 173b. The storage conductor 177b overlaps the capacitor electrode 137b.

The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are the first and second electrodes of the linear semiconductor 151. Together with the protrusions 154a and 154b, the first and second thin film transistors TFTs Qa / Qb are formed, and the channels of the first and second thin film transistors Qa / Qb are firstly formed. It is formed in the first / second protrusions 154a / 154b between the second source electrodes 173a / 173b and the first / second drain electrodes 175a / 175b.

The data conductors 171, 175a, 175b, and 177b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive material. It may have a multilayer structure including a film (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer, aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data conductors 171, 175a, 175b, and 177b may be made of various other metals or conductors.

The data conductors 171, 175a, 175b, and 177b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161, 165a, 165b, and 167b exist only between the semiconductors 151 and 157b below and the data conductors 171, 175a, 175b, and 177b thereon, and the ohmic contacts 161, 165a. 165b) lowers the contact resistance between them. The semiconductors 151, 157b have substantially the same planar shape as the data conductors 171, 175a, 175b, and 177b and the ohmic contacts 161, 165a, 165b, and 167b thereunder. However, the protrusions 154a and 154b of the linear semiconductor 151 may have data conductors 171, 175a, 175b, and 177b and the ohmic contact members therebetween, such as between the source electrodes 173a and 173b and the drain electrodes 175a and 175b. (161, 165a, 165b, 167b) has an exposed portion.

In the method of manufacturing such a thin film transistor according to an exemplary embodiment of the present invention, the data conductors 171, 175a, 175b, and 177b, the semiconductors 151, 157b, and the ohmic contacts 161, 165a, 165b, and 167b may be used. Form by the photographic process of burn.

The photosensitive film used in such a photo process differs in thickness according to a position, and especially includes a 1st part and a 2nd part in order of decreasing thickness. The first part is located in the wiring area occupied by the data conductors 171, 175a, 175b, and 177b, and the second part is located in the channel area of the thin film transistors Qa / Qb.

There may be various methods of varying the thickness of the photoresist film according to the position. For example, a method of providing a translucent area in addition to a light transmitting area and a light blocking area in a photomask is possible. have. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photosensitive film with a conventional exposure mask having only a light transmitting area and a light blocking area, and then reflowing to allow the photosensitive film to flow down into a region where no light remains.

In this way, a one-time photographic process can be reduced, thereby simplifying the manufacturing method.

A passivation layer 180 is formed on the data conductors 171, 175a, 175b, and 177b and the exposed portion of the semiconductor 151. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. The organic insulator preferably has a dielectric constant of 4.0 or less, and may have photosensitivity. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portions of the semiconductors 154a and 154b while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 may include a plurality of contact holes exposing the end portion 179 of the data line 171, the extended portion 177a of the first drain electrode 175a, and the wide end portion of the second drain electrode 175b, respectively. contact holes 182, 185a, and 185b, a plurality of contact holes 187 exposing the sustain conductor 177b, and a through hole 188 disposed over the capacitor electrode 137b to expose the gate insulating layer 140, have. In addition, the passivation layer 180 and the gate insulating layer 140 are located in the plurality of contact holes 181 exposing the end portion 129 of the gate line 121 and the plurality of contacts positioned in the through hole 188 and exposing the capacitor electrode 137b. The hole 186 is formed.

A plurality of pixel electrodes 191, a plurality of shielding electrodes 88, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

Each pixel electrode 191 has four peripheral sides substantially parallel to the gate line 121 or the data line 171 and has a substantially rectangular shape in which the left corner is chamfered. The hypotenuse of the pixel electrode 191 forms an angle of about 45 ° with respect to the gate line 121.

Each pixel electrode 191 includes a pair of first and second subpixel electrodes 191a and 191b divided with a gap 91 therebetween. The gap 91 includes upper and lower diagonal portions extending from the upper right and lower corners of the pixel electrode 191 toward the left side and vertical portions connecting them. Upper and lower oblique portions of the gap 91 form about 45 ° with the gate line 121 and are substantially perpendicular to each other. Accordingly, as long as the first subpixel electrode 191a becomes an isosceles trapezoid rotated by approximately right angles, and the second subpixel electrode 191b is rotated by approximately 45 ° facing the hypotenuse of the first subpixel electrode 190a. The pair includes a trapezoidal portion and a vertical portion facing the left side of the first subpixel electrode 190a. The pixel electrode 191 and the gap 91 have approximately inversion symmetry with respect to the gate line 121. Hereinafter, for convenience of explanation, the gap 91 is also expressed as a cutout.

The first and second subpixel electrodes 191a and 191b are physically and electrically connected to the first and second drain electrodes 175a and 175b through the contact holes 185a and 185b and the first and second drain electrodes. The data voltage is applied from 175a / 175b. In addition, the capacitor electrode 137b is physically and electrically connected to the second subpixel electrode 191b through the contact hole 186 to receive the same data voltage as the second subpixel electrode 191b.

The shielding electrode 88 receives a common voltage, extends while completely covering the data line 171 along the data line 171, and includes a protrusion 89 extending toward the storage conductor 177b. The shielding electrode 88 blocks electromagnetic interference between the data line 171 and the pixel electrode 191 and between the data line 171 and the common electrode 270 to prevent voltage distortion and the data line 171 of the pixel electrode 191. Reduces the signal delay of the data voltage delivered by

The first and second subpixel electrodes 191a and 191b and the common electrode 270 of the upper panel 200 have a first and second liquid crystal capacitors C _LC a / C together with portions of the liquid crystal layer 3 therebetween. _LC b) is applied to maintain the applied voltage even after the thin film transistors Qa / Qb are turned off.

The storage conductor 177b is physically and electrically connected to the shielding electrode 88 through the contact hole 187 and receives a common voltage from the shielding electrode 88. The first subpixel electrode 191a is sequentially extended from the bottom of the first drain electrode 175a with the gate insulating layer 140, the semiconductor 157a, the ohmic contact member 167a, and the passivation layer 180 interposed therebetween. 177a sequentially forms the first storage capacitor C _ST a by overlapping the storage electrode 137a with the gate insulating layer 140, the semiconductor 157a, and the ohmic contact 167a interposed therebetween. In addition, the capacitor electrode 137b connected to the second subpixel electrode 191b is sequentially interposed from the bottom with the gate insulating layer 140, the semiconductor 157b, and the ohmic contact member 167b interposed therebetween, and the second subpixel electrode 191b. ) Forms a second storage capacitor C _ST b by overlapping the storage conductor 177b with the passivation layer 180 therebetween. The first / second holding capacitors C _ST a / C _ST b enhance the voltage holding capability of the first / second liquid crystal capacitors C _LC a / C _LC b.

As shown in FIGS. 4 to 7, the first / second storage capacitors C _ST a / C _ST b are extended portions of the storage electrode 137a / capacitive electrode 137b and the first drain electrode 175a. The 177a / holding conductor 177b overlaps the gate insulating film 140 with the semiconductors 157a / 157b interposed therebetween as a dielectric. That is, the first storage capacitor C _ST a has the first drain electrode 175a as the upper terminal and the storage electrode 137a as the lower terminal, and the upper terminal is adjacent to the semiconductor 157a, and the lower terminal is the gate insulating film ( Adjacent to 140). The second storage capacitor C _ST b has the storage conductor 177b as the upper terminal and the capacitor electrode 137b as the lower terminal, and the upper terminal is adjacent to the semiconductor 157b, and the lower terminal is connected to the gate insulating layer 140. Adjacent. The data voltage is applied to the upper terminal of the first storage capacitor C _ST a and the common voltage Vcom is applied to the lower terminal, and conversely, the common voltage Vcom is applied to the upper terminal of the second storage capacitor C _ST b. Since the data voltage is applied to the lower terminals, the polarities of the voltages applied to the semiconductors 157a and 157b and the adjacent terminals are opposite to each other, so that the capacitances of the first and second storage capacitors C _ST a and C _ST b are reversed. This one becomes larger and the other smaller.

Therefore, the leakage current is changed and the voltages of the first and second liquid crystal capacitors C _LC a and C _LC b are maintained differently according to the change in capacitance of the first and second storage capacitors C _ST a and C _ST b. do.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 and the external device.

Next, the upper panel 200 will be described with reference to FIGS. 5 to 7.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass, plastic, or the like. The light blocking member 220 has a plurality of through holes 225 facing the pixel electrode 191 and having substantially the same shape as the pixel electrode 191, and prevents light leakage between the pixel electrodes 191. However, the light blocking member 22 may include a portion corresponding to the gate line 121 and the data line 171 and a portion corresponding to the thin film transistor.

A plurality of color filters 230 is also formed on the substrate 210 and the light blocking member 220. The color filter 230 is mostly present in an area surrounded by the light blocking member 230, and may extend long along the column of pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be made of an (organic) insulator, which prevents the color filter 230 from being exposed and provides a flat surface. The overcoat 250 may be omitted.

The common electrode 270 is formed on the overcoat 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO and has a plurality of cutouts 71, 72a, and 72b.

One set of cutouts 71, 72a, and 72b includes a central cutout 71, a lower cutout 72a, and an upper cutout 72b facing one pixel electrode 191. Each of the cutouts 71, 72a, and 72b is disposed between the cutout 91 of the pixel electrode 191 and the side of the cutout side or the pixel electrode 191. In addition, each of the cutouts 71, 72a, and 72b includes at least one diagonal line extending in parallel with the upper diagonal line or the lower diagonal line of the cutout 91 of the pixel electrode 191, with respect to the gate line 121. It is almost inverted symmetrical.

Each of the lower and upper cutouts 72a and 72b includes an oblique portion, a horizontal portion and a vertical portion. The diagonal portion extends from the upper side or the lower side of the pixel electrode 191 to the left side. The horizontal part and the vertical part extend from each end of the oblique part along the sides of the pixel electrode 191 while overlapping the sides and form an obtuse angle with the oblique part.

The central cutout 71 includes a central transverse portion, a pair of oblique portions and a pair of longitudinal longitudinal portions. The central horizontal portion extends from the left side of the pixel electrode 191 to the right along the horizontal center line of the pixel electrode 191. The pair of diagonal portions form an obtuse angle with the central horizontal portion from the end of the central horizontal portion toward the right side of the pixel electrode 191 and extends substantially parallel to the lower and upper cutouts 72a and 72b, respectively. The vertical longitudinal portion extends along the right side of the pixel electrode 191 from the end of the diagonal line and overlaps the right side, and forms an obtuse angle with the diagonal line.

The number of cutouts 71, 72a, and 72b may vary depending on design factors, and the light blocking member 220 overlaps the cutouts 71, 72a and 72b so that light leakage near the cutouts 71, 72a and 72b may be generated. You can block.

Alignment layers 11 and 21 are formed on inner surfaces of the display panels 100 and 200, and they may be vertical alignment layers.

Polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, and the polarization axes of the two polarizers 12 and 22 may be perpendicular to each other, and the lower and upper diagonal lines of the cutout 91 may be perpendicular to each other. It is preferable to make an angle of approximately 45 ° with the oblique portions of the portions and the cut portions 71, 72a, 72b. In the case of a reflective liquid crystal display, one of the two polarizers 12 and 22 may be omitted. In the case of the orthogonal polarizer, incident light entering the liquid crystal layer 3 having no electric field is blocked.

The liquid crystal display according to the present exemplary embodiment may further include a phase retardation film (not shown) for compensating for the delay of the liquid crystal layer 3. The liquid crystal display may also include a polarizer 12 and 22, a phase retardation film, display panels 100 and 200, and a backlight unit (not shown) for supplying light to the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

The cutouts 71, 72a, 72b may be replaced by protrusions (not shown) or depressions (not shown). The protrusions may be made of organic or inorganic materials and may be disposed above or below the field generating electrodes 191 and 270.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 applies the input image signals R, G, and B to the operating conditions of the liquid crystal panel assembly 300 and the data driver 500 based on the input image signals R, G, and B and the input control signal. After properly processing and generating the gate control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal ( DAT) is output to the data driver 500. The output video signal DAT has a predetermined number (or gradation) as a digital signal.

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of transmission of image data to a group of subpixels, a load signal LOAD and a data clock signal for applying a data signal to the liquid crystal panel assembly 300. (HCLK). The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " RVS) may be further included.

In accordance with the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the group of subpixels PXa and PXb and receives the respective digital image signals DAT. By converting the digital image signal DAT into an analog data signal by selecting a gray scale voltage corresponding to the?

The gate driver 400 applies a gate-on voltage Von to the gate line according to the gate control signal CONT1 from the signal controller 600 to turn on the switching elements Qa and Qb connected to the gate line. Then, the data signal applied to the data line is applied to the corresponding subpixels PXa and PXb through the switching elements Qa and Qb turned on.

4 to 7, although the first subpixel electrode 191a and the second subpixel electrode 191b constituting one pixel electrode 191 are connected to respective switching elements Qa and Qb, each switching element Qa and Qb are connected to the same gate line 121 and the same data line 171 to receive substantially the same data voltage.

In this way, when a potential difference occurs between both ends of the first or second liquid crystal capacitors C _LC a and C _LC b, a primary electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated. Is generated). [Hereinafter, the pixel electrode 190 and the common electrode 270 will be referred to as "field generating electrodes." The angle of inclination is perpendicular, and the degree of change in polarization of incident light in the liquid crystal layer 3 varies according to the degree of inclination of the liquid crystal molecules. This change in polarization is represented by a change in transmittance by the polarizer, through which the liquid crystal display displays an image.

The angle at which the liquid crystal molecules are tilted depends on the intensity of the electric field. As described above, the capacitances of the first and second sustain capacitors C _ST a and C _ST b become larger and the other relatively smaller, so that the two liquid crystal capacitors The voltages of (C _LC a and C _LC b) are different from each other. Then, the inclination angle of the liquid crystal molecules is also different, and thus the luminance of the two subpixels is different. Therefore, if the voltage of the first liquid crystal capacitor C _LC a and the voltage of the second liquid crystal capacitor C _LC b are properly adjusted by adjusting the capacitances of the first and second sustain capacitors C _ST a and C _ST b The image viewed at can be as close as possible to the image viewed at the front, that is, the side gamma curve can be as close as possible to the front gamma curve.

By doing so, the side visibility can be improved without adding additional data lines or gate lines or driving.

In addition, since one gate line 121 and one data line 171 are connected to one pixel PX, two or more gate lines or data lines are connected to one pixel PX, thereby connecting each subpixel. Compared with a structure for separately driving (PXa, PXb), the side visibility can be improved even with a driving frequency of 1/2.

The direction in which the liquid crystal molecules are inclined is primarily due to the horizontal component created by distorting the main electric field between the cutouts 91, 71, 72a and 71b of the field generating electrodes 191 and 270 and the subpixel electrodes 191a and 191b. Is determined by. The horizontal component of this main electric field is substantially perpendicular to the sides of the cutouts 71, 72a, 71b, 91 and the sides of the subpixel electrodes 191a, 191b.

4 through 7, one set of cutouts 71, 72a, 71b, and 91 divides the pixel electrode 191 into a plurality of sub-areas, and each of the sub-regions includes the pixel electrode 191. Have two primary edges that form an oblique angle with the periphery. The periphery of each subregion forms about 45 degrees with the polarization axis of the polarizers 12 and 22, in order to maximize the light efficiency.

Most of the liquid crystal molecules on each subregion are inclined in a direction perpendicular to the periphery thereof, and thus, the inclination directions are approximately four directions. As described above, when the liquid crystal molecules are inclined in various directions, the reference viewing angle of the liquid crystal display is increased.

The shape and arrangement of the cutouts 71, 72a, 71b, 91 for determining the inclination direction of the liquid crystal molecules may be changed, and the at least one cutout 71, 72a, 71b, 91 may have a protrusion (not shown). Or depressions (not shown). The protrusions may be made of organic or inorganic materials and may be disposed above or below the field generating electrodes 191 and 270.

On the other hand, the direction of the secondary electric field generated by the voltage difference between the subpixel electrodes 191a, 191b is perpendicular to the periphery of the subregion. Thus, the direction of the negative electric field coincides with the direction of the horizontal component of the main electric field. As a result, the negative electric field between the subpixel electrodes 191a and 191b acts to strengthen the crystal in the oblique direction of the liquid crystal molecules.

The operation of the liquid crystal display is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE). When the data signal is applied to all the pixels PX by sequentially applying the gate-on voltage Von to the GL, an image of one frame is displayed.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame").

In this case, the polarities of the data signals flowing through one data line are changed (eg, row inversion and point inversion) according to the characteristics of the inversion signal RVS within one frame, or the polarities of the data signals applied to a group of pixels are also different from each other. Can be different (eg invert columns, invert points). Among these, in the case of point inversion or the like, the polarities of the data voltages flowing to the adjacent data lines are reversed, and the voltages of the respective data lines continue to repeat the positive and negative polarities.

As described above, when the polarities of the data voltages flowing through the data lines are reversed, the capacitances of the first and second sustain capacitors C _ST a and C _ST b also change. In other words, when the positive data signal is applied, the capacitance of the first sustain capacitor C _ST a is referred to as C1, and the capacitance when the data signal changes to negative polarity is referred to as C2. When the positive data signal is applied to the data line 171, the capacity of the second storage capacitor C _ST b is referred to as C3, and the capacity at the time of changing to negative polarity is C4.

C1> C2, C3 <C4

Becomes That is, because it turns a negative polarity in the positive capacity of the first storage capacitor (C _ST a) a second storage capacitor (C _ST b) capacity becomes smaller in the increase, the first and second storage capacitor (C _ST Since the capacitance changes of a and C _ST b) cancel each other, and eventually the luminance changes of the two subpixels PXa and PXb cancel each other, flicker does not occur due to polarity inversion.

On the other hand, since the same common voltage is applied to the common electrode 270 and the shielding electrode 88, there is almost no electric field between the two. Therefore, since the liquid crystal molecules positioned between the common electrode 270 and the shielding electrode 88 maintain the initial vertical alignment state, light incident on the portion is not transmitted and is blocked.

As described above, in the exemplary embodiment of the present invention, the visibility can be improved by using the change of luminance of each subpixel according to the change of capacitance of the first and second holding capacitors while simplifying the manufacturing process, and the luminance of the two subpixels cancel each other out. This eliminates the flicker phenomenon and improves image quality. In addition, visibility can be improved with existing driving frequencies.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (12)

First and second signal lines that cross each other, A first switching element connected to the first and second signal lines, A first liquid crystal capacitor connected to the first switching element, A first holding capacitor connected to the first switching element in parallel with the first liquid crystal capacitor, A second switching element connected to the first and second signal lines, A second liquid crystal capacitor connected to the second switching element, and A second holding capacitor connected to the second switching element in parallel with the second liquid crystal capacitor Including, The first and second storage capacitors are respectively disposed between a first terminal connected to the switching element, a second terminal opposite to the first terminal, and between the first terminal and the second terminal, the insulating film and the semiconductor. Including a dielectric comprising, The first terminal of the first storage capacitor is closer to the semiconductor than the first terminal of the second storage capacitor. Liquid crystal display. In claim 1, And second terminals of the first and second storage capacitors are connected to the same voltage. In claim 2, The signal applied to the second signal line has a polarity inverted with respect to the same voltage. Board, A gate electrode formed on the substrate, A storage electrode formed on the substrate and separated from the gate line; A capacitor electrode separated from the gate electrode and the sustain electrode, A first insulating film formed on the sustain electrode, the capacitor electrode, and the first signal line and having a first contact hole exposing the capacitor electrode; First, second and third semiconductors formed on the first insulating film, A source electrode formed on the first semiconductor, First drain electrodes formed on the first and second semiconductors and separated from the source electrodes; A second drain electrode formed on the first semiconductor, A storage conductor formed on the third semiconductor and overlapping the capacitor electrode; A first subpixel electrode connected to the first drain electrode, A second subpixel electrode connected to the second drain electrode and connected to the capacitor electrode through the first contact hole; Including; A common voltage is applied to the sustain electrode and the sustain conductor. Thin film transistor display panel. In claim 4, The thin film transistor array panel of which the first semiconductor and the second semiconductor are connected to each other. In claim 5, The first and second semiconductors have substantially the same planar shape as the source electrode and the first and second drain electrodes except for a portion positioned between the source electrode and the first and second drain electrodes. 3 The thin film transistor array panel having a semiconductor shape substantially the same as that of the storage conductor. In claim 4, A second insulating film formed on the source electrode and the first and second drain electrodes; The second insulating layer has second and third contact holes exposing the first and second drain electrodes, respectively, and a fourth contact hole connected to the first contact hole, The first and second subpixel electrodes are formed on the second insulating layer, and are connected to the first and second drain electrodes through the second and third contact holes, respectively. The second subpixel electrode is connected to the capacitive electrode through the first and fourth contact holes. Thin film transistor display panel. In claim 7, The sustain conductor has a through hole through which the fourth contact hole passes. In claim 7, A gate line formed on the substrate and connected to the gate electrode, and A data line formed on the first insulating layer and connected to the source electrode; Thin film transistor display panel further comprising. In claim 9, And a shielding electrode formed on the second insulating layer and overlapping the data line. In claim 10, The second insulating film further has a fifth contact hole exposing the storage conductor, The shielding electrode is connected to the sustaining conductor through the fifth contact hole. Thin film transistor display panel. In claim 4, And the signal applied to the source electrode is inverted in polarity with respect to the common voltage.

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