KR20070003047A - Digital Temperature Detector and Oscillator Circuit Using the Same - Google Patents

Abstract

The present invention relates to a digital temperature detector and an oscillator circuit using the same, and generates a short cycle pulse signal when the temperature inside the chip rises above a certain temperature by using a digital temperature detector for digitally detecting the internal temperature of the chip. When the temperature inside the chip falls below a certain temperature, a long period pulse signal is generated, thereby reducing power consumption of the product and suppressing an increase in the internal temperature, thereby stably operating the product.

An oscillator circuit using a digital temperature detector according to the present invention includes a digital temperature detector for generating a digital signal obtained by comparing the internal temperature of a semiconductor chip with a reference voltage; And an oscillator for generating pulse signals of different periods according to the digital signals received from the digital temperature detector.

Description

DIGITAL TEMPERATURE DETECTOR AND OSCILLATOR CIRCUIT USING THEREOF}

1 is a block diagram of a digital temperature detector and an oscillator circuit using the same according to the present invention.

2 is a circuit diagram of a digital temperature detector according to the present invention.

3 is an output waveform diagram of a digital temperature detector according to the present invention.

<Description of Major Symbols in Drawing>

100: digital temperature detector 110: temperature change detector

120: comparison unit 210: first oscillator unit

220: second oscillator portion 230: logic circuit portion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital temperature detector and an oscillator circuit using the same, and more particularly, to a digital temperature detector and an oscillator circuit using the same so that a product can be stably operated by generating pulse signals having different cycles according to the chip internal temperature.

In order to achieve high speed and high integration of semiconductor devices, due to the steady reduction of design rules, the reliability of the product is affected by the reduction of threshold voltage, increase of threshold current, decrease of punching margin, and increase of junction leakage current, which occur when individual devices enter the short channel region. Was given.

Due to the weakness of individual devices, the operating current increases at high power voltage and high temperature, and the internal thermal stress of the device varies depending on the degree of heat release even in the same external environment depending on the type of semiconductor package. The trend is getting worse.

Therefore, in order to solve the serious problem that the increase in the internal temperature of the chip on the characteristics of the device, there is an urgent need for a technique to suppress the increase in the internal temperature by reducing the power when the internal temperature rises.

Accordingly, an object of the present invention is to provide a digital temperature detector capable of digitally detecting the temperature inside the chip.

In addition, another technical problem to be achieved by the present invention is to generate a short cycle pulse signal when the temperature inside the chip rises above a certain temperature using the digital temperature detector, and when the temperature inside the chip falls below a certain temperature It is to provide an oscillator circuit using a digital temperature detector that generates a long period of the pulse signal, reducing the power consumption of the product, suppress the rise of the internal temperature to ensure stable operation of the product.

In order to achieve the above technical problem, the present invention includes a temperature change detection unit for detecting a temperature change using a polycrystalline silicon resistor whose resistance value changes in accordance with the ambient temperature change; It provides a digital temperature detector comprising a comparison unit for generating a signal obtained by comparing and amplifying the voltage output from the temperature change detection unit and the reference voltage.

In the present invention, the temperature change detection unit has a current mirror structure and the first and second PMOS transistors for supplying a power supply voltage to the first and second nodes, respectively, when the first node has a first voltage level; First and second NMOS transistors for supplying voltages of the first and second nodes to third and fourth nodes, respectively, when the second node has a second voltage level; A third NMOS transistor connected in series between the third node and a ground voltage terminal and a polycrystalline silicon resistor whose resistance value is changed according to a temperature; A fourth NMOS transistor connected between the fourth node and a ground voltage terminal; A third PMOS transistor supplying a power supply voltage to a fifth node when the second node has a first voltage level; It is preferable to include a fifth NMOS transistor connected in series between the fifth node and the ground voltage terminal and resistance means whose resistance value changes according to temperature.

In the present invention, the resistance means is preferably a polycrystalline silicon resistor.

In the present invention, the resistance means is preferably a fuse option or a metal option.

In the present invention, the comparison unit preferably includes a differential amplifier circuit for receiving a voltage of the second node and the voltage of the fifth node and outputs a signal amplified by comparison.

In the present invention, the comparator comprises: fourth and fifth PMOS transistors having a current mirror structure and supplying power voltages to the sixth and seventh nodes, respectively, when the seventh node has the first voltage level; Sixth and seventh NMOS transistors supplying voltages of the sixth and seventh nodes to an eighth node by voltage magnitudes of the fifth node and the second node; An eighth NMOS transistor forming a current path between the eighth node and a ground voltage terminal; It is preferable to include an inverter for inverting the voltage of the sixth node to output to the ninth node.

In addition, the present invention includes a digital temperature detector for generating a digital signal obtained by comparing the internal temperature of the semiconductor chip with a reference voltage; The present invention provides an oscillator circuit using a digital temperature detector including an oscillator for generating pulse signals having different periods according to digital signals received from the digital temperature detector.

In the present invention, the digital temperature detector includes a temperature change detector for detecting a temperature change by using a polycrystalline silicon resistor whose resistance value changes in accordance with the ambient temperature change; It is preferable to include a comparison unit for generating a signal obtained by comparatively amplifying the voltage output from the temperature change detection unit and the reference voltage.

In the present invention, the temperature change detection unit has a current mirror structure and the first and second PMOS transistors for supplying a power supply voltage to the first and second nodes, respectively, when the first node has a first voltage level; First and second NMOS transistors for supplying voltages of the first and second nodes to third and fourth nodes, respectively, when the second node has a second voltage level; A third NMOS transistor connected in series between the third node and a ground voltage terminal and a polycrystalline silicon resistor whose resistance value is changed according to a temperature; A fourth NMOS transistor connected between the fourth node and a ground voltage terminal; A third PMOS transistor supplying a power supply voltage to a fifth node when the second node has a first voltage level; It is preferable to include a fifth NMOS transistor connected in series between the fifth node and the ground voltage terminal and resistance means whose resistance value changes according to temperature.

In the present invention, the resistance means is preferably a polycrystalline silicon resistor.

In the present invention, the resistance means is preferably a fuse option or a metal option.

In the present invention, the comparison unit preferably includes a differential amplifier circuit for receiving a voltage of the second node and the voltage of the fifth node and outputs a signal amplified by comparison.

In the present invention, the comparator comprises: fourth and fifth PMOS transistors having a current mirror structure and supplying power voltages to the sixth and seventh nodes, respectively, when the seventh node has the first voltage level; Sixth and seventh NMOS transistors supplying voltages of the sixth and seventh nodes to an eighth node by voltage magnitudes of the fifth node and the second node; An eighth NMOS transistor forming a current path between the eighth node and a ground voltage terminal; It is preferable to include an inverter for inverting the voltage of the sixth node to output to the ninth node.

In the present invention, the digital temperature detector outputs a second voltage level when the ambient temperature is higher than the reference voltage, and outputs a first voltage level when the ambient temperature is lower than the reference voltage.

In the present invention, the oscillator includes a first oscillator unit for generating a pulse signal of a first period when the output signal of the digital temperature detector has a first voltage level; A second oscillator unit for generating a pulse signal of a second period shorter than the first period when the output signal of the digital temperature detector has a second voltage level; It is preferable to include a logic circuit section for receiving the output signal of the first and second oscillator section and outputs a logically calculated signal.

In an embodiment of the present invention, the logic circuit section includes: a NAND gate configured to receive and logically output signals of the first and second oscillator sections; It is preferable to include an inverter for inverting and outputting the output signal of the NAND gate.

Accordingly, the present invention generates a short period pulse signal when the temperature inside the chip rises above a certain temperature by using the digital temperature detector, and a long period pulse signal when the temperature inside the chip falls below a certain temperature. By generating a, it is possible to reduce the power consumption of the product and to suppress the rise of the internal temperature to operate the product stably.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

1 is a block diagram of a digital temperature detector and an oscillator circuit using the same according to the present invention.

As shown in FIG. 1, the digital temperature detector and the oscillator circuit using the same of the present invention include a digital temperature detector 110 for generating a digital signal obtained by comparing the internal temperature of a semiconductor chip with a reference voltage, and the digital temperature detector ( The oscillator 200 generates pulse signals of different periods according to the digital signals received from the 110.

Here, the digital temperature detector 110 includes a temperature change detector 110 for detecting a temperature change using a polycrystalline silicon resistor whose resistance value changes according to a change in ambient temperature, and a voltage output from the temperature change detector 110. Comparing unit 120 for generating a signal obtained by comparatively amplifying the reference voltage.

The oscillator 200 generates a pulse signal of a first period (long period) when the output signal C of the digital temperature detector 100 has a first voltage level (for example, 'low'). A second period shorter than the first period when the first oscillator unit 210 and the output signal C of the digital temperature detector 100 have a second voltage level (for example, 'high'). A second oscillator unit 220 for generating a pulse signal of a short period (short period), and a logic circuit unit for receiving an output signal of the first and second oscillator units 210 and 220 and outputting a logically calculated signal ( 230).

Here, the logic circuit unit 230 inverts and outputs the output signal of the NAND gate G1 and the NAND gate G1 that receive and logically output the output signals of the first and second oscillator units 210. It consists of an inverter G2.

The digital temperature detector 100 outputs a second voltage level 'high' when the ambient temperature is higher than the reference voltage, and outputs a first voltage level 'low' when the ambient temperature is lower than the reference voltage. Outputs In addition, when the output signal of the digital temperature detector 100 has a first voltage level ('low'), the oscillator 200 operates the first oscillator unit 210 to perform a first period. Generating a pulse signal, and when the output signal of the digital temperature detector 100 has a second voltage level ('high'), the first oscillator unit 210 operates to generate a second period shorter than the first period. Generates a pulse signal of a short period.

2 is a circuit diagram of a digital temperature detector 100 according to the present invention.

As shown in FIG. 2, the temperature change detector 110 of the digital temperature detector 100 has a current mirror structure and the first node Nd1 has a first voltage level 'low'. And first and second PMOS transistors P1 and P2 for supplying a power supply voltage to the second node Nd1 and Nd2, respectively, and the second node Nd2 sets a second voltage level ('high'). First and second NMOS transistors N1 and N2 respectively supplying voltages of the first and second nodes Nd1 and Nd2 to third and fourth nodes Nd3 and Nd4, respectively; A third NMOS transistor N3 connected in series between the third node Nd3 and the ground voltage Vss terminal, and a polycrystalline silicon resistor R1 whose resistance value changes according to temperature, and the fourth node Nd4 and ground When the fourth NMOS transistor N4 connected between the voltage Vss terminal and the second node Nd2 have the first voltage level 'low', the power supply voltage VDD to the fifth node Nd5. Third PMOS trap to supply Consists of a register (P3) and said fifth node (Nd5) and a ground voltage (Vss) a fifth NMOS transistor (N5) and a polysilicon resistor (R1), the resistance value changes with temperature connected in series between the stage.

The comparator 120 has a current mirror structure and supplies power to the sixth and seventh nodes Nd6 and Nd7 when the seventh node Nd7 has the first voltage level 'low', respectively. The sixth and seventh nodes Nd6 by the voltage magnitudes of the fourth and fifth PMOS transistors P4 and P5 supplying the VDD and the fifth node Nd5 and the second node Nd2. Current path between the sixth and seventh NMOS transistors N6 and N7 for supplying the voltage of Nd7 to the eighth node Nd8, and the eighth node Nd8 and the ground voltage Vss terminal. An eighth NMOS transistor N8 to be formed, and an inverter G3 that inverts the voltage of the sixth node Nd6 and outputs it to the ninth node Nd9.

When the ambient temperature increases, the voltage level of the second node Nd2 is increased because the polysilicon resistance R1 of the temperature change detector 110 increases to lower the threshold voltage of the NMOS transistors N1 and N2. (A) is drastically lowered as shown in FIG. Referring to FIG. 3, it can be seen that the voltage level A of the second node Nd2 decreases as the temperature increases.

The voltage level B of the fifth node Nd5, which is the output signal of the temperature change detection unit 110, is lowered as the temperature increases, but the slope thereof is shown in FIG. 3 as the second node Nd2. It is much lower than the voltage level (A) of.

The voltage level A of the second node Nd2 and the voltage level A of the fifth node Nd5 are compared and amplified by the comparison unit 120 and output. At this time, when it is higher than the reference voltage, the state becomes A <B, and when it is lower than the reference temperature, the state is A> B. When the value is lower than the reference voltage, the output signal C becomes 'low', and when it is high, the output signal C ) Becomes 'high'.

At this time, when the output signal C of the digital temperature detector 100 is' low ', the first oscillator unit 210 operates to generate a short period pulse signal, and the output signal C is' In the case of 'high', the second oscillator 220 operates to generate a long period pulse signal, thereby generating pulse signals having different periods according to temperature.

If the reference voltage is to be changed, the resistance R2 of the temperature change detector 110 may be changed. In addition, the reference voltage may be tuned using a fuse option or a metal option instead of the resistor R2.

Although the present invention focuses on logic that changes a period according to temperature, the present invention can be applied to any logic that sends a specific signal to temperature.

In conclusion, the present invention generates a short cycle pulse signal when the temperature inside the chip rises above a certain temperature by using the digital temperature detector, and a long cycle pulse signal when the temperature inside the chip falls below a certain temperature. By generating a, it is possible to reduce the power consumption of the product and to suppress the rise of the internal temperature to operate the product stably.

As described above, according to the digital temperature detector and the oscillator circuit using the same according to the present invention, when the temperature inside the chip rises above a certain temperature by using a digital temperature detector that detects the chip internal temperature digitally, By generating a signal and generating a long cycle pulse signal when the temperature inside the chip falls below a certain temperature, it reduces the power consumption of the product and suppresses an increase in the internal temperature. have.

Claims (16)

A temperature change detector for detecting a temperature change by using a polycrystalline silicon resistor whose resistance value changes with a change in ambient temperature; And a comparator for generating a signal obtained by comparatively amplifying a voltage output from the temperature change detector and a reference voltage. The method of claim 1, The temperature change detection unit First and second PMOS transistors having a current mirror structure and supplying power voltages to the first and second nodes when the first node has a first voltage level; First and second NMOS transistors for supplying voltages of the first and second nodes to third and fourth nodes, respectively, when the second node has a second voltage level; A third NMOS transistor connected in series between the third node and a ground voltage terminal and a polycrystalline silicon resistor whose resistance value is changed according to a temperature; A fourth NMOS transistor connected between the fourth node and a ground voltage terminal; A third PMOS transistor supplying a power supply voltage to a fifth node when the second node has a first voltage level; And a fifth NMOS transistor connected in series between the fifth node and a ground voltage terminal, and resistance means for changing a resistance value according to a temperature. The method of claim 2, And the resistance means is a polycrystalline silicon resistor. The method of claim 2, Wherein the resistance means is a fuse option or a metal option. The method of claim 2, And the comparator comprises a differential amplifier circuit configured to receive a voltage of the second node and a voltage of the fifth node and output a signal that is amplified by comparison. The method of claim 5, The comparison unit Fourth and fifth PMOS transistors having a current mirror structure and supplying power voltages to the sixth and seventh nodes when the seventh node has the first voltage level; Sixth and seventh NMOS transistors supplying voltages of the sixth and seventh nodes to an eighth node by voltage magnitudes of the fifth node and the second node; An eighth NMOS transistor forming a current path between the eighth node and a ground voltage terminal; And an inverter for inverting the voltage of the sixth node and outputting the inverted voltage to the ninth node. A digital temperature detector for generating a digital signal obtained by comparing the internal temperature of the semiconductor chip with a reference voltage; An oscillator circuit comprising an oscillator for generating pulse signals of different periods in accordance with the digital signal received from the digital temperature detector. The method of claim 7, wherein The digital temperature detector A temperature change detector for detecting a temperature change by using a polycrystalline silicon resistor whose resistance value changes with a change in ambient temperature; An oscillator circuit using a digital temperature detector including a comparison unit for generating a signal obtained by comparing and amplifying a voltage output from the temperature change detection unit and a reference voltage. The method of claim 8, The temperature change detection unit First and second PMOS transistors having a current mirror structure and supplying power voltages to the first and second nodes when the first node has a first voltage level; First and second NMOS transistors for supplying voltages of the first and second nodes to third and fourth nodes, respectively, when the second node has a second voltage level; A third NMOS transistor connected in series between the third node and a ground voltage terminal and a polycrystalline silicon resistor whose resistance value is changed according to a temperature; A fourth NMOS transistor connected between the fourth node and a ground voltage terminal; A third PMOS transistor supplying a power supply voltage to a fifth node when the second node has a first voltage level; And a fifth NMOS transistor connected in series between the fifth node and a ground voltage terminal, and resistance means for changing a resistance value according to a temperature. The method of claim 9, And the resistance means is a polycrystalline silicon resistor. The method of claim 9, The resistance means is an oscillator circuit using a digital temperature detector which is a fuse option or a metal option. The method of claim 8, And the comparator comprises a differential amplifier circuit configured to receive a voltage of the second node and a voltage of the fifth node, and output a signal that has been compared and amplified. The method of claim 12, The comparison unit Fourth and fifth PMOS transistors having a current mirror structure and supplying power voltages to the sixth and seventh nodes when the seventh node has the first voltage level; Sixth and seventh NMOS transistors supplying voltages of the sixth and seventh nodes to an eighth node by voltage magnitudes of the fifth node and the second node; An eighth NMOS transistor forming a current path between the eighth node and a ground voltage terminal; An oscillator circuit using a digital temperature detector including an inverter for inverting the voltage of the sixth node to output to the ninth node. The method of claim 7, wherein The digital temperature detector outputs a second voltage level when the ambient temperature is higher than the reference voltage, and outputs a first voltage level when the ambient temperature is lower than the reference voltage. Circuit. The method of claim 14, The oscillator A first oscillator unit for generating a pulse signal of a first period when the output signal of the digital temperature detector has a first voltage level; A second oscillator unit for generating a pulse signal of a second period shorter than the first period when the output signal of the digital temperature detector has a second voltage level; And a logic circuit section configured to receive output signals of the first and second oscillator sections and output a logically calculated signal. The method of claim 15, The logic circuit portion A NAND gate configured to receive and logically output signals of the first and second oscillators; An oscillator circuit using a digital temperature detector including an inverter for inverting the output signal of the NAND gate and outputs.

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