[go: up one dir, main page]

KR20070001421A - Trench type isolation layer formation method of semiconductor device - Google Patents

Trench type isolation layer formation method of semiconductor device Download PDF

Info

Publication number
KR20070001421A
KR20070001421A KR1020050056908A KR20050056908A KR20070001421A KR 20070001421 A KR20070001421 A KR 20070001421A KR 1020050056908 A KR1020050056908 A KR 1020050056908A KR 20050056908 A KR20050056908 A KR 20050056908A KR 20070001421 A KR20070001421 A KR 20070001421A
Authority
KR
South Korea
Prior art keywords
oxide film
trench
film
semiconductor device
furnace
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1020050056908A
Other languages
Korean (ko)
Other versions
KR100869350B1 (en
Inventor
김진웅
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050056908A priority Critical patent/KR100869350B1/en
Publication of KR20070001421A publication Critical patent/KR20070001421A/en
Application granted granted Critical
Publication of KR100869350B1 publication Critical patent/KR100869350B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 트렌치 소자분리 공정에 관한 것이다. 본 발명은 트렌치 매립 산화막의 갭필 특성을 확보할 수 있는 반도체 소자의 트렌치형 소자분리막 형성방법을 제공하는데 그 목적이 있다. 본 발명에서는 트렌치를 갭필함에 있어서, 우수한 스텝 커버리지(80% 이상)를 가지며 막질이 우수한 퍼니스 증착 산화막(예컨대, 고온산화막(HTO))을 기존의 고밀도플라즈마(HDP) 산화막과 함께 사용한다. 한편, 퍼니스 증착 산화막은 고밀도플라즈마(HDP) 산화막과 달리 심(seam)을 유발하기 때문에 퍼니스 증착 산화막 증착 후 리세스 과정을 거쳐 고밀도플라즈마(HDP) 산화막을 증착한다. 이 경우, 보이드 발생 없이 좁은 트렌치의 갭필이 가능하다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to trench isolation processes in semiconductor device manufacturing processes. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a trench type isolation layer for a semiconductor device capable of securing gap fill characteristics of a trench buried oxide film. In the present invention, in the gap fill trench, a furnace deposition oxide film (eg, high temperature oxide film (HTO)) having excellent step coverage (80% or more) and excellent film quality is used together with the existing high density plasma (HDP) oxide film. On the other hand, since the furnace deposition oxide film causes a seam unlike the high density plasma (HDP) oxide film, the furnace deposition oxide film is deposited and then the high density plasma (HDP) oxide film is deposited through a recess process. In this case, a narrow trench gapfill is possible without voids.

Description

반도체 소자의 트렌치형 소자분리막 형성방법{METHOD FOR FORMING TRENCH TYPE ISOLATION LAYER IN SEMICONDUCTOR DEVICE}METHODS FOR FORMING TRENCH TYPE ISOLATION LAYER IN SEMICONDUCTOR DEVICE}

도 1a 및 도 1b는 종래기술에 따른 STI 공정을 나타낸 단면도.1A and 1B are cross-sectional views illustrating an STI process according to the prior art.

도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 STI 공정을 나타낸 단면도.2A-2D are cross-sectional views illustrating STI processes in accordance with one embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

20: 실리콘 기판20: silicon substrate

21: 패드 산화막21: pad oxide film

22: 패드 질화막22: pad nitride film

23: 고온산화막(HTO)23: high temperature oxide film (HTO)

24: 고밀도플라즈마(HDP) 산화막24: high density plasma (HDP) oxide film

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 트렌치 소자분리 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to trench isolation processes in semiconductor device manufacturing processes.

전통적인 소자분리 공정인 실리콘국부산화(LOCOS) 공정은 근본적으로 버즈비크(Bird's beak)로부터 자유로울 수 없으며, 버즈비크에 의한 활성영역의 감소로 인하여 고집적 반도체 소자에 적용하기 어렵게 되었다.The silicon isolation process (LOCOS) process, which is a traditional device isolation process, cannot fundamentally be free from Bird's beak and is difficult to apply to highly integrated semiconductor devices due to the reduction of the active area caused by Buzzbeek.

한편, 트렌치 소자분리(shallow trench isolation, STI) 공정은 반도체 소자의 디자인 룰(design rule)의 감소에 따른 필드 산화막의 열화와 같은 공정의 불안정 요인을 근본적으로 해결할 수 있고, 활성영역의 확보에 유리한 소자분리 공정으로 부각되고 있으며, 현재는 물론 향후의 초고집적 반도체 소자 제조 공정까지 적용이 유망한 기술이다.Meanwhile, the trench trench isolation (STI) process can fundamentally solve instability factors such as deterioration of the field oxide film due to the reduction of the design rule of the semiconductor device, and is advantageous for securing the active region. It is emerging as a device separation process, and is a promising technology that can be applied to the manufacturing process of ultra-high density semiconductor devices now and in the future.

도 1a 및 도 1b는 종래기술에 따른 STI 공정을 나타낸 단면도이다.1A and 1B are cross-sectional views illustrating an STI process according to the prior art.

종래기술에 따른 STI 공정은, 우선 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 패드 산화막(11) 및 패드 질화막(12)을 형성하고, 소자분리 마스크를 사용한 사진 및 식각 공정을 통해 패드 질화막(12) 및 패드 산화막(11)을 패터닝하여 트렌치 마스크 패턴을 형성한 다음, 트렌치 마스크 패턴을 식각 베리어로 사용하여 노출된 실리콘 기판을 건식 식각함으로써 트렌치를 형성한다.In the STI process according to the related art, first, as shown in FIG. 1A, the pad oxide layer 11 and the pad nitride layer 12 are formed on the silicon substrate 10, and the pads are formed by a photo-etching process using an isolation mask. The nitride film 12 and the pad oxide film 11 are patterned to form a trench mask pattern, and then the trench is formed by dry etching the exposed silicon substrate using the trench mask pattern as an etching barrier.

이어서, 도 1b에 도시된 바와 같이 전체 구조 상부에 고밀도플라즈마(high density plasma, HDP) 산화막(13)을 증착하여 트렌치를 매립한다.Subsequently, as shown in FIG. 1B, a high density plasma (HDP) oxide film 13 is deposited on the entire structure to fill the trench.

이후, 패드 질화막(12)을 연마 정지막으로 하여 화학·기계적 연마(chemical mechanical polishing, CMP) 공정을 실시하여 HDP 산화막(13)을 평탄화시키고, 인산 용액을 사용한 패드 질화막(12) 제거 공정 및 불산 용액 또는 BOE 용액을 사용 한 패드 산화막(11) 제거 공정을 실시하여 트렌치 소자 분리 공정을 완료한다.Subsequently, a chemical mechanical polishing (CMP) process is performed by using the pad nitride film 12 as a polishing stop film to planarize the HDP oxide film 13, and a process of removing the pad nitride film 12 using phosphoric acid solution and hydrofluoric acid is performed. The process of removing the pad oxide layer 11 using a solution or a BOE solution is performed to complete the trench device isolation process.

그런데, 상기와 같은 종래기술에 따라 STI 공정을 수행하는 경우, 고집적화에 따른 셀 사이즈 축소 및 소자분리 영역의 축소에 따라, HDP 산화막(13) 증착시 트렌치 내에 보이드(A)를 유발하는 문제점이 있었다.However, when performing the STI process according to the prior art as described above, there is a problem of causing voids (A) in the trench during the deposition of the HDP oxide film 13 by reducing the cell size and the device isolation region due to high integration. .

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 트렌치 매립 산화막의 갭필 특성을 확보할 수 있는 반도체 소자의 트렌치형 소자분리막 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of forming a trench type isolation layer for a semiconductor device capable of securing gap fill characteristics of a trench buried oxide film.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 실리콘 기판 상에 패드 산화막 및 패드 질화막을 포함하는 트렌치 마스크 패턴을 형성하는 단계; 노출된 상기 실리콘 기판을 선택적으로 식각하여 트렌치를 형성하는 단계; 상기 트렌치가 형성된 전체 구조 상부에 퍼니스 증착 산화막을 증착하는 단계; 상기 퍼니스 증착 산화막이 상기 실리콘 기판의 표면 아래에 잔류하도록 리세스 시키는 단계; 상기 퍼니스 증착 산화막이 리세스된 전체 구조 상부에 고밀도플라즈마 산화막을 증착하는 단계; 상기 패드 질화막이 노출되도록 상기 고밀도플라즈마 산화막을 평탄화시키는 단계; 및 상기 패드 질화막 및 상기 패드 산화막을 제거하는 단계를 포함하는 반도체 소자의 트렌치형 소자분리막 형성방법이 제공된다.According to an aspect of the present invention for achieving the above technical problem, forming a trench mask pattern including a pad oxide film and a pad nitride film on a silicon substrate; Selectively etching the exposed silicon substrate to form a trench; Depositing a furnace deposition oxide on the entire structure of the trench; Recessing the furnace deposited oxide film to remain below the surface of the silicon substrate; Depositing a high density plasma oxide film on the entire structure of the furnace deposition oxide film recessed; Planarizing the high density plasma oxide film to expose the pad nitride film; And removing the pad nitride film and the pad oxide film.

본 발명에서는 트렌치를 갭필함에 있어서, 우수한 스텝 커버리지(80% 이상)를 가지며 막질이 우수한 퍼니스 증착 산화막(예컨대, 고온산화막(HTO))을 기존의 고밀도플라즈마(HDP) 산화막과 함께 사용한다. 한편, 퍼니스 증착 산화막은 고밀도플라즈마(HDP) 산화막과 달리 심(seam)을 유발하기 때문에 퍼니스 증착 산화막 증착 후 리세스 과정을 거쳐 고밀도플라즈마(HDP) 산화막을 증착한다. 이 경우, 보이드 발생 없이 좁은 트렌치의 갭필이 가능하다.In the present invention, in the gap fill trench, a furnace deposition oxide film (eg, high temperature oxide film (HTO)) having excellent step coverage (80% or more) and excellent film quality is used together with the existing high density plasma (HDP) oxide film. On the other hand, since the furnace deposition oxide film causes a seam unlike the high density plasma (HDP) oxide film, the furnace deposition oxide film is deposited and then the high density plasma (HDP) oxide film is deposited through a recess process. In this case, a narrow trench gapfill is possible without voids.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 STI 공정을 나타낸 단면도이다.2A through 2D are cross-sectional views illustrating an STI process according to an embodiment of the present invention.

본 실시예에 따른 STI 공정은 우선, 도 2a에 도시된 바와 같이 실리콘 기판(20) 상에 패드 산화막(21) 및 패드 질화막(22)을 형성하고, 소자분리 마스크를 사용한 사진 및 식각 공정을 통해 패드 질화막(22) 및 패드 산화막(21)을 패터닝하여 트렌치 마스크 패턴을 형성한 다음, 트렌치 마스크 패턴을 식각 베리어로 사용하여 노출된 실리콘 기판을 건식 식각함으로써 트렌치를 형성한다.In the STI process according to the present embodiment, first, as shown in FIG. 2A, a pad oxide film 21 and a pad nitride film 22 are formed on a silicon substrate 20, and a photo and etching process using an isolation mask is performed. A trench mask pattern is formed by patterning the pad nitride layer 22 and the pad oxide layer 21, and then a trench is formed by dry etching the exposed silicon substrate using the trench mask pattern as an etching barrier.

이어서, 도 2b에 도시된 바와 같이 전체 구조 상부에 고온산화막(Hot Temperature oxide, HTO)(23)을 증착하여 트렌치를 매립한다. 여기서, 고온산화막(23)은 퍼니스에서 증착되며, 스텝 커버리지와 막질이 우수한 것으로 알려져 있으 나, 깊은 심(seam, B 부분 참조)을 유발하는 단점이 있다. 한편, 고온산화막(23) 증착 직후 후속 습식 식각 속도의 제어 및 막질 개선을 위하여 열처리를 수행할 수 있다. 열처리는 N2, O2, H2O 분위기 등에서 수행하는 것이 바람직하다.Subsequently, as illustrated in FIG. 2B, a hot temperature oxide (HTO) 23 is deposited on the entire structure to fill the trench. Here, the high temperature oxide film 23 is deposited in the furnace, and is known to have excellent step coverage and film quality, but has a disadvantage of causing a deep seam (see part B). Meanwhile, heat treatment may be performed immediately after the deposition of the high temperature oxide film 23 to control the subsequent wet etching rate and to improve the quality of the film. The heat treatment is preferably carried out in an N 2 , O 2 , H 2 O atmosphere or the like.

다음으로, 도 2c에 도시된 바와 같이 HF 용액 또는 BOE 용액을 사용한 습식 식각을 실시하여 고온산화막(23)이 실리콘 기판(20) 표면보다 낮게 잔류하도록 리세스 시킨다. 도면 부호 '23a'는 습식 식각에 의해 리세스된 고온산화막을 나타낸 것이다.Next, as shown in FIG. 2C, wet etching using an HF solution or a BOE solution is performed to recess the hot oxide layer 23 to remain lower than the surface of the silicon substrate 20. Reference numeral '23a' represents a high temperature oxide film recessed by wet etching.

계속하여, 도 2d에 도시된 바와 같이 전체 구조 상부에 고밀도플라즈마(HDP) 산화막(24)을 증착한다.Subsequently, as shown in FIG. 2D, a high density plasma (HDP) oxide film 24 is deposited on the entire structure.

이후, 패드 질화막(22)을 연마 정지막으로 하여 화학·기계적 연마(CMP) 공정을 실시하여 HDP 산화막(24)을 평탄화시키고, 인산 용액을 사용한 습식 식각을 통해 패드 질화막(22)을 제거한 후, HF 용액 또는 BOE 용액을 사용한 습식 식각을 실시하여 패드 산화막(21)을 제거함으로써 STI 공정을 완료한다.Subsequently, the chemical vapor deposition (CMP) process is performed by using the pad nitride film 22 as a polishing stop film to planarize the HDP oxide film 24, and the pad nitride film 22 is removed by wet etching using a phosphoric acid solution. The STI process is completed by performing wet etching using an HF solution or a BOE solution to remove the pad oxide layer 21.

전술한 실시예에 따르면, 스텝 커버리지가 우수한 고온산화막(23)으로 트렌치 갭필을 수행하기 때문에 보이드 발생을 방지할 수 있으며, 고온산화막(23)에 존재하는 심(seam)을 활성 영역 아래로 리세스 시킨 상태에서 심을 유발하지 않는 HDP 산화막(24)을 증착하기 때문에 심의 노출에 의한 단락 등을 염려할 필요가 없다.According to the above-described embodiment, since the gap gap fill is performed with the high temperature oxide film 23 having excellent step coverage, void generation can be prevented, and the seam existing in the high temperature oxide film 23 is recessed below the active region. Since the HDP oxide film 24 which does not cause shim is deposited in this state, there is no need to worry about short circuit or the like due to the shim exposure.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

예컨대, 전술한 실시예에서는 고온산화막(HTO)을 리세스하기 위하여 습식 식각을 수행하는 경우를 일례로 들어 설명하였으나, 이를 건식 식각으로 대체하는 경우에도 본 발명은 적용된다.For example, in the above-described embodiment, a case of performing wet etching to recess the high temperature oxide film (HTO) has been described as an example. However, the present invention is also applicable to the case of replacing the dry etching with dry etching.

또한, 전술한 실시예에서는 퍼니스 증착 산화막으로 고온산화막(HTO)을 증착하는 경우를 일례로 들어 설명하였으나, 중온산화막(MTO)나 저온산화막(LTO)와 같은 다른 퍼니스 증착 산화막 증착 후 후속 열처리를 통해 고온산화막(HTO)과 유사한 막질의 필름을 형성하는 경우에도 본 발명은 적용된다.In addition, in the above-described embodiment, the case where the high temperature oxide film (HTO) is deposited as the furnace deposition oxide film is described as an example. The present invention also applies to the case of forming a film of a film quality similar to a high temperature oxide film (HTO).

전술한 본 발명은 트렌치 갭필시 보이드 발생을 억제하는 효과가 있으며, 이로 인하여 반도체 소자의 전기적 특성 및 수율을 개선하는 효과가 있다.The present invention described above has the effect of suppressing the generation of voids during trench gap fill, thereby improving the electrical properties and yield of the semiconductor device.

Claims (4)

실리콘 기판 상에 패드 산화막 및 패드 질화막을 포함하는 트렌치 마스크 패턴을 형성하는 단계;Forming a trench mask pattern including a pad oxide layer and a pad nitride layer on the silicon substrate; 노출된 상기 실리콘 기판을 선택적으로 식각하여 트렌치를 형성하는 단계;Selectively etching the exposed silicon substrate to form a trench; 상기 트렌치가 형성된 전체 구조 상부에 퍼니스 증착 산화막을 증착하는 단계;Depositing a furnace deposition oxide on the entire structure of the trench; 상기 퍼니스 증착 산화막이 상기 실리콘 기판의 표면 아래에 잔류하도록 리세스 시키는 단계;Recessing the furnace deposited oxide film to remain below the surface of the silicon substrate; 상기 퍼니스 증착 산화막이 리세스된 전체 구조 상부에 고밀도플라즈마 산화막을 증착하는 단계;Depositing a high density plasma oxide film on the entire structure of the furnace deposition oxide film recessed; 상기 패드 질화막이 노출되도록 상기 고밀도플라즈마 산화막을 평탄화시키는 단계; 및Planarizing the high density plasma oxide film to expose the pad nitride film; And 상기 패드 질화막 및 상기 패드 산화막을 제거하는 단계Removing the pad nitride film and the pad oxide film 를 포함하는 반도체 소자의 트렌치형 소자분리막 형성방법.Trench type device isolation film forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 퍼니스 증착 산화막은 고온산화막(HTO)인 것을 특징으로 하는 반도체 소자의 트렌치형 소자분리막 형성방법.The furnace deposition oxide film is a high temperature oxide film (HTO) characterized in that the trench type device isolation film forming method of a semiconductor device. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 퍼니스 증착 산화막을 증착하는 단계 수행 후,After the step of depositing the furnace deposition oxide film, 상기 퍼니스 증착 산화막에 대한 후속 열처리를 수행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 트렌치형 소자분리막 형성방법.And performing a subsequent heat treatment of the furnace deposited oxide film. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 퍼니스 증착 산화막을 습식 식각을 통해 리세스 시키는 것을 특징으로 하는 반도체 소자의 트렌치형 소자분리막 형성방법.Forming a trench type isolation layer in the semiconductor device, wherein the furnace deposition oxide film is recessed through wet etching.
KR1020050056908A 2005-06-29 2005-06-29 Trench type isolation layer formation method of semiconductor device Expired - Fee Related KR100869350B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050056908A KR100869350B1 (en) 2005-06-29 2005-06-29 Trench type isolation layer formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050056908A KR100869350B1 (en) 2005-06-29 2005-06-29 Trench type isolation layer formation method of semiconductor device

Publications (2)

Publication Number Publication Date
KR20070001421A true KR20070001421A (en) 2007-01-04
KR100869350B1 KR100869350B1 (en) 2008-11-24

Family

ID=37868821

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050056908A Expired - Fee Related KR100869350B1 (en) 2005-06-29 2005-06-29 Trench type isolation layer formation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100869350B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110052038A (en) * 2009-11-12 2011-05-18 삼성전자주식회사 Device isolation structure and method for forming the same
KR20140083559A (en) * 2012-12-26 2014-07-04 에스케이하이닉스 주식회사 Method for manufacturing semiconductor devie

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020004729A (en) * 2000-07-07 2002-01-16 윤종용 Trench isolation method and structure of that
KR100375229B1 (en) * 2000-07-10 2003-03-08 삼성전자주식회사 Trench isolation method
KR100512167B1 (en) * 2001-03-12 2005-09-02 삼성전자주식회사 Method of forming trench type isolation layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110052038A (en) * 2009-11-12 2011-05-18 삼성전자주식회사 Device isolation structure and method for forming the same
US8017495B2 (en) 2009-11-12 2011-09-13 Samsung Electronics Co., Ltd. Method of forming isolation layer structure and method of manufacturing a semiconductor device including the same
US8237240B2 (en) 2009-11-12 2012-08-07 Samsung Electronics Co., Ltd. Isolation layer structure, method of forming the same and method of manufacturing a semiconductor device including the same
KR20140083559A (en) * 2012-12-26 2014-07-04 에스케이하이닉스 주식회사 Method for manufacturing semiconductor devie

Also Published As

Publication number Publication date
KR100869350B1 (en) 2008-11-24

Similar Documents

Publication Publication Date Title
KR100869350B1 (en) Trench type isolation layer formation method of semiconductor device
KR100559042B1 (en) Shallow Trench Isolation Method for Semiconductor Devices
KR100979711B1 (en) Trench gap fill method of semiconductor device
KR100319186B1 (en) Method for fabricating a trench isolation
KR100703836B1 (en) Trench type isolation layer formation method of semiconductor device
KR20040059445A (en) Method for forming trench type isolation layer in semiconductor device
KR100868655B1 (en) Semiconductor device and manufacturing method
KR100703841B1 (en) Trench type isolation layer formation method of semiconductor device
KR100835111B1 (en) Device Separator Formation Method of Semiconductor Device
KR100808051B1 (en) Device Separating Method of Semiconductor Device
KR100826776B1 (en) Device Separator Formation Method of Semiconductor Device
KR100842483B1 (en) Manufacturing Method of Semiconductor Device
KR20040004873A (en) Method for forming trench type isolation layer in semiconductor device
KR100681212B1 (en) Trench type isolation layer formation method of semiconductor device
KR100622029B1 (en) Flash memory device manufacturing method
KR100800104B1 (en) Device isolation region of semiconductor device and forming method thereof
KR101012342B1 (en) Trench type isolation layer formation method of semiconductor device
KR100922074B1 (en) Device Separator Formation Method of Semiconductor Device
KR100541707B1 (en) Device Separating Method of Semiconductor Device
KR100840469B1 (en) Mask Pattern Formation Method to Prevent STI Divot
KR20040105980A (en) The method for forming shallow trench isolation in semiconductor device
KR20070001420A (en) Trench type isolation layer formation method of semiconductor device
KR20080001340A (en) Device Separating Method of Semiconductor Device
KR20080088680A (en) ST formation process of semiconductor device
KR20040004866A (en) Method for forming trench type isolation layer in semiconductor device

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

E601 Decision to refuse application
PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

AMND Amendment
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

J201 Request for trial against refusal decision
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PJ0201 Trial against decision of rejection

St.27 status event code: A-3-3-V10-V11-apl-PJ0201

PB0901 Examination by re-examination before a trial

St.27 status event code: A-6-3-E10-E12-rex-PB0901

E801 Decision on dismissal of amendment
B601 Maintenance of original decision after re-examination before a trial
PB0601 Maintenance of original decision after re-examination before a trial

St.27 status event code: N-3-6-B10-B17-rex-PB0601

J301 Trial decision

Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20080305

Effective date: 20080930

PJ1301 Trial decision

St.27 status event code: A-3-3-V10-V15-crt-PJ1301

Decision date: 20080930

Appeal event data comment text: Appeal Kind Category : Appeal against decision to decline refusal, Appeal Ground Text : 2005 0056908

Appeal request date: 20080305

Appellate body name: Patent Examination Board

Decision authority category: Office appeal board

Decision identifier: 2008101001860

PS0901 Examination by remand of revocation

St.27 status event code: A-6-3-E10-E12-rex-PS0901

S901 Examination by remand of revocation
GRNO Decision to grant (after opposition)
PS0701 Decision of registration after remand of revocation

St.27 status event code: A-3-4-F10-F13-rex-PS0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20111113

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20111113

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000