KR20070000674A - Display substrate, manufacturing method thereof and liquid crystal display device having same - Google Patents

Abstract

A display substrate capable of improving display characteristics, a method of manufacturing the same, and a liquid crystal display device having the same are disclosed. The liquid crystal display includes a lower substrate having a first color filter layer formed in the display area and a second color filter layer formed in a peripheral area where an image is not displayed. The lower substrate may minimize the difference in cell gap between the display area and the peripheral area by forming the color filter layer in the peripheral area as well as the display area. Accordingly, the liquid crystal display device can prevent edge irregularities caused by the difference in light transmittance between the display area and the peripheral area, thereby improving display characteristics.

Description

DISPLAY SUBSTRATE, METHOD OF FABRICATING THE SAME AND LIQUID CRYSTAL DISPLAY APPARATUS HAVING THE SAME

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a plan view illustrating the lower substrate of FIG. 1.

3 is a block diagram illustrating a first gate driver illustrated in FIG. 2.

4 is a cross-sectional view taken along the line II ′ of FIG. 1.

5A through 5C are cross-sectional views illustrating a manufacturing process of the lower substrate illustrated in FIG. 4.

6 is an enlarged plan view illustrating a portion 'A' of FIG. 2.

FIG. 7 is a cross-sectional view taken along the line II-II ′ of FIG. 6.

8 is a cross-sectional view taken along line III-III ′ of FIG. 1.

9 is a cross-sectional view taken along the line IV-IV ′ of FIG. 1.

<Description of the symbols for the main parts of the drawings>

100: lower substrate 200: upper substrate

300: driving chip 400: liquid crystal layer

500: liquid crystal display device

The present invention relates to a display substrate, a method for manufacturing the same, and a liquid crystal display having the same, and more particularly, to a display substrate capable of improving display characteristics, a method for manufacturing the same, and a liquid crystal display having the same.

In general, the liquid crystal display includes a liquid crystal display panel for displaying an image and a backlight assembly for providing light to the liquid crystal display panel.

The liquid crystal display panel includes a lower substrate on which a pixel portion is formed, an upper substrate coupled to the lower substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate.

The lower substrate further includes a pixel electrode provided for each pixel part to apply a signal voltage to the liquid crystal layer. The upper substrate includes a common electrode applying a common voltage to the liquid crystal layer and color pixels expressing a predetermined color by using light. Each color pixel is positioned corresponding to each pixel portion. However, when combining the lower substrate and the upper substrate, it is difficult to match the position between the color pixels and the pixel portions.

In order to solve this problem, a method of forming color pixels on the lower substrate has emerged. When the color pixels are formed in the lower substrate, the color pixels are formed only in the display area in which the image is displayed, and are not formed in the peripheral area surrounding the display area, and thus the cell gap between the peripheral area and the display area is different. As a result, the light transmittance between the peripheral area and the transmission area is different from the liquid crystal display panel, and thus, edge irregularities occur.

An object of the present invention is to provide a display substrate which can improve display characteristics by making the cell gap uniform.

Another object of the present invention is to provide a method of manufacturing the display substrate.

Another object of the present invention is to provide a liquid crystal display device having the aforementioned display substrate.

According to one aspect of the present invention, a display substrate includes a base substrate, a pixel portion, a first color filter layer, and a second color filter layer.

The base substrate is divided into a display area where an image is displayed and a peripheral area surrounding the display area. The pixel portion is formed on the base substrate in correspondence with the display area. The first color filter layer is formed on the base substrate on which the pixel portion is formed corresponding to the display area. The second color filter layer is formed on the base substrate corresponding to the peripheral area.

In addition, in the display substrate manufacturing method according to one feature for realizing the above object of the present invention, first, a pixel portion is formed in a display area on a base substrate. A color pixel layer is deposited on the base substrate on which the pixel portion is formed. Thereafter, the color pixel layer is patterned to form a first color filter layer in the display area, and at the same time, a second color filter layer is formed corresponding to the peripheral area surrounding the display area.

According to an aspect of the present invention, a liquid crystal display device includes a lower substrate, an upper substrate, and a liquid crystal layer.

The lower substrate includes a first base substrate, a first color filter layer, and a second color filter layer. The first base substrate is divided into a display area in which an image is displayed and a peripheral area surrounding the display area. The first color filter layer is formed on the first base substrate corresponding to the display area, and the second color filter layer is formed on the first base substrate corresponding to the peripheral area. The upper substrate has a second base substrate facing the first base substrate and a common electrode formed on the second base substrate. The liquid crystal layer is interposed between the upper substrate and the lower substrate.

According to such a display substrate, a manufacturing method thereof, and a liquid crystal display having the same, a color filter layer may be formed in the display area and the peripheral area of the lower substrate to minimize the difference in cell gap between the display area and the peripheral area. Accordingly, the liquid crystal display device can prevent edge irregularities caused by the difference in light transmittance between the display area and the peripheral area, thereby improving display characteristics.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view showing a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is a plan view showing a lower substrate shown in FIG. 1, and FIG. 3 is a block diagram showing a first gate driver shown in FIG. 2. to be.

1 and 2, the liquid crystal display device 500 is mounted on the lower substrate 100, the upper substrate 200 and the lower substrate 100 coupled to face the lower substrate 100. A driving chip 300 for outputting a data signal is included.

The lower substrate 100 includes a first base substrate 110 and a plurality of pixel parts formed on the first base substrate 110.

The first base substrate 110 is a transparent material which is partitioned into a display area DA in which an image is displayed and a peripheral area PA surrounding the display area PA and in which the image is not substantially displayed. Is made of.

The plurality of pixel units includes a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. Where n and m are one or more natural numbers.

The plurality of gate lines GL1 to GLn extend in a first direction D1 and are disposed in a second direction D2 orthogonal to the first direction D1. The plurality of gate lines GL1 to GLn are insulated from and cross the plurality of data lines DL1 to DLm in the display area DA, and transmit gate signals.

The plurality of data lines DL1 to DLm extend in the second direction D2 and are disposed in the first direction D1. The plurality of data lines DL1 to DLm are electrically connected to the driving chip 300 to transmit the data signals.

Each pixel unit Px includes a thin film transistor (TFT) 120 connected to a gate line and a data line, and a pixel electrode 130 electrically connected to the TFT 120. A detailed description of the TFT 120 and the pixel electrode 130 will be described later with reference to FIG. 4.

The lower substrate 100 further includes a first gate driver 140 formed in the peripheral area PA of the first base substrate 110 to output the gate signal.

The first gate driver 140 sequentially outputs gate signals to the gate lines GL1 to GLn in response to a control signal input from the outside. The first gate driver 140 is formed together in the process of forming the TFT 120 through the same process as the process of forming the TFT 120.

However, the first gate driver 140 may be embedded in the driving chip 300 or formed as a separate chip and mounted on the peripheral area PA of the base substrate 110. When the first gate driver 140 is embedded in the driving chip 300, the driving chip 300 outputs the gate signals to the gate lines GL1 to GLn.

Referring to FIG. 3, the first gate driver 140 includes a circuit part CS and an input part LS provided adjacent to the circuit part CS.

The circuit unit CS is configured of first to nth + 1 stages SRC1 to SRCn + 1 connected to each other and sequentially outputs first to nth gate signals OUT1 to OUTn.

Each of the first to n + 1th stages SRC1 to SRCn + 1 includes a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, Ground voltage terminal V1, reset terminal RE, carry terminal CR, and output terminal OUT are included.

A first clock CKV is provided to the first clock terminal CK1 of the odd-numbered stages SRC1, SRC3, ... SRCn + 1 of the first to n + 1th stages SRC1 to SRCn + 1. The first clock terminal CK2 of the even-numbered stages SRC2, SRCn is provided with a second clock CKVB having a phase different from that of the first clock CKV. The second clock terminal CKVB of the odd stages SRC1, SRC3, ... SRCn + 1 is provided with the second clock CKVB, and the even stages SRC2, SRCn The first clock CKV is provided to the second clock terminal CK2.

The start signal STV or the previous gate signal of the previous stage is input to the first input terminal IN1 of each of the first to n + 1th stages SRC1 to SRCn + 1. The first input terminal IN1 of the first driving stage SRC1 is provided with the start signal STV at which the operation of the circuit unit CS starts.

The carry signal of the next stage is input to the second input terminal IN1 of each of the first to n + 1th stages SRC1 to SRCn + 1. The n + 1th stage SRCn + 1 is a dummy stage provided to provide a carry signal to the second input terminal IN2 of the nth stage SRCn. The start signal STV is provided to the second input terminal IN2 of the n + 1th stage SRCn + 1 instead of the rear carry signal of the next stage.

The off voltage Voff is provided to the off voltage terminals V1 of the first to nth stages SRC1 to SRCn + 1, and the reset of the first to n + 1th stages SRC1 to SRCn + 1 is performed. The terminal RE is provided with an n + 1 th gate signal output from the n + 1 th stage SRCn + 1.

The first clock CKV is output from the carry terminal CR and the output terminal OUT of the odd-numbered stages SRC1, SRC3, ... SRCn + 1, and the even-numbered stages SRC2, ... The second clock CKVB is output from the carry terminal CR and the output terminal OUT of SRCn. The carry signal output from the carry terminal CR of the second to n + 1th stages SRC2 to SRCn + 1 is provided to the second input terminal IN2 of the previous stage. In addition, the first to nth gate signals OUT1 to OUTn output from the output terminals OUT of the first to nth stages SRC1 to SRCn are provided to the first input terminal IN1 of the next stage.

The input part LS includes the first to fifth signal wires SL1, SL2, SL3, SL4, and SL5.

The first signal line SL1 receives the off voltage Voff from the outside. The second signal line SL2 receives the first clock CKV from the outside, and the third clock line SL3 receives the second clock CKVB from the outside. The fourth signal line SL4 receives the start signal STV provided from the outside from the first input terminal IN1 of the first stage SRC1 and the second input of the n + 1th stage SRCn + 1. Provided to terminal IN2. The fifth signal line SL5 resets the n + 1 gate signal output from the n + 1th stage (SRCn + 1) to the reset terminal of the first to n + 1th stages SRC1 to SRCn + 1. Provided by (RE).

For example, the fifth signal line SL5, the fourth signal line SL4, the third signal line SL3, the second signal line SL2, and the first signal line SL1 may be sequentially formed. It is arrange | positioned adjacent to the circuit part CS. Therefore, the first signal line SL4 is disposed outside the first base substrate 110 (see FIG. 2) rather than the other lines.

The input part LS further includes first, second and third connection wirings CL1, CL2, and CL3.

The first connection line CL1 connects the first signal line SL1 to the off voltage terminal V1 of the first to n + 1th stages SRC1 to SRCn + 1 of the circuit part CS. The second connection line CL2 connects the second signal line SL2 to the first clock terminal CK1 and the even-numbered number of the odd stages SRC1, SRC3,... SRCn + 1 of the circuit unit CS. It is connected to the second clock terminal CK2 of the stages SRC2, ... SRCn. The third connection line CL3 connects the third signal line SL3 to the first clock terminal CK1 and the odd-numbered stage SRC1, of even-numbered stages SRC2, ... SRCn of the circuit unit CS. It is connected to the second clock terminal CK2 of SRC3, ... SRCn + 1).

Referring back to FIG. 2, the lower substrate 100 may further include a second gate driver 145 formed in the peripheral area PA of the first base substrate 110. The second gate driver 145 is provided to face the first gate driver 140. That is, the first and second gate drivers 140 and 145 are provided at both sides of the display area DA, respectively.

The second gate driver 145 is formed to equally fit a cell gap between an area provided with the first gate driver 140 and an area opposite to the display area DA. In addition, the second gate driver 145 may be formed to share the function of the first gate driver 140.

When the second gate driver 145 performs the same function as the first gate driver 140, the gate signal is output in response to a control signal input from outside like the first gate driver 140. The gate signals output to the plurality of gate lines GL1 to GLn are provided.

In contrast, the gate signal is not output when the second gate driver 145 is simply formed to uniformize the cell gap of the peripheral area PA.

Like the first gate driver 140, the second gate driver 145 is formed in the same process as the process of forming the TFT 120, and is formed together when the TFT 120 is formed.

Referring back to FIG. 1, the lower substrate 100 may include the first color filter layer 150 and the first base substrate 110 formed in the display area DA of the first base substrate 110. A second color filter layer 155 is further formed in the peripheral area PA.

The first color filter layer 150 is provided to correspond to the display area DA and is formed of RGB color pixels expressing a predetermined color by using light provided from the outside.

The second color filter layer 155 is provided corresponding to the peripheral area PA and is formed on the first and second gate drivers 140 and 145. Like the first color filter layer 150, the second color filter layer 155 may be formed of the RGB color pixels, or may be formed of only one of the RGB color pixels.

The second color filter layer 155 is formed through the same process as the process of forming the first color filter layer 150, and is formed together in the process of forming the first color filter layer 150.

The second color filter layer 155 may be formed in the entire peripheral area PA so as to surround the display area PA, and both sides of the display area DA, that is, the first and second gates. It may be located only in the region where the driving units 140 and 145 are formed.

As such, when the second color filter layer 155 is provided only at both sides of the display area DA, the first color filter layer 150 extends toward the peripheral area PA and the second color filter. It may also replace the function of layer 155.

That is, the first color filter layer 150 is formed from the display area DA from the source color side of the first base substrate 110 on which the driving chip 300 is located. It extends to the end side opposite the source side. Therefore, the first color filter layer 150 partially covers the peripheral area PA in addition to the display area DA.

4 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 4, the TFT 120 is provided in the display area DA on the first base substrate 110. The TFT 120 includes a gate electrode 121, an active layer 122, an ohmic contact layer 123, a source electrode 124, and a drain electrode 125 formed on the first base substrate 110. .

The gate electrode 121 is formed by branching from a gate line and receives the gate signal. Although not shown in FIG. 4, the gate electrode 121 is provided on the same layer as the plurality of gate lines GL1 to GLn.

A gate insulating layer 170 is provided on the first base substrate 110 on which the gate electrode 121 is formed. The gate insulating layer 170 protects the gate electrode 121 and the gate lines GL1 to GLn.

The active layer 122 and the ohmic contact layer 123 are sequentially formed in the display area DA on the gate insulating layer 170. The active layer 122 and the ohmic contact layer 123 are provided to correspond to the gate electrode 121. The center portion of the ohmic contact layer 123 is removed to partially expose the active layer 122. The exposed region of the active layer 122 serves as a channel region.

The source electrode 124 and the drain electrode 125 are formed on the ohmic contact layer 123. The source electrode 124 and the drain electrode 125 are positioned to face each other with respect to the channel region. The source electrode 124 is formed branched from a data line and receives the data signal.

The lower substrate 100 further includes a passivation layer 175 that protects the TFT 120 and the first gate driver 140. The passivation layer 175 is formed on the first base substrate 110 on which the TFT 120 and the first gate driver 140 are formed.

First and second color filter layers 150 and 155 are formed on the passivation layer 175. The first color filter layer 150 is formed in the display area DA.

The second color filter layer 155 is formed in the peripheral area PA and is made of the same material as the first color filter layer 150. The second color filter layer 155 is positioned on the first and second gate drivers 140 and 145 so that the first and second gate drivers 140 and 145 and the upper substrate 200 are separated from each other. Insulate. Accordingly, the liquid crystal display 500 may prevent the lower substrate 100 and the upper substrate 200 from shorting to each other in the peripheral area PA.

The first and second color filter layers 150 and 155 are formed to have the same thickness. Therefore, the liquid crystal display 500 may reduce the difference between the cell gap G1 of the display area DA and the cell gap G2 of the peripheral area PA. In addition, since the lower substrate 100 may have a thick thickness of the peripheral area PA, the liquid crystal display 500 may prevent light from leaking in the peripheral area PA.

Accordingly, since the liquid crystal display device 500 can prevent spots from occurring in the peripheral area PA, display characteristics can be improved.

Meanwhile, the passivation layer 175 and the first color filter layer 150 have contact holes CH formed by partially removing the passivation layer 125 to partially expose the drain electrode 125.

The pixel electrode 130 is formed on an upper surface of the first color filter layer 150. The pixel electrode 300 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 130 is electrically connected to the TFT 120 through the contact hole CH.

The upper substrate 200 is provided to face the lower substrate 100. The upper substrate 200 includes a second base substrate 210, a black matrix 220, and a common electrode 230.

The second base substrate 210 is made of a transparent material that transmits light and is positioned to face the first base substrate 110. The black matrix 220 is formed on the second base substrate 210 to block light. The black matrix 220 is positioned to correspond to the TFT 120 and the peripheral area PA. The common electrode 230 is formed on the second base substrate 210 on which the black matrix 220 is formed to provide a common voltage. The common electrode 230 is made of a transparent conductive material such as ITO or IZO.

The liquid crystal layer 400 is interposed between the lower substrate 100 and the upper substrate 200. The liquid crystal layer 400 adjusts light transmittance according to an electric field formed between the pixel electrode 130 and the common electrode 230. As a result, the liquid crystal display 500 displays the image.

5A through 5C are cross-sectional views illustrating a manufacturing process of the lower substrate illustrated in FIG. 4.

Referring to FIG. 5A, the TFT 120 is formed in the display area DA of the first base substrate 110. In the process of forming the TFT 120, the first gate driver 140 is formed in the peripheral area PA of the first base substrate 110.

Although not shown in FIGS. 5A to 5C, the second gate driver 145 (see FIG. 1) is formed together with the first gate driver 140, and the plurality of TFTs 120 may be formed in the process of forming the TFT 120. Gate lines GL1 to GLn (see FIG. 2) and the plurality of data lines DL1 to DLm (see FIG. 2) are formed together.

Thereafter, the passivation layer 175 covering the TFT 120 and the first gate driver 140 is formed on the first base substrate 110.

Referring to FIG. 5B, a color pixel layer CP having a predetermined color is formed on the passivation layer 175. The color pixel layer CP is patterned to form one color pixel among the RGB color pixels constituting the first color filter layer 150 and simultaneously form the second color filter layer 155.

Here, the color layer CP is formed of any one of the RGB color pixels. Therefore, the first color filter layer 150 is formed by repeatedly depositing and patterning three pixel layers corresponding to each of the RGB color pixels for each of the pixel layers.

Referring to FIG. 5C, portions of the first color filter layer 150 and the passivation layer 175 are removed to form the contact hole CH. As shown in FIG. 4, the lower substrate 100 is completed by forming the pixel electrode 130 on the first color filter layer 150.

6 is an enlarged plan view illustrating a portion 'A' of FIG. 2, and FIG. 7 is a cross-sectional view taken along the line II-II 'of FIG. 6.

2 and 6, the lower substrate 100 further includes a first output unit electrically connected to the first gate driver 140. The first output part is formed in the peripheral area PA of the first base substrate 110 and transmits a gate signal output from the first gate driver 140.

The first output part includes a plurality of output lines OL1_1 to OL1_p, and the plurality of output lines OL1_1 to OL1_p are electrically connected to the plurality of gate lines GL1 to GLn. Here, p is a natural number of 1 or more.

In this embodiment, structures of the plurality of output lines OL1_1 to OL1_p are the same, and a connection relationship between the plurality of output lines OL1_1 to OL1_p and the plurality of gate lines GL1 to GLn is the same. . Therefore, the structure of the plurality of output lines OL1_1 to OL1_p will be described below using the first output line OL1_1 as an example, and a connection relationship between the first output line OL1_1 and the first gate line OL is described. As an example, a connection relationship between the plurality of gate lines GL1 to GLn and the plurality of output lines OL1_1 to OL1_p will be described.

6 and 7, the first output line OL1_1 is formed on the gate insulating layer 170, and the passivation layer 175 is provided on the first output line OL1_1. The first output line OL1_1 is covered. An output pad OL1_OP is formed at an end of the first output line OL1_1 adjacent to the first gate line GL1.

An input pad GL1_IP is formed at an end of the first gate line GL1 adjacent to the first output line OL1_1, and an end of the input pad GL1_IP is provided in the peripheral area PA. The first gate line GL1 is provided under the gate insulating layer 170. Therefore, the first output line OL1_1 and the first gate line GL1 are provided in different layers.

The gate insulating layer 170 and the passivation layer 175 have a first via hole VH1 formed by removing a portion thereof. The first via hole VH1 partially exposes the input pad OP of the first gate line GL1.

The passivation layer 175 further includes a second via hole VH2 formed by removing a portion of the passivation layer 175. The second via hole VH2 partially exposes the output pad OL1_OP of the first output line OL1_1.

The lower substrate 100 further includes a first electrode layer 180 electrically connecting the plurality of gate lines GL1 to GLn and the plurality of output lines OL1_1 to OL1_p.

The first electrode layer 180 is formed on the passivation layer 175 and is made of a transparent conductive material. The first electrode layer 180 is formed in the same process as the process of forming the pixel electrode 130 (see FIG. 2), and is formed together in the process of forming the pixel electrode 130.

The first electrode layer 180 is electrically connected to the first gate line GL1 through the first via hole VH1 and electrically connected to the first output line OL1_1 through the second via hole VH2. Is connected. Thus, the first output line OL1 is electrically connected to the first gate line GL1, and the first gate line GL1 receives a gate signal from the first output line OL1_1.

The second color filter layer 155 is removed in a region corresponding to the first electrode layer 180. This is because when the second color filter layer 155 is provided on the output pad OL1_OP and the input pad GL1_IP, the first and second via holes VH1 and VH2 and the first and second holes. Steps between the peripheral parts of the via holes VH1 and VH2 are severe.

As a result, a contact between the first electrode layer 180, the output pad OL1_OP and the input pad GL1_IP may not be well formed, and thus, the first gate line GL1 and the first output line OL1_1 may not be well formed. ) The electrical connection between the terminals may be broken or incompletely connected. In order to prevent this, the second color filter layer 155 is removed from an area where the plurality of gate lines GL1 to GLn and the plurality of output lines OL1_1 to OL1_p are electrically connected.

Referring again to FIGS. 1 and 2, the lower substrate 100 further includes a second output unit electrically connected to the second gate driver 145. Like the first output unit, the second output unit is formed in the peripheral area PA of the first base substrate 110 and transmits a gate signal output from the second gate driver 145.

The second output part includes a plurality of gate output lines OL2_1 to OL2_q, and the plurality of gate output lines OL2_1 to OL2_q are electrically connected to the plurality of gate lines GL1 to GLn. Where q is one or more natural numbers.

In this embodiment, the structure of the plurality of gate output lines OL2_1 to OL2_q is the same as the plurality of output lines OL1_1 to OL1_p. In addition, a connection relationship between the plurality of gate output lines OL2_1 to OL2_q and the plurality of gate lines GL1 to GLn may be defined between the plurality of output lines OL1_1 to OL1_p and the plurality of gate lines GL1 to GLn. Same as connection relationship. Therefore, hereinafter, redundant descriptions of the plurality of gate output lines OL2_1 to OL2_q will be omitted.

8 is a cross-sectional view taken along line III-III ′ of FIG. 1.

1 and 2, the lower substrate 100 is formed on the first base substrate 110 to apply a plurality of common electrode lines CL1 to CLn and the plurality of common electrodes. The apparatus further includes a third output part OL3 providing the common voltage to the lines CL1 to CLn.

The plurality of common electrode lines CL1 to CLn extend in the first direction D1 and are disposed in the second direction D2. The plurality of common electrode lines CL1 to CLq are positioned over the display area DA and the peripheral area PA. One end of the plurality of common electrode lines CL1 to CLn is connected to the third output part OL3 to receive the common voltage.

Although not shown in the drawing, the plurality of common electrode lines CL1 to CLn are electrically connected to the common electrode 230 (see FIG. 8) provided in the upper substrate 200. As a result, the common electrode 230 receives the common voltage from the plurality of common electrode lines CL1 to CLn.

The third output part OL3 is positioned in the peripheral area PA of the first base substrate 110 and partially surrounds the display area DA. The third output part OL3 is connected to the driving chip 300 to receive the common voltage from the driving chip 300.

The plurality of common electrode lines CL1 to CLn have the same structure, and the connection relationship with the third output part OL3 is also the same. Therefore, hereinafter, in the description of the connection relationship between the plurality of common electrode lines CL1 to CLn and the third output unit OL3, the third output unit may be configured by using the first common electrode line CL1 as an example. The connection relationship with (OL3) is demonstrated.

1 and 8, the first common electrode line CL1 is formed on the first base substrate 110 and is disposed on the same layer as the plurality of gate lines GL1 to GLn. One end of the first common electrode line CL1 is positioned in the peripheral area PA.

The gate insulating layer 170 is formed on the first base substrate 110 on which the first common electrode line CL1 is formed.

The third output part OL3 is formed on the top surface of the gate insulating film 170, and the passivation layer 175 is formed on the gate insulating film 170 on which the third output part OL3 is formed. As such, since the third output part OL3 and the first common electrode line CL1 are provided in different layers, the third output part OL3 and the first common electrode line CL1 are insulated from each other.

The passivation layer 175 includes third and fourth via holes VH3 and VH4 to electrically connect the third output part OL3 and the first common electrode line CL1.

The third and fourth via holes VH3 and VH4 are formed in the peripheral area PA and are adjacent to each other. The third via hole VH3 is formed by partially removing the gate insulating layer 170 and the passivation layer 175 and exposing one end of the first common electrode line CL1. The fourth via hole VH4 is formed by partially removing the passivation layer 175, and partially exposes the third output part OL3.

The lower substrate 100 further includes a second electrode layer 185 electrically connecting the third output part OL3 and the first common electrode line CL1.

The second electrode layer 185 is formed on the top surface of the passivation layer 175 and is positioned in the peripheral area PA. The second electrode layer 185 is formed of the same material as the first electrode layer 180 (see FIG. 6), and is formed together when the first electrode 180 is formed. The second electrode layer 185 is electrically connected to the first common electrode line CL1 through the third via hole VH3, and is connected to the third output part OL3 through the fourth via hole VH4. Electrically connected. The second electrode layer 185 extends to an area where the third via hole VH3 is formed and is formed over an area where the fourth via hole VH4 is formed. As a result, the first common electrode line CL1 and the third output part OL3 are electrically connected to each other through the electrode layer 180.

The second color filter layer 155 may be connected to the first common electrode line CL1 such that the first common electrode line CL1, the third output unit OL3, and the electrode layer OL3 are in stable contact with each other. The third output part OL3 is not formed in an area that is electrically connected, that is, in an area corresponding to the second electrode layer 185.

9 is a cross-sectional view taken along the line IV-IV ′ of FIG. 1.

1 and 2, the lower substrate 100 further includes an static electricity blocking circuit 160 to prevent static electricity from flowing into the display area DA through the data lines DL1 to DLm. Equipped.

The static electricity blocking circuit 160 is formed in the peripheral area PA of the first base substrate 110. The static electricity blocking circuit 160 is positioned between the driving chip 300 and the display area PA.

1 and 9, the liquid crystal display device 500 further includes a sealant 510 that seals the liquid crystal layer 400 by combining the lower substrate 100 and the upper substrate 200. .

The static electricity blocking circuit 160 is formed in a region where the liquid crystal layer 400 is located. The first color filter layer 150 and the second color filter layer 155 extending to the peripheral area PA are not formed on the static electricity blocking circuit 160.

Although not shown in the drawing, the static electricity blocking circuit 160 includes a first electrode provided under the gate insulating film 170 and a second electrode provided on an upper surface of the gate insulating film 170. The first and second electrodes are electrically connected to each other by using a third electrode, similarly to the method of connecting the plurality of gate lines GL1 to GLn and the first output unit. The first color filter layer 150 and the second color filter layer 155 are removed from the region in which the static electricity blocking circuit 160 is formed so as to stably contact the third electrode with the first and second electrodes. do.

The liquid crystal display device 500 further includes an anisotropic conductive film (ACF) 350 for attaching the driving chip 300 to the lower substrate 100. The ACF 350 is interposed between the lower substrate 100 and the driving chip 300 to electrically connect the lower substrate 100 and the driving chip 300.

According to the present invention described above, the liquid crystal display includes a lower substrate having a first color filter layer formed in the display area and a second color filter layer formed in the peripheral area where an image is not displayed. The lower substrate may form a color filter layer not only in the display area but also in the peripheral area to minimize the difference in thickness between the display area and the peripheral area, thereby minimizing the difference in cell gap between the display area and the peripheral area. Accordingly, the liquid crystal display device can prevent edge irregularities caused by the difference in light transmittance between the display area and the peripheral area, thereby improving display characteristics.

In addition, since the second color filter layer is provided on the first and second gate drivers, the second color filter layer insulates the first and second gate drivers and the common electrode from each other. Accordingly, the liquid crystal display device can prevent the upper substrate and the lower substrate from shorting to each other in the peripheral area.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (18)

A base substrate partitioned into a display area in which an image is displayed and a peripheral area surrounding the display area; A pixel portion formed on the base substrate corresponding to the display area; A first color filter layer formed on the base substrate on which the pixel portion is formed corresponding to the display area; And And a second color filter layer formed on the base substrate corresponding to the peripheral area. The display of claim 1, further comprising a first gate driver which is simultaneously formed in the peripheral region on the base substrate, is electrically connected to the pixel portion, and outputs a gate signal. Board. The display substrate of claim 2, wherein the second color filter layer is formed on the first gate driver. The display substrate of claim 2, wherein the second color filter layer is formed in a region other than a region electrically connected to the pixel portion and the first gate driver. The method of claim 4, wherein A first output line formed in the peripheral region on the base substrate and electrically connected to the first gate driver; And A gate line forming the pixel portion and electrically connected to the first output line; And an area in which the pixel portion and the first gate driver are electrically connected to each other is an area in which the first output line and the gate line are electrically connected to each other. The method of claim 5, An insulation layer formed on the base substrate on which the gate line is formed, the insulating layer having a first via hole formed by partially removing the gate line and partially exposing the gate line; A protective film formed on the insulating layer on which the first output line is formed and having a second via hole formed by partially removing the first output line to partially expose the first output line; And And an electrode layer formed on the passivation layer and electrically connected to the gate line and the first output line through the first and second via holes. 3. The display device of claim 2, further comprising a second gate driver formed at the same time when the first gate driver is formed in the peripheral region on the base substrate and facing the first gate driver with the pixel portion interposed therebetween. Display substrate. The display substrate of claim 7, wherein the second color filter layer is formed in an area except for an area in which the pixel part and the second gate driver are electrically connected to each other. The method of claim 7, wherein A gate line formed on the base substrate to form the pixel portion; And A second layer formed in the peripheral area on the base substrate and formed on a layer different from the gate line, and electrically connected to the second gate driver and the gate line to transmit a gate signal output from the second gate driver; Further includes 2 output lines, And an area in which the pixel portion and the second gate driver are electrically connected to each other is an area in which the gate line and the second output line are electrically connected to each other. The display substrate of claim 9, wherein the second color filter layer is formed on the second gate driver. The display substrate of claim 1, further comprising an electrostatic blocking circuit formed in the peripheral region of the base substrate and provided on a source side of the base substrate to prevent static electricity from flowing into the display region. . The display substrate of claim 11, wherein the second color filter layer is formed in a region other than the region in which the static electricity blocking circuit is provided. The display device of claim 1, wherein the first color filter layer extends outside the display area so that a portion of the first color filter layer is formed in the peripheral area, and is positioned in a source side of the base substrate and an area opposite to the source side. Display substrate, characterized in that. Forming a pixel portion in the display area on the base substrate; Depositing a color pixel layer on the base substrate on which the pixel portion is formed; And Patterning the color pixel layer to form a first color filter layer corresponding to the display area and simultaneously forming a second color filter layer corresponding to a peripheral area surrounding the display area. Substrate manufacturing method. The method of claim 14, wherein in the forming of the pixel portion, And forming a first gate driver configured to provide a gate signal to the pixel portion in the peripheral area on the base substrate. A first base substrate partitioned into a display area where an image is displayed and a peripheral area surrounding the display area, a first color filter layer formed on the first base substrate corresponding to the display area, and corresponding to the peripheral area A lower substrate having a second color filter layer formed on the first base substrate; An upper substrate having a second base substrate facing the first base substrate and a common electrode formed on the second base substrate; And And a liquid crystal layer provided between the upper substrate and the lower substrate. The method of claim 16, wherein the lower substrate, A common electrode line formed in the display area on the first base substrate and electrically connected to the common electrode; And And a third output line formed to partially surround the display area in the peripheral area on the first base substrate, and disposed on a layer different from the common electrode line and electrically connected to the common electrode line. A liquid crystal display device. 18. The liquid crystal display of claim 17, wherein the second color filter layer is provided in a region other than a region in which the third output line and the common electrode line are electrically connected to each other.

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