KR20060136205A - Method of manufacturing a Non-volatile memory device - Google Patents

Abstract

In a method of manufacturing a nonvolatile memory device capable of shortening a process, gate structures are formed on a substrate including a common source line forming region and a contact region. A first interlayer insulating layer pattern may be formed on the substrate, the first interlayer insulating layer pattern including a first linear opening to expose a common source line forming region of the substrate and a second opening to expose the contact region. A common source line is formed in the first opening and a contact pad is formed in the second opening. A second interlayer insulating layer pattern including a third opening exposing the contact pad is formed on the common source line, the contact pad, and the first interlayer insulating layer pattern. The common source line and the at least one contact pad may be simultaneously formed by forming a wire connected to the contact pad through a third opening on the second interlayer insulating layer pattern. The method can shorten the manufacturing process of the nonvolatile memory device.

Description

Method of manufacturing a non-volatile memory device

1 to 4 are cross-sectional views illustrating a method of manufacturing a conventional NAND type flash memory device.

FIG. 5 is a diagram illustrating a layout of a NAND type flash memory cell according to the first embodiment of the present invention, and FIG. 6 is a cross-sectional view of the NAND type flash memory cell obtained by cutting FIG. 5 in the Y-Y 'direction.

7 to 9 are cross-sectional views illustrating a method of manufacturing the NAND type flash memory cell shown in FIG. 6.

10 is a cross-sectional view of a NAND type flash memory cell according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 103 tunnel oxide film

104: floating gate 106: interlayer dielectric film

108: control gate 110: first interlayer insulating film pattern

113: first opening 114: common source line

115: second opening 116: bit line contact pad

220: second interlayer insulating film pattern 128: metal wiring

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a nonvolatile memory device including a common source line and a bit line contact pad.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. If you do this, you can maintain the status, but it can be divided into ROM (read only memory) products with slow data input and output. Among these ROM products, there is an increasing demand for electrically erasable and programmable ROM (EEPROM) or flash memory that can electrically input and output data. The flash memory device is an advanced form of EEPROM that can be electrically erased at high speed. The flash memory device electrically controls input and output of data by F-N tunneling or hot electron injection.

Looking at the flash memory device from a circuit point of view, a NAND type in which n cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line. Each cell transistor can be classified into a NOR type connected in parallel between the bit line and the ground line. The NOR type is advantageous for high speed operation, while the NAND type is advantageous for high integration.

1 to 4 are cross-sectional views illustrating a method of manufacturing a conventional NAND type flash memory device.

Referring to FIG. 1, gate structures 12 of a memory cell transistor and a selection transistor are formed on a substrate 10. The substrate 10 includes a common source line forming region A, a bit line contact region B, and a metal wiring contact region C.

Subsequently, after the first interlayer insulating film is formed on the substrate 10 on which the gate structure 12 is formed, a common source line is selectively etched by selectively etching the first interlayer insulating film by a general photolithography process. A first interlayer insulating film pattern 20 including a first opening (not shown) in which the CSL is to be formed. Subsequently, conductive material deposition and a first chemical mechanical polishing process are performed to form a common source line 22 in the first opening.

Referring to FIG. 2, after forming the second interlayer insulating film on the resultant material on which the common source line 22 is formed, the second interlayer insulating film and the first interlayer insulating film pattern may be selectively etched by a conventional photolithography process. A second interlayer insulating film pattern 30 including a second opening (not shown) exposing the bit line contact region B of the substrate is formed. Subsequently, the conductor deposition and the second chemical mechanical smoke deposition process are performed to form the bitline contact pads 32 in the second openings.

Referring to FIG. 3, the second interlayer insulating layer pattern 30 is selectively etched by a conventional photolithography process to form a third opening (not shown) exposing the metal wiring contact region C of the substrate. . Subsequently, a conductive deposit and a third chemical mechanical smoke deposition process are performed to form the metallization contact pad 34 in the third opening.

Referring to FIG. 4, a conductive material is deposited on the resultant to form conductive wires 36 connected to the bit line contact pads and the metal wire contact pads. The conductive wires correspond to bit lines and metal wires.

According to the above-described conventional method, at least three chemical mechanical polishing processes and an opening forming process should be performed to form a common source line, bit line contact pad, and metal wiring contact pad.

In addition, since the heights of the first and second interlayer insulating films, which are applied as the degree of integration of the nonvolatile device is increased, it is difficult to form the third opening of FIG. 3 to have a constant diameter, and the substrate is formed by the openings. The problem of not being exposed is caused. In addition, increasing the height of the interlayer insulating film means increasing the depth of the opening. Accordingly, a problem arises in that voids are generated in the bit line contact pads formed in the openings and the contact pads of the metal wiring.

Accordingly, an object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of simultaneously forming a common source line and at least one contact pad.

In the method of manufacturing a nonvolatile memory device according to an embodiment of the present invention for achieving the above object, the gate structures are formed on a substrate including a common source line forming region and a contact region. A first interlayer insulating layer pattern may be formed on the substrate to cover the gate structure, the first interlayer insulating layer pattern including a common source line forming region of the substrate and a first opening exposing the contact region. A common source line and a contact pad are formed in the first opening. A second interlayer insulating layer pattern including a second opening exposing the contact pad is formed on the common source line, the contact pad, and the first interlayer insulating layer pattern. A nonvolatile memory device capable of simultaneously forming the common source line and the at least one contact pad may be manufactured by forming a wire connected to the contact pad through a second opening on the second interlayer insulating layer pattern.

In the method of manufacturing a nonvolatile memory device according to a specific embodiment of the present invention for achieving the above object, n word lines on the substrate divided into a cell region and a peripheral region, and the first of the n word lines A string select line adjacent to the word line and a ground select line adjacent to the nth word line are formed. A first interlayer insulating film is formed on the substrate on which the n word lines, the string select lines, and the ground select lines are formed. A first opening exposing the substrate between the ground selection lines by etching the first interlayer insulating film, a second opening exposing the substrate between the string selection lines, and a third opening exposing a peripheral region of the substrate; A first interlayer insulating film pattern is formed. A common source line is formed in the first opening, a bit line contact pad is formed in the second opening, and a metal wiring contact pad is formed in the third opening. A fourth opening exposing the bit line contact pad on the common source line, the bit line contact pad, the metal wiring contact pad, and the first interlayer insulating layer pattern, and a fifth opening exposing the metal wiring contact pad. A second interlayer insulating film pattern is formed. Subsequently, a common source line and at least one contact pad may be simultaneously formed by forming a wire connected to the bit line contact pad and the metal wiring contact pad through a fourth opening and a fifth opening on the second interlayer insulating layer pattern. A nonvolatile memory device can be manufactured.

In the method, the first interlayer insulating layer pattern may be formed by forming an first interlayer insulating layer covering the substrate on which the gate structure is formed, and then performing an etching process using an etching mask to form a common source line forming region of the substrate on the first interlayer insulating layer. It can be formed by forming a first opening that exposes the contact region of the substrate.

The common source line and the contact pad may be formed by forming a conductive film on the first interlayer insulating film pattern to fill the first opening, and then chemically mechanically polishing the conductive film so that the surface of the first interlayer insulating film pattern is exposed. can do.

According to the present invention, when forming a common source line, a bit line contact pad and a metal wiring contact pad are formed at the same time, and then an insulating layer pattern having openings exposing the contact pads is formed.

Accordingly, since bit line contact holes are formed on the bit line contact pads, misaligned margins can be secured during a photolithography process for forming bit line contact holes. In addition, during the above-described photolithography process, an etching margin may be secured due to a lower interlayer insulating layer step.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a diagram illustrating a layout of a NAND type flash memory cell according to the first embodiment of the present invention, and FIG. 6 is a cross-sectional view of the NAND type flash memory cell obtained by cutting FIG. 5 in the Y-Y 'direction.

5 and 6, the active regions 102 in which the channels and the sources / drains of the memory cell transistors are to be formed are spaced apart by the field regions 101 and extended in the Y axis in parallel with each other, and are repeated in the X axis. Are arranged.

N word lines (W / L ₁ , W / L ₂ ,..., W / L _n ) are repeatedly arranged in the Y-axis while extending in the X-axis on the active region 102, thereby controlling the floating gate 104 and the control. Stacked gate cell memory cell transistors are formed. Thus, a high concentration source / drain region (not shown) is formed on the surface of the exposed active region 102 between word lines W / L ₁ , W / L ₂ ,..., W / L _n spaced at predetermined intervals. Are formed.

A plurality of memory cell arrays arranged in the XY direction by an array of the active region 102 extending in the Y axis and the word lines W / L ₁ , W / L ₂ ,..., W / L _n extending in the X axis. When forming a, a string select line (SSL) and a ground select line (GSL), which are select transistors, are respectively disposed outside the first word line (W / L ₁ ) and the nth word line (W / L _n ). Form a "string" as a memory unit of the &quot; string &quot; In the string, n memory cell transistors are connected in series while sharing a source / drain.

Select transistors constituting the string select line SSL and the ground select line GSL have a floating gate 104 in the field region 101 between each input / output I / O to prevent signal delay caused by a resistor. ) And a butting contact hole (not shown) for connecting the control gate 108. Thus, the select transistors operate as MOS transistors having electrically one gate.

One bit line contact pad 116 is provided between the string selection lines SSL adjacent to each other, and the two strings share one bit line contact pad 116 in the form of a mirror image. The word lines W / L ₁ , W / L ₂ ,..., W / L _n extend on the Y-axis so as to be orthogonal to the word lines through the first interlayer insulating film 110 and the second interlayer insulating film 120. K bit lines (B / L _k , B / L _k-1 , B / L _k-2 ,...) Repeated on the X axis are formed. Another outer side of the "string" is provided with a common source line 114 extending in the X-axis direction between adjacent ground select lines GSL, and each of the plurality of bit lines on the common source line 114. One contact hole (not shown) is formed.

Referring to FIG. 6, the common source line 114 and the bit line contact pads 116 are planarized to the same height as the first interlayer insulating pattern 110 while the openings 113 and 115 formed in the first interlayer insulating layer pattern are buried. Are formed at the same time. Thereafter, a bit line 128 connected to the bit line contact pad is formed on the second interlayer insulating layer pattern 120 having the opening 122 exposing the bit line contact pad 116.

7 to 9 are cross-sectional views illustrating a method of manufacturing the NAND type flash memory cell shown in FIG. 6.

Referring to FIG. 7, an isolation layer (not shown) is formed on the substrate 100 to define the substrate 100 as an active region and an isolation region. The device isolation layer may be formed by performing a shallow trench isolation (STI) process. The substrate 100 includes a common source line forming region A and a contact region B. FIG. In particular, the contact region B includes a region connected to the contact pad of the metal line and a region connected to the contact pad of the bit line.

Subsequently, a tunnel oxide film (ie, a gate oxide film) 103 is formed on the substrate in the active region. The tunnel oxide film 103 may be formed by performing a thermal oxidation process, a chemical vapor deposition process, an atomic layer deposition process, or the like. Alternatively, in order to vary the thickness of the tunnel oxide layer between the selection transistor and the cell transistor, the gate oxide layer is grown on the substrate 100, and then the gate oxide layer of the cell transistor region is removed by a wet etching process using a photolithography process. 103 may be formed.

After forming a first conductive layer (not shown) to be used as a floating gate of the cell transistor on the gate oxide layer, the first conductive layer is selectively etched by a conventional photolithography process. Examples of the first conductive film include a doped polysilicon film or a metal film.

A dielectric film is formed on the selectively etched first conductive film. Examples of the dielectric film include an ONO film and a metal oxide film.

A second conductive layer to be used as a control gate of the cell transistor is formed on the dielectric layer. Examples of the second conductive film include a doped polysilicon film, a metal film, a composite film in which a polysilicon film and a tungsten silicide film are laminated.

Subsequently, after forming a photoresist pattern exposing the memory cell region by a photo process, the second conductive layer, the dielectric layer, and the first conductive layer exposed to the photoresist pattern are sequentially dry-etched to form the gate WL of the cell transistor. To form. At the same time, the string select transistor SSL and the gates GSL of the ground select transistor are formed. The gate WL of the cell transistor, the gate SSL of the string select transistor, and the gate GSL of the ground select transistor include a floating gate 104, an interlayer dielectric layer 106, and a control gate 108.

For example, a well-known self-aligned shallow trench isolation (SA-STI) process may be performed to simultaneously form a device isolation layer and a floating gate. In this case, in order to increase the area of the interlayer dielectric film 106, the conductive film for the floating gate may be deposited again after the device isolation process. Subsequently, source / drain regions (not shown) of the cell transistors and the selection transistors are formed by a conventional ion implantation process.

Thereafter, a first interlayer insulating film (not shown) is formed on a substrate on which the gate WL, the string select transistor SSL, and the ground select transistor SSL of the cell transistor are formed. The first interlayer insulating layer uses an oxide such as boro-phosphor silicate glass (BPSG), phosphor silicate glass (PSG), undoped silicate glass (USG), spin on glass (SOG), plasma enhanced-tetraethylorthosilicate (PE-TEOS), or the like. Can be formed. The first interlayer dielectric layer may be formed using a chemical vapor deposition process, a plasma enhanced chemical vapor deposition (PE-CVD) process, an atomic layer deposition process, or a high density plasma chemical vapor deposition (HDP-CVD) process.

Subsequently, the first interlayer dielectric layer may be dry-etched by a photolithography process to form a first interlayer dielectric layer pattern 110. The first interlayer insulating layer pattern may include a first opening 113 exposing a substrate (common source line forming region) between adjacent ground selection lines GSL and a substrate (contact) between adjacent string selection lines SSL. A second opening 115 exposing the region). For example, the first insulating layer pattern may further include a third opening (not shown) that exposes a peripheral region of the substrate.

Referring to FIG. 8, a third conductive layer (not shown) is buried in the first layer insulating layer pattern 110 including the first opening 113 and the second opening 115. C). As an example of the said 3rd conductive film, the metal film which consists of tungsten, aluminum, and titanium is mentioned.

After forming the third conductive layer, an etch back or chemical mechanical polishing (CMP) process is performed to remove the third conductive layer until the surface of the first interlayer insulating layer pattern 110 is exposed. Then, a common source line 114 is formed in the first opening 113, and a contact pad 116 is formed in the second opening 113. The common source line 114 and the contact pads 116 of the bit line are simultaneously formed.

For example, when a third opening is formed in the first interlayer insulating layer pattern, a contact pad (not shown) of a metal wiring is formed in the third opening.

Referring to FIG. 9, a second interlayer insulating layer is formed on the common source line 114, the bit line contact pads 116, and the first interlayer insulating layer pattern 110. Since the method for forming the second interlayer insulating film and the oxide for forming the second interlayer insulating film have been described in detail above, they are omitted.

Subsequently, the second interlayer dielectric layer is dry-etched by a photolithography process to form a second interlayer dielectric layer pattern 120. The second interlayer dielectric pattern includes a fourth opening 122 exposing the bit line contact pad 116. For example, the second interlayer insulating layer pattern 120 may further include a fifth opening (not shown) exposing a metal wiring contact pad (not shown) formed in the peripheral area of the substrate.

Subsequently, a fourth conductive layer is formed on the second interlayer insulating layer pattern 118 including the fourth opening 122 to bury the fourth opening. Accordingly, as illustrated in FIG. 6, a conductive line 128 including a bit line plug connected to the bit line contact pad 116 is formed. The conductive wiring 128 is a bit line. Examples of the fourth conductive film include a metal film made of tungsten, aluminum and titanium. As the fourth conductive film, a tungsten film is preferably used.

The bit line 128 is connected to the exposed substrate between the gates SSL of neighboring string select lines through the bit line contact pad 115a.

As described above, according to the first embodiment of the present invention, the bit line contact pads 116 may be simultaneously formed when the common source line 114 is formed, thereby minimizing the semiconductor manufacturing process. In addition, since the bit line forming opening 122 is formed on the bit line contact pad 116, a misalignment margin and an etching margin may be secured during the photolithography process for forming the bit line forming opening 120. Can be.

10 is a cross-sectional view of a NAND type flash memory cell according to a second embodiment of the present invention.

Hereinafter, a method of manufacturing a NAND flash memory cell according to a second embodiment of the present invention will be described with reference to FIG. 10. The steps of forming the gate WL of the cell transistor, the string select transistor SSL, the gate SSL of the ground select transistor, and the interlayer insulating layer on the substrate are the same as in the above-described embodiment, and thus description thereof will be omitted. . Here, reference numeral 200 denotes a substrate, 203 a tunnel oxide film, 204 a floating gate, 206 an interlayer dielectric film, and 208 a control gate.

In the same manner as in the first embodiment, the first interlayer insulating layer pattern may include a second opening 215 and a substrate exposing the substrate (contact region) between the first opening 213 and the adjacent string select line SSL. It may further include a third opening 217 exposing the peripheral region (C) of the.

The first opening, the second opening, and the third opening may be buried in the first layer insulating film pattern 210 including the first opening 213, the second opening 215, and the third opening 217. 3 conductive film (not shown) is formed. The third conductive film is a tungsten film. After forming the third conductive layer, an etch back or chemical mechanical polishing (CMP) process is performed to remove the third conductive layer until the surface of the first interlayer insulating layer pattern 210 is exposed. Then, a common source line 214 is formed inside the first opening 213, a contact pad 216 of a bit line is formed inside the second opening 213, and a third opening 217. The contact pads 218 of metal wirings are formed in the interior thereof. The common source line 214, the bit pad contact pad 216, and the metal wire contact pad 218 are formed at the same time.

A second interlayer insulating film is formed on the common source line 214, the bit pad contact pad 216, the metal wiring contact pad 218, and the first interlayer insulating film pattern 210. Since the method for forming the second interlayer insulating film and the oxide for forming the second interlayer insulating film have been described in detail above, they are omitted. Subsequently, the second interlayer dielectric layer is dry etched to form a second interlayer dielectric layer pattern 220. The second interlayer insulating film pattern 220 includes a fourth opening 222 exposing the bit line contact pad 216 and a fifth opening 224 exposing the contact pad 218 of a metal wiring. do.

Subsequently, a fourth conductive layer is formed on the second interlayer insulating layer pattern 220 to bury the fourth opening 222 and the fifth opening 224. Accordingly, as illustrated in FIG. 10, a conductive line 228 including a bit line plug connected to the bit line contact pad 216 and a metal wire plug (not shown) connected to the contact pad 218 of the metal wiring. ) Is formed. The conductive wiring 228 is a bit line. The fourth conductive film is a tungsten film.

As described above, according to the second embodiment of the present invention, when forming the common source line 214, the bit line contact pad 216 and the metallization contact pad 218 can be formed simultaneously, thereby minimizing the semiconductor manufacturing process. Can be shortened.

As described above, according to the present invention, when forming a common source line, the bit line contact pad and the metal wiring contact pad can be formed at the same time, thereby minimizing the semiconductor manufacturing process.

In addition, openings for forming bit lines and metal wirings may be formed on the bit line contact pads and the metal wiring contact pads, respectively, to secure misalignment margins and etching margins during the photolithography process for forming the openings. Can be. In addition, an etching margin according to the height of the interlayer insulating layer may be secured during the interlayer insulating layer etching process.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (6)

Forming a first interlayer insulating film pattern covering a gate structure on the substrate, the first interlayer insulating layer pattern including a linear first opening to expose a common source line forming region of the substrate and a second opening to expose a contact region of the substrate; Forming a common source line in the first opening and a contact pad in the second opening; Forming a second interlayer insulating layer pattern on the common source line, the contact pad and the first interlayer insulating layer pattern, the second interlayer insulating layer pattern including a third opening exposing the contact pad; And And forming a wire connected to the contact pad through a third opening on the second interlayer insulating layer pattern. The method of claim 1, wherein the forming of the first interlayer insulating film pattern comprises: Forming a first interlayer insulating film covering the substrate on which the gate structure is formed; Performing an etching process using an etching mask to form a first opening exposing a common source line forming region of the substrate and a second opening exposing a contact region of the substrate in the first interlayer insulating layer; A method of manufacturing a nonvolatile memory device. The method of claim 1, wherein the forming of the common source line and the contact pad comprises: Forming a conductive film on the first interlayer insulating film pattern to fill the first and second openings; And And chemically polishing the conductive layer to expose the surface of the first interlayer insulating layer pattern to simultaneously form the common source line and the contact pad. The method of claim 1, wherein the contact region comprises a bit line contact region and a metal wiring contact region. The method of claim 1, wherein the contact pad comprises a bit line contact pad and a metal wire contact pad. On the substrate divided into a cell region and a peripheral region, n word lines WL, a string select line SSL adjacent to the first word line among the n word lines, and a ground select line adjacent to the nth word line ( Forming GSL); Forming a first interlayer dielectric layer on a substrate on which the n word lines, string select lines, and ground select lines are formed; A third first opening exposing the substrate between the ground selection lines by etching the first interlayer insulating layer, a second opening exposing the substrate between the string selection lines, and a third region exposing the peripheral region of the substrate; Forming a first interlayer insulating film pattern including openings; Simultaneously forming a common source line in the first opening, a bitline contact pad in the second opening, and a metallization contact pad in the third opening; A fourth opening exposing the bit line contact pad and a fifth opening exposing the metal wiring contact pad on the common source line, the bit line contact pad, the metal wiring contact pad, and the first interlayer insulating layer pattern. Forming a second interlayer insulating film pattern; And And forming a wire connected to the bit line contact pad and the metal wire contact pad through a fourth opening and a fifth opening on the second interlayer insulating layer pattern.

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