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KR20060131129A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR20060131129A
KR20060131129A KR1020050051343A KR20050051343A KR20060131129A KR 20060131129 A KR20060131129 A KR 20060131129A KR 1020050051343 A KR1020050051343 A KR 1020050051343A KR 20050051343 A KR20050051343 A KR 20050051343A KR 20060131129 A KR20060131129 A KR 20060131129A
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layer
film
diffusion barrier
semiconductor device
contact plug
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이성권
정태우
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 컨택 플러그 형성시 절연막 상에 플러그 찌꺼기가 잔류하는 것을 방지하면서 반도체 소자의 금속배선 증착공정시 보이드 발생을 억제할 수 있는 반도체 소자 제조방법을 제공하기 위한 것으로, 이를 위해 본 발명에서는 반도체 기판 상에 절연막을 형성하는 단계와, 상기 절연막 상에 희생막을 증착하는 단계와, 상기 희생막 및 상기 절연막을 식각하여 상기 기판을 노출시키는 컨택홀을 형성하는 단계와, 상기 컨택홀을 포함한 전체 구조 상부의 단차를 따라 확산방지막을 증착하는 단계와, 상기 컨택홀이 매립되도록 상기 확산방지막 상에 컨택 플러그용 도전층을 증착하는 단계와, 상기 절연막과 상기 확산방지막 및 상기 컨택 플러그용 도전층 간의 식각 선택비를 이용한 식각공정을 통해 상기 확산방지막 및 상기 컨택 플러그용 도전층을 일정 깊이로 리세스시키는 단계와, 상기 희생막을 제거하는 단계와, 상기 절연막을 포함한 전체 구조 상부에 금속배선을 증착하는 단계를 포함하는 반도체 소자 제조방법을 제공한다.The present invention is to provide a method for manufacturing a semiconductor device that can suppress the generation of voids during the metallization deposition process of the semiconductor device while preventing the plug residue on the insulating film when forming the contact plug of the semiconductor device, the present invention for this purpose The method may further include forming an insulating film on a semiconductor substrate, depositing a sacrificial film on the insulating film, forming a contact hole to expose the substrate by etching the sacrificial film and the insulating film, and including the contact hole. Depositing a diffusion barrier along the step of the entire structure, depositing a contact plug conductive layer on the diffusion barrier so that the contact hole is filled, the insulating layer, the diffusion barrier and the conductive layer for contact plug The diffusion barrier and the contact plug through an etching process using an etching selectivity between Provides the step of removing the steps of the conductive layer for the recessed by a predetermined depth, the sacrificial film, and a semiconductor device manufacturing method comprising the step of depositing a metal wiring on the entire upper structure including the insulating film.

Description

반도체 소자 제조방법{METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}

도 1 내지 도 5는 종래 기술에 따른 반도체 소자 제조방법을 도시한 공정단면도.1 to 5 are process cross-sectional views showing a method of manufacturing a semiconductor device according to the prior art.

도 6은 종래 기술에 따른 반도체 소자의 금속배선에 나타난 보이드 현상을 도시한 SEM 사진.6 is a SEM photograph showing a void phenomenon in the metal wiring of the semiconductor device according to the prior art.

도 7은 종래 기술에 따른 반도체 소자의 금속배선에 나타난 보이드 현상을 도시한 TEM 사진.7 is a TEM photograph showing a void phenomenon in a metal wiring of a semiconductor device according to the prior art.

도 8 내지 도 11은 본 발명의 바람직한 실시예에 따른 반도체 소자 제조방법을 도시한 공정단면도.8 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

10, 110 : 반도체 기판 11, 111 : 제1 절연막10, 110: semiconductor substrate 11, 111: first insulating film

12, 112 : 컨택 플러그 13, 113 : 제2 절연막12, 112: contact plug 13, 113: second insulating film

14, 115 : 포토레지스트 패턴 15, 117 : 컨택홀14, 115: photoresist pattern 15, 117: contact hole

17, 119 : 확산 방지막 18, 120 : 컨택 플러그용 도전층17, 119: diffusion barrier films 18, 120: conductive layer for contact plug

19, 116 : 식각공정 17a, 120a : 컨택 플러그19, 116: etching process 17a, 120a: contact plug

18a : 플러그 찌꺼기 S : 심18a: Plug residue S: Shim

20, 121 : 금속배선 V : 보이드20, 121: metal wiring V: void

114 : 희생막114: sacrifice

본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 80㎚ 이내의 디자인룰(Design rule)을 갖는 반도체 소자의 컨택 플러그 및 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact plug and a metal wiring of a semiconductor device having a design rule within 80 nm.

최근 반도체 소자의 미세화와 배선의 다층화 추세에 따라 컨택홀(contact hole) 또는 비아(via)홀의 깊이가 점점 더 깊어지고 있다. 이에 따라, 컨택홀 또는 비아홀에 매립되는 컨택 플러그 형성시 컨택 플러그의 손실(loss)이 발생된다. 이러한 컨택 플러그의 손실은 후속공정을 통해 컨택 플러그 상부에 형성될 금속배선의 손실을 일으키는 원인이 된다.Recently, as the semiconductor devices become more miniaturized and the wirings become more multiplied, the depths of contact holes or via holes are becoming deeper. Accordingly, loss of the contact plug occurs when the contact plug is buried in the contact hole or the via hole. Such a loss of the contact plug causes a loss of metal wiring to be formed on the contact plug through a subsequent process.

도 1 내지 도 5는 종래 기술에 따른 반도체 소자의 금속배선 형성방법을 도시한 공정단면도이다.1 to 5 are process cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.

먼저, 도 1에 도시된 바와 같이, 기판(10) 상에 컨택 플러그(12) 또는 금속배선을 포함한 소정의 하부 반도체 구조물층이 개재된 제1 절연막(11)을 형성한다. 그런 다음, 제1 절연막(11)을 포함한 전체 구조 상부에 제2 절연막(13)을 증착한 후, 포토리소그래피(photolithography) 공정을 통해 제2 절연막(13) 상에 포토레지스트 패턴(14)을 형성한다.First, as shown in FIG. 1, the first insulating layer 11 having a predetermined lower semiconductor structure layer including a contact plug 12 or a metal wiring is formed on the substrate 10. Then, after the second insulating film 13 is deposited on the entire structure including the first insulating film 11, the photoresist pattern 14 is formed on the second insulating film 13 through a photolithography process. do.

이어서, 포토레지스트 패턴(14)을 통해 제2 절연막(13)을 식각하여 컨택 플러그(12)를 노출시키는 컨택홀(15)을 형성한다.Subsequently, the second insulating layer 13 is etched through the photoresist pattern 14 to form the contact hole 15 exposing the contact plug 12.

이어서, 도 2에 도시된 바와 같이, 스트립(strip) 공정을 실시하여 포토레지스트 패턴(14, 도 1 참조)을 제거하고, 컨택홀(15, 도 1 참조)이 형성된 전체 구조 상부의 단차를 따라 확산방지막(17)을 증착한다. 그런 다음, 컨택홀(15)이 매립되도록 확산 방지막(17) 상에 텅스텐과 같은 플러그 도전층(18)을 CVD(Chemical Vapor Deposition) 방식으로 증착한다. 이때, 컨택홀(15)의 깊이가 깊어 컨택홀(15)의 중앙부에서는 플러그 도전층(18)의 심(seam, S) 현상이 불가피하다.Subsequently, as shown in FIG. 2, a strip process is performed to remove the photoresist pattern 14 (see FIG. 1), and to follow the steps of the entire structure where the contact holes 15 (see FIG. 1) are formed. The diffusion barrier 17 is deposited. Then, a plug conductive layer 18 such as tungsten is deposited on the diffusion barrier layer 17 by CVD (Chemical Vapor Deposition) so that the contact hole 15 is filled. At this time, since the depth of the contact hole 15 is deep, the phenomenon of seam S of the plug conductive layer 18 is inevitable in the center portion of the contact hole 15.

이어서, 도 3에 도시된 바와 같이, 금속과 절연막 간의 식각선택비를 이용한 에치백(etch back) 공정(19)을 실시하여, 심(S)이 노출되지 않도록 플러그 도전층(18) 및 확산방지막(17)을 제1 깊이(H1)로 식각한다. Next, as shown in FIG. 3, an etch back process 19 using an etching selectivity between the metal and the insulating layer is performed, so that the plug conductive layer 18 and the diffusion barrier layer are not exposed. Etch 17 to the first depth H 1 .

그러나, 이처럼 심(S)이 노출되지 않도록 플러그 도전층(18) 및 확산방지막(17)을 제1 깊이(H1)로 식각하면, 제2 절연막(13) 상부에 플러그 도전층(18)의 찌꺼기(18a)가 잔류하게 되는 문제점이 있다. 결국, 이러한 플러그 찌꺼기(18a)를 제거하기 위해서 종래에는 도 4에 도시된 바와 같이, 플러그 도전층(18) 및 확산방지막(17)을 제1 깊이(H1)보다 깊은 제2 깊이(H2)로 과도식각하였다.However, when the plug conductive layer 18 and the diffusion barrier 17 are etched to the first depth H 1 such that the shim S is not exposed, the plug conductive layer 18 may be formed on the second insulating layer 13. There is a problem that the residue 18a remains. As a result, in order to remove the plug dregs 18a, as shown in FIG. 4, the plug conductive layer 18 and the diffusion barrier layer 17 have a second depth H 2 deeper than the first depth H 1 . Over-etched).

그리고, 도 5에 도시된 바와 같이, PVD(Physical Vapor Depostion) 방식으로 금속배선(20)을 증착한다. 통상적으로 현재 80㎚ 이내의 디자인 룰을 갖는 반도체 소자의 금속배선 증착시에는 PVD 방식을 이용하고 있다. 그러나, 이러한 PVD 방식은 매립특성이 나쁜 문제점이 있다.Then, as shown in Figure 5, the metal wiring 20 is deposited by PVD (Physical Vapor Depostion) method. In general, the PVD method is used to deposit metal wires of semiconductor devices having design rules within 80 nm. However, this PVD method has a problem of poor landfill characteristics.

결국, 도 4에서와 같이, 플러그 도전층(18) 및 확산방지막(17)을 제2 깊이(H2)로 식각하면 플러그 도전층(18)과 제2 절연막(13) 간의 단차가 증가하여 금속배선(20)의 증착공정시 노출된 심(S)의 상부에서 보이드(V, void)가 발생하는 문제점이 있다. 이러한 금속배선의 보이드 현상은 도 5 및 도 6에 자세히 도시되었다.As a result, as shown in FIG. 4, when the plug conductive layer 18 and the diffusion barrier layer 17 are etched to the second depth H 2 , the step difference between the plug conductive layer 18 and the second insulating layer 13 is increased to form a metal. In the deposition process of the wiring 20, there is a problem in that voids V and voids are generated on the exposed shim S. The void phenomenon of the metallization is shown in detail in FIGS. 5 and 6.

따라서, 본 발명은 상기한 문제점을 해결하기 위하여 제안된 것으로, 반도체 소자의 컨택 플러그 형성시 절연막 상에 플러그 찌꺼기가 잔류하는 것을 방지하는 반도체 소자 제조방법을 제공하는 것을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device which prevents plug residues from remaining on an insulating layer when forming a contact plug of a semiconductor device.

또한, 본 발명의 다른 목적은 반도체 소자의 금속배선 증착공정시 보이드 발생을 억제할 수 있는 반도체 소자 제조방법을 제공하는데 있다.In addition, another object of the present invention to provide a semiconductor device manufacturing method that can suppress the generation of voids during the metallization deposition process of the semiconductor device.

상기에서 설명한 목적을 달성하기 위한 일측면에 따른 본 발명은, 반도체 기판 상에 절연막을 형성하는 단계와, 상기 절연막 상에 희생막을 증착하는 단계와, 상기 희생막 및 상기 절연막을 식각하여 상기 기판을 노출시키는 컨택홀을 형성하 는 단계와, 상기 컨택홀을 포함한 전체 구조 상부의 단차를 따라 확산방지막을 증착하는 단계와, 상기 컨택홀이 매립되도록 상기 확산방지막 상에 컨택 플러그용 도전층을 증착하는 단계와, 상기 절연막과 상기 확산방지막 및 상기 컨택 플러그용 도전층 간의 식각 선택비를 이용한 식각공정을 통해 상기 확산방지막 및 상기 컨택 플러그용 도전층을 일정 깊이로 리세스시키는 단계와, 상기 희생막을 제거하는 단계와, 상기 절연막을 포함한 전체 구조 상부에 금속배선을 증착하는 단계를 포함하는 반도체 소자 제조방법을 제공한다.According to an aspect of the present invention, there is provided a method of forming an insulating film on a semiconductor substrate, depositing a sacrificial film on the insulating film, and etching the sacrificial film and the insulating film. Forming a contact hole for exposing, depositing a diffusion barrier along a step of an upper portion of the entire structure including the contact hole, and depositing a conductive layer for a contact plug on the diffusion barrier to fill the contact hole And recessing the diffusion barrier layer and the contact plug conductive layer to a predetermined depth through an etching process using an etching selectivity between the insulating layer, the diffusion barrier layer, and the contact plug conductive layer, and removing the sacrificial layer. And depositing a metal wiring on the entire structure including the insulating layer. Provide corrective measures.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 다양한 실시예를 첨부된 도면을 참조하여 설명하기로 한다. 또한, 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장되어진 것이며, 층이 다른 층 또는 기판 "상"에 있다고 언급되어지는 경우에 그것은 다른 층 또는 기판 상에 직접 형성될 수 있거나, 또는 그들 사이에 제3의 층이 개재될 수도 있다. Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween.

실시예Example

도 8 내지 도 11은 본 발명의 바람직한 실시예에 따른 반도체 소자 제조방법을 도시한 공정단면도이다. 여기서, 도 8 내지 도 11에 도시된 참조부호들 중 서로 동일한 참조부호는 동일한 기능을 하는 동일 요소이다. 8 to 11 are process cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 8 to 11 are the same elements having the same function.

먼저, 도 8에 도시된 바와 같이, 소정의 반도체 구조물층이 형성된 반도체 기판(110) 상에 제1 절연막(111)을 증착한다. 여기서, 반도체 구조물층은 트랜지스 터와 같은 복수의 능동소자와 저항, 캐패시터, 인덕터 등의 수동소자와 복수의 메모리셀과 금속배선과 금속 플러그 등을 포함한다. First, as shown in FIG. 8, the first insulating layer 111 is deposited on the semiconductor substrate 110 on which the predetermined semiconductor structure layer is formed. Here, the semiconductor structure layer includes a plurality of active elements such as transistors, passive elements such as resistors, capacitors, and inductors, a plurality of memory cells, metal wires, metal plugs, and the like.

이어서, 제1 절연막(111)을 식각하여 기판(110)의 일정 영역을 노출시키는 컨택홀(미도시)을 형성한 다음, 컨택홀이 매립되는 금속 컨택 플러그(112; 이하, 제1 컨택 플러그라 함)를 형성한다.Subsequently, the first insulating layer 111 is etched to form a contact hole (not shown) that exposes a predetermined region of the substrate 110, and then a metal contact plug 112 having a contact hole embedded therein; Form).

이어서, 제1 컨택 플러그(112)를 포함한 제1 절연막(111) 상에 제2 절연막(113)을 증착한다. 이때, 제2 절연막(113)은 층간절연막(ILD : Inter Layer Dilectric)으로 산화막 계열의 물질로 형성한다. 예컨대, 제2 절연막(113)은 HDP(High Density Plasma) 산화막, BPSG(Boron Phosphorus Silicate Glass)막, PSG(Phosphorus Silicate Glass)막, PETEOS(Plasma Enhanced Tetra Ethyle Ortho Silicate)막, PECVD(Plasma Enhanced Chemical Vapor Deposition)막, USG(Un-doped Silicate Glass)막, FSG(Fluorinated Silicate Glass)막, CDO(Carbon Doped Oxide)막 및 OSG(Organic Silicate Glass)막 중 어느 하나를 이용하여 단층막 또는 이들이 적층된 적층막으로 형성한다.Subsequently, a second insulating layer 113 is deposited on the first insulating layer 111 including the first contact plug 112. In this case, the second insulating layer 113 is an interlayer dielectric (ILD: inter layer dielectric) and is formed of an oxide-based material. For example, the second insulating layer 113 may include an HDP (High Density Plasma) oxide film, a BPSG (Boron Phosphorus Silicate Glass) film, a PSG (Phosphorus Silicate Glass) film, a PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, and a PECVD (Plasma Enhanced Chemical) film. A single layer film or a laminate thereof is formed by using any one of a vapor deposition (USG) film, a USG (Un-doped Silicate Glass) film, a FSG (Fluorinated Silicate Glass) film, a carbon doped oxide (CDO) film, and an organic Silicate Glass (OSG) film. It is formed of a laminated film.

이어서, 제2 절연막(113) 상에 희생막(114)을 증착한다. 이때, 희생막(114)은 제2 절연막(113)과 식각 선택비가 다른 물질로 형성한다. 바람직하게는, 희생막(114)은 제2 절연막(113)보다 식각 선택비가 높은 물질로 형성한다. 예컨대, 제2 절연막(113)이 산화막 계열의 물질로 이루어지면 희생막(114)은 질화막 계열의 물질로 형성한다. 바람직하게는, 질화막(nitride), 실리콘리치산화질화막(SRON, Silicon Rich Oxide Nitride) 및 실리콘산화질화막(SiON, Silicon Oxide Nitride) 의 일군에서 선택된 어느 하나로 형성한다. 한편, 제2 절연막(113)이 저유전상수 값(low-k)을 갖는 무기물(inorganic)로 이루어진 경우 희생막(114)은 유기물(organic) 폴리머(polymer)로 형성한다.Subsequently, a sacrificial layer 114 is deposited on the second insulating layer 113. In this case, the sacrificial layer 114 is formed of a material having a different etching selectivity from the second insulating layer 113. Preferably, the sacrificial layer 114 is formed of a material having a higher etching selectivity than the second insulating layer 113. For example, when the second insulating layer 113 is formed of an oxide film-based material, the sacrificial film 114 is formed of a nitride film-based material. Preferably, it is formed of any one selected from the group consisting of a nitride film, a silicon rich oxide nitride (SRON) and a silicon oxide nitride (SiON). Meanwhile, when the second insulating film 113 is made of an inorganic material having a low dielectric constant value (low-k), the sacrificial film 114 is formed of an organic polymer.

이어서, 희생막(114) 상에 포토레지스트(미도시)를 도포한 후, 포토마스크(미도시)를 이용한 노광공정 및 현상공정을 실시하여 포토레지스트 패턴(115)을 형성한다.Subsequently, after the photoresist (not shown) is coated on the sacrificial layer 114, an exposure process and a developing process using a photomask (not shown) are performed to form the photoresist pattern 115.

이어서, 포토레지스트 패턴(115)을 식각마스크로 이용한 식각공정(116)을 실시하여 희생막(113)과 제2 절연막(113)을 식각한다. 이로써, 제1 컨택 플러그(112)를 노출시키는 컨택홀(117)이 형성된다.Subsequently, an etching process 116 using the photoresist pattern 115 as an etching mask is performed to etch the sacrificial layer 113 and the second insulating layer 113. As a result, a contact hole 117 exposing the first contact plug 112 is formed.

이어서, 도 9에 도시된 바와 같이, 스트립 공정을 실시하여 포토레지스트 패턴(115, 도 8 참조)을 제거한다. Subsequently, as shown in FIG. 9, a strip process is performed to remove the photoresist pattern 115 (see FIG. 8).

이어서, 컨택홀(117)을 포함한 전체 구조 상부의 단차를 따라 확산방지막(119)을 증착한다. 이때, 확산방지막(119)은 후속공정을 통해 증착될 컨택 플러그용 도전층(120)이 제2 절연막(113)으로 확산되는 것을 방지한다. 예컨대, 확산방지막(119)은 Ti/TiN 또는 Ta/TaN으로 형성한다.Subsequently, the diffusion barrier 119 is deposited along the stepped portion of the entire structure including the contact hole 117. In this case, the diffusion barrier 119 prevents the contact plug conductive layer 120 to be deposited through the subsequent process from being diffused into the second insulating layer 113. For example, the diffusion barrier 119 is formed of Ti / TiN or Ta / TaN.

이어서, 컨택홀(117)이 매립되도록 확산방지막(119) 상에 컨택 플러그용 도전층(120)을 증착한다. 이때, 컨택홀(117)의 깊이가 깊어 증착된 컨택 플러그용 도전층(120) 내에 심(S)이 발생된다.Next, the contact plug conductive layer 120 is deposited on the diffusion barrier 119 so that the contact hole 117 is filled. In this case, the seam S is generated in the conductive plug 120 for the contact plug deposited because the depth of the contact hole 117 is deep.

이어서, 도 10에 도시된 바와 같이, 희생막(114)과 확산방지막(119) 및 컨택 플러그용 도전층(120) 간의 식각 선택비를 이용한 전면식각공정(etch back)을 실시 하여 확산방지막(119) 및 컨택 플러그용 도전층(120)을 일정 깊이(H3)로 리세스(recess)시킨다. 이로써, 심이 노출되는 컨택 플러그(120a; 이하, 제2 컨택 플러그라 함)가 형성된다.Subsequently, as shown in FIG. 10, the diffusion barrier 119 is formed by performing an etch back using an etching selectivity between the sacrificial layer 114, the diffusion barrier 119, and the contact plug conductive layer 120. ) And the contact plug conductive layer 120 are recessed to a predetermined depth H 3 . As a result, a contact plug 120a (hereinafter referred to as a second contact plug) to which the shim is exposed is formed.

이어서, 도 11에 도시된 바와 같이, 습식식각공정을 실시하여 희생막(114, 도 10 참조)을 식각한다. 이로써, 제2 절연막(113)과 제2 컨택 플러그(120a) 간의 표면 단차(H4)가 감소된다.Subsequently, as shown in FIG. 11, the sacrificial layer 114 (see FIG. 10) is etched by performing a wet etching process. As a result, the surface step H 4 between the second insulating film 113 and the second contact plug 120a is reduced.

이어서, 컨택 플러그(120a)를 포함한 제2 절연막(113) 상에 금속배선(121)을 증착한다. 이때, 금속배선(121)은 스텝 커버리지 특성이 나쁜 PVD 방식으로 증착하는데, 제2 절연막(113)과 제2 컨택 플러그(120a) 간의 표면 단차(H4)가 작아 금속배선(121) 내에 보이드가 발생하는 것을 억제할 수 있다.Subsequently, the metal wiring 121 is deposited on the second insulating layer 113 including the contact plug 120a. At this time, the metal wiring 121 is deposited by a PVD method having poor step coverage characteristics, and the void in the metal wiring 121 is small due to a small surface step H 4 between the second insulating film 113 and the second contact plug 120a. It can suppress generation.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

이상에서 설명한 바와 같이, 본 발명에 의하면, 상부에 희생막이 형성된 절연막 상에 컨택 플러그용 도전층을 증착한 후 희생막 상에 플러그 찌꺼기가 잔류하지 않을 깊이로 컨택 플러그용 도전층을 식각하여 컨택 플러그를 형성함으로써 컨 택 플러그 형성시 플러그 찌꺼기가 잔류됨을 방지할 수 있다.As described above, according to the present invention, after depositing a contact plug conductive layer on an insulating film having a sacrificial film formed thereon, the contact plug is etched by etching the contact plug conductive layer to a depth where no plug residues remain on the sacrificial film. By forming a to prevent plug residues remaining during the formation of the contact plug.

또한, 본 발명에 의하면, 상부에 희생막이 형성된 절연막 상에 컨택 플러그용 도전층을 증착한 후 컨택 플러그용 도전층을 식각하여 컨택 플러그를 형성한 다음 희생막을 제거함으로써 절연막과 컨택 플러그 간의 표면 단차를 감소시킨다. 따라서, 후속으로 컨택 플러그를 포함한 절연막 상에 PECVD 증착되는 금속배선에서 보이드 현상이 발생하는 것을 억제할 수 있다.In addition, according to the present invention, after depositing the contact plug conductive layer on the insulating film formed on the sacrificial layer, the contact plug conductive layer is etched to form a contact plug, and then the sacrificial film is removed to reduce the surface step between the insulating film and the contact plug. Decrease. Therefore, it is possible to suppress the occurrence of void phenomenon in the metal wiring which is subsequently PECVD deposited on the insulating film including the contact plug.

Claims (7)

반도체 기판 상에 절연막을 형성하는 단계;Forming an insulating film on the semiconductor substrate; 상기 절연막 상에 희생막을 증착하는 단계;Depositing a sacrificial film on the insulating film; 상기 희생막 및 상기 절연막을 식각하여 상기 기판을 노출시키는 컨택홀을 형성하는 단계;Etching the sacrificial layer and the insulating layer to form a contact hole exposing the substrate; 상기 컨택홀을 포함한 전체 구조 상부의 단차를 따라 확산방지막을 증착하는 단계;Depositing a diffusion barrier along a step of the entire structure including the contact hole; 상기 컨택홀이 매립되도록 상기 확산방지막 상에 컨택 플러그용 도전층을 증착하는 단계;Depositing a conductive layer for a contact plug on the diffusion barrier to fill the contact hole; 상기 절연막과 상기 확산방지막 및 상기 컨택 플러그용 도전층 간의 식각 선택비를 이용한 식각공정을 통해 상기 확산방지막 및 상기 컨택 플러그용 도전층을 일정 깊이로 리세스시키는 단계;Recessing the diffusion barrier layer and the contact plug conductive layer to a predetermined depth through an etching process using an etching selectivity between the insulating layer, the diffusion barrier layer, and the contact plug conductive layer; 상기 희생막을 제거하는 단계; 및Removing the sacrificial layer; And 상기 절연막을 포함한 전체 구조 상부에 금속배선을 증착하는 단계Depositing a metal wiring on the entire structure including the insulating film 를 포함하는 반도체 소자 제조방법.Semiconductor device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 희생막은 상기 절연막과의 식각 선택비를 이용하여 제거하는 반도체 소 자 제조방법.And removing the sacrificial layer by using an etching selectivity with the insulating layer. 제 1 항에 있어서,The method of claim 1, 상기 희생막은 상기 절연막이 산화막인 경우 질화막, 실리콘리치산화질화막 및 실리콘산화질화막 중 어느 하나로 형성하는 반도체 소자 제조방법.And the sacrificial layer is formed of any one of a nitride film, a silicon rich oxynitride film, and a silicon oxynitride film when the insulating film is an oxide film. 제 1 항에 있어서,The method of claim 1, 상기 희생막은 상기 절연막이 저유전상수 값을 갖는 무기물인 경우 유기물 폴리머로 형성하는 반도체 소자 제조방법.And the sacrificial layer is formed of an organic polymer when the insulating layer is an inorganic material having a low dielectric constant value. 제 1 항 내지 제 4 항 중 어느 하나의 항에 있어서,The method according to any one of claims 1 to 4, 상기 희생막은 전면식각공정을 실시하여 제거하는 반도체 소자 제조방법.The sacrificial layer is removed by performing a front surface etching process. 제 1 항에 있어서, The method of claim 1, 상기 금속배선의 증착은 물리적 화학기상 증착 방식을 통해 이루어지는 반도체 소자 제조방법.The deposition of the metal wiring is a semiconductor device manufacturing method made through a physical chemical vapor deposition method. 제 1 항에 있어서, The method of claim 1, 상기 일정 깊이는 상기 희생막 상에 상기 플러그용 도전층의 찌꺼기가 잔류되지 않을 깊이로 하는 반도체 소자 제조방법.The predetermined depth is a semiconductor device manufacturing method so that the residue of the plug conductive layer on the sacrificial film does not remain.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100846388B1 (en) * 2007-07-11 2008-07-15 주식회사 하이닉스반도체 Method for forming multilayer wiring of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100846388B1 (en) * 2007-07-11 2008-07-15 주식회사 하이닉스반도체 Method for forming multilayer wiring of semiconductor device

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