KR20060130322A - Field effect transistor having vertical channel and manufacturing method thereof - Google Patents

Abstract

The present invention provides a field effect transistor having a vertical channel capable of securing a channel area while preventing short channel effects due to the size reduction of the transistor, and a method of manufacturing the same. On the tunnel oxide film so as to overlap with the trench in a direction intersecting the fin, and a fin formed with a trench in a portion of the active region which protrudes in a vertical direction and vertically protrudes. A field effect transistor having a vertical channel including a gate electrode formed and an isolation layer formed in a field region of the substrate except for the active region is provided.

Description

Field effect transistor having vertical channel and manufacturing method therefor {FIELD EFFECT TRANSISTOR HAVING VERTICAL CHANNEL AND METHOD THEREOF}

1 is a cross-sectional view schematically showing a field effect transistor having a general fin structure.

2 is a cross-sectional view schematically showing a typical trench type transistor.

3 is a perspective view illustrating a vertical channel type field effect transistor according to a preferred embodiment of the present invention.

4A and 4B are enlarged perspective views illustrating a portion 'A' shown in FIG. 3 to explain a process for forming a 'U' fin according to a preferred embodiment of the present invention.

5A and 5B are TEM photographs showing field effect transistors according to a preferred embodiment of the present invention.

6 is a plan view illustrating a method of manufacturing a field effect transistor according to a preferred embodiment of the present invention.

(A) of FIG. 7 thru | or 10 is process sectional drawing along the AA 'cut line shown in FIG.

(B) of FIG. 7 to FIG. 10 is a cross sectional view taken along the line BB ′ shown in FIG. 6.

<Explanation of symbols for the main parts of the drawings>

100: substrate

110: active area

111: pad oxide film

112: pad nitride film

113: device isolation layer

114: pin mask

116: recess mask

118: 'U' pin

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a field effect transistor having a vertical channel and a method of manufacturing the same.

In general, a transistor having a horizontal channel widely applied to a transistor causes various problems as the design rule is reduced, thereby limiting the reduction of the transistor. The biggest problems of the reduced horizontal channel transistors include short channel effects and drain induced barrier lower (DIBL) effects caused by shorter channel lengths. In conventional transistors, when the channel length is reduced to 50 nm or less, the dispersion of device characteristics is increased by process variables, and when the channel length is 30 nm or less, the short channel effect and the DIBL effect become severe and it is known that the transistor is difficult to operate normally.

In order to overcome the problems of horizontal channel transistors, double gate transistors have been proposed. The double gate transistor has a channel having a thickness of 30 nm or less, and a structure surrounding the channel or having gates disposed on both sides of the channel.

In the above-described horizontal channel transistor, since the gate electrode is formed only on the upper portion of the horizontal channel, an electric field is vertically asymmetrically applied to the channel, and thus there is a lot of difficulty in effectively controlling the on / off operation of the transistor by the gate electrode. As a result, the smaller the channel size, the greater the influence of the short channel effect. In contrast, in the double gate transistor having the vertical channel, since gate electrodes are formed on both sides of the thin channel, all regions of the channel are affected by the gate electrode. Therefore, since the charge flow between the source and the drain can be suppressed when the transistor is off, power consumption can be reduced, and the on / off operation of the transistor can be effectively controlled.

One transistor with a vertical channel is a Fin-FET device. A typical Fin-FET device is shown in FIG. As shown in FIG. 1, the Fin-FET device has a structure in which upper portions of the substrates between the device isolation layers 3 are formed in the form of fins 2, and both sides of the fins 2 function as channels. This can solve the short channel effect problem by increasing the channel area. However, such a structure can reduce the body effect, but there is a limit to increasing the channel length. On the other hand, another of the transistors having a vertical channel is a trench type (or recess type) transistor shown in FIG. Unlike fin-FET devices, trench-type transistors have a transistor structure in which a threshold voltage is determined regardless of the gate length. However, the threshold voltage is lowered or the short channel effect cannot be solved freely as a trench transistor.

Meanwhile, reference numeral '4' illustrated in FIG. 1 is a gate electrode, reference numeral '11' illustrated in FIG. 2 is a substrate, '12' is a trench, '13' is an isolation layer, and '14' is a gate electrode. .

Accordingly, the present invention has been made to solve the above problems of the prior art, and a field effect transistor having a vertical channel capable of securing a channel area while preventing a short channel effect due to the size reduction of the transistor and a method of manufacturing the same. The purpose is to provide.

According to an aspect of the present invention, an active region of a substrate protrudes vertically, and a fin is formed in a portion of the active region that protrudes vertically, and a fin is formed along a step. A field effect transistor having a vertical channel including a formed tunnel oxide film, a gate electrode formed on the tunnel oxide film so as to overlap the trench in a direction crossing the fin, and an isolation layer formed in a field region of the substrate except the active region; to provide.

According to another aspect of the present invention, there is provided a substrate on which an isolation layer is formed, and performing a first etching process using a fin mask to recess the isolation layer to activate the substrate. Forming a fin in which a region protrudes, forming a trench in a portion of the fin by performing a second etching process using a recess mask, forming a tunnel oxide film along a step of the trench, and A method of manufacturing a field effect transistor having a vertical channel includes forming a gate electrode on the tunnel oxide layer so as to overlap the trench in a direction crossing a fin.

According to another aspect of the present invention, there is provided a substrate in which an isolation layer is formed, and a first etching process using a recess mask is performed to form a trench in a portion of the active region of the substrate. And forming a fin to protrude the active region in which the trench is formed by recessing the device isolation layer by performing a second etching process using a fin mask, and forming a tunnel oxide layer along the step difference of the trench. And forming a gate electrode on the tunnel oxide layer so as to overlap the trench in a direction crossing the fins.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3, 4A, and 4B are perspective views and cross-sectional views illustrating a field effect transistor having a vertical channel according to a preferred embodiment of the present invention. 4A and 4B are cross-sectional views illustrating an enlarged view of a portion 'A' illustrated in FIG. 3.

As shown in FIGS. 3, 4A, and 4B, in the field effect transistor according to the preferred embodiment of the present invention, the device isolation layer 113 formed in the field region is etched to form a fin in a constant shape. An etching process using a recess mask is performed to etch a portion of the active region 110 in which the fin is formed to form a 'U'-shaped fin 118.

As described above, the field effect transistor according to the preferred embodiment of the present invention forms a 'U'-shaped fin 118 structure in parallel with the conventional fin process and the recess process. That is, after the fin is formed, the silicon substrate under the gate is recessed to form a 'U'-shaped fin 118 structure, so that the fin 118 formed through the recess process is added to the channel length obtained through the conventional fin structure. The channel length can be secured to prevent short channel effects and to secure the channel area.

5A and 5B show the 'U'-shaped fin structure in which the fin structure and the recess structure are actually parallel, and then the' X 'axis direction (the direction parallel to the gate electrode) and the' Y 'axis direction (the intersection with the gate electrode), respectively. TEM (Transmission Electron Microscope) photograph taken in

Meanwhile, reference numeral '111' illustrated in FIG. 5B is a pad oxide film, and '112' is a pad nitride film.

Hereinafter, a method of manufacturing a field effect transistor according to a preferred embodiment of the present invention will be described.

6 is a plan view illustrating a field effect transistor according to a preferred embodiment of the present invention, and FIGS. 7 to 10 are process cross-sectional views illustrating a method of manufacturing a field effect transistor. Here, (a) is a cross-sectional view taken along the line AA ′ of FIG. 6, and (b) is a cross-sectional view taken along the line B-B ′ of FIG. 6.

6 and 7, the pad oxide layer 111 and the pad nitride layer 112 are sequentially deposited on the semiconductor substrate 100, and then a shallow trench isolation (STI) process is performed to the field region. The device isolation layer 113 is formed. Thus, the field region and the active region 110 are defined.

For example, the STI process proceeds as follows. First, a photoresist pattern (not shown) is formed on the pad nitride layer 112, and an etching process using the photoresist pattern as an etching mask is performed to etch the pad nitride layer 112, the pad oxide layer 111, and the substrate 100. do. Then, an HDP (High Density Plasma) oxide film is deposited so as to fill trenches (not shown) formed in the substrate 100 by an etching process, and then a CMP (Chemical Mechanical Polishing) process is performed to isolate the device inside the trench. The separator 113 is formed.

Subsequently, as shown in FIGS. 6 and 8, after forming the photoresist pattern 114 (hereinafter referred to as a fin mask) to expose the region where the device isolation layer 113 is formed except the active region 110, the fin is formed. An etching process 115 using the mask 114 is performed to recess the device isolation layer 113 to a predetermined depth to form a fin structure from which the active region 110 is derived. In this case, the fin mask 114 preferably controls the critical dimension so that the critical dimension (CD) of the unidirectional width of the fin formed after the etching process 115 is 80 nm or less, and the device isolation layer 113 is The etching process 115 is controlled to be recessed to a depth of at least 500 mm 3.

Meanwhile, the fin forming process may apply a hard mask scheme. In this case, a hard mask (not shown) made of a polysilicon film, a nitride film, an oxide film, an amorphous carbon film, or SiLK (product name) is deposited on the pad nitride film 112, and then the fin mask 114 is formed thereon. ). Then, an etching process using the fin mask 114 is performed first to etch the hard mask, and then an etching process using the etched hard mask as an etching mask is performed to recess the device isolation layer 113 to form a fin structure. do.

6 and 9, a strip process is performed to remove the fin mask 114 (see FIG. 8).

Subsequently, after forming a photoresist pattern 116 (hereinafter referred to as a recess mask) in which a portion of the active region 110 protruding into the fin structure is formed, an etching process 117 using the recess mask 116 is performed. In some embodiments, a portion of the active region 110 is recessed to form a 'U'-shaped fin 118 having a trench structure. At this time, the recess mask 116 has a threshold smaller than the threshold of the fin mask 114, for example, at least 10 nm or smaller, and preferably has a threshold of 70 nm. In addition, the depth of the active region 110 recessed through the etching process 117 is shallower than the depth of the device isolation layer 113 recessed through the etching process 115 in FIG. 8, preferably, the device isolation layer. It is formed to be at least 50 kPa shallower than the recessed depth of 113.

Meanwhile, a dry etching process may be performed to compensate for the damaged active region 110 during the etching process 117.

6 and 10, a strip process is performed to remove the recess mask 116.

Subsequently, the pad nitride film 112 and the pad oxide film 111 are etched and removed. As a result, the U-shaped pin 118 is formed as shown in the same figure. Meanwhile, in FIG. 10, '118a' and 118b 'do not deposit separate layers, but indicate channel regions for better understanding. That is, both the inner wall and the bottom of the 'U'-shaped fin 118 correspond to the channel region. As a result, the short channel effect can be prevented by increasing the channel length of the fin 118 compared to the conventional fin structure.

Subsequently, although not shown, a tunnel oxide film is formed along a step of the upper portion of the entire structure including the fin 118, and then a gate electrode 200 is formed on the tunnel oxide film so as to intersect the fin 118.

Meanwhile, in the above-described preferred embodiment of the present invention, the pin etching process is first performed using the pin mask, and then the recess etching process is performed using the recess mask, which is an example of the recess using the recess mask. The etching process may be performed first, and then a fin etching process may be performed using a pin mask to form a 'U'-shaped fin. In this case, the process conditions including the critical dimension of the mask are the same as described above.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a channel is formed by performing a fin etching process to form an active region in a fin structure to secure a channel area, and then performing a recess etching process inside the fin to form a 'U' fin. The length can be secured to prevent short channel effects.

Claims (15)

A fin in which an active region of the substrate protrudes vertically and a trench is formed in a portion of the active region which protrudes vertically; A tunnel oxide film formed along a step of the fin; A gate electrode formed on the tunnel oxide layer to overlap the trench in a direction crossing the fins; And An isolation layer formed in the field region of the substrate except for the active region Field effect transistor having a vertical channel comprising a. The method of claim 1, And the trench has a vertical channel formed to be shallower than the height at which the pin protrudes. The method according to claim 1 or 2, And the inner wall portion and the bottom portion of the trench have vertical channels functioning as channel regions. Providing a substrate on which an isolation layer is formed; Performing a first etching process using a fin mask to recess the device isolation layer to form a fin protruding from the active region of the substrate; Forming a trench in a portion of the fin by performing a second etching process using a recess mask; Forming a tunnel oxide film along the steps of the trench; And Forming a gate electrode on the tunnel oxide layer to overlap the trench in a direction crossing the fins Method of manufacturing a field effect transistor having a vertical channel comprising a. Providing a substrate on which an isolation layer is formed; Forming a trench in a portion of the active region of the substrate by performing a first etching process using a recess mask; Performing a second etching process using a fin mask to recess the device isolation layer to form fins protruding the active region in which the trench is formed; Forming a tunnel oxide film along the steps of the trench; And Forming a gate electrode on the tunnel oxide layer to overlap the trench in a direction crossing the fins Method of manufacturing a field effect transistor having a vertical channel comprising a. The method according to claim 4 or 5, And the trench has a vertical channel formed so that the active region is shallower than the protruding height. The method according to claim 4 or 5, And the pin mask has a vertical channel having a larger critical dimension than the recess mask. The method of claim 7, wherein And wherein the recess mask has a vertical channel formed to have a threshold dimension that is at least 10 nm smaller than the fin mask. The method of claim 8, The recess mask is a method of manufacturing a field effect transistor having a vertical channel formed to have a threshold dimension of 40nm ~ 70nm. The method according to claim 4 or 5, The unidirectional width of the fin has a vertical channel having a 50nm ~ 80nm method of manufacturing a field effect transistor. The method according to claim 4 or 5, And said device isolation layer has a vertical channel recessed to a depth of at least 500 microns. The method of claim 11, And the trench has a vertical channel formed at least about 50 microns shallower than the recessed depth of the device isolation layer. The method according to claim 4 or 5, And performing a dry etching process on the substrate after the second etching process, thereby compensating for the damaged portion during the second etching process. The method of claim 4 or 5, wherein forming the fins, Depositing a hard mask on the substrate; Etching the hard mask using the pin mask; Removing the pin mask; And Performing an etching process using the etched hard mask Method of manufacturing a field effect transistor having a vertical channel comprising a. The method of claim 14, The hard mask is a method of manufacturing a field effect transistor having a vertical channel formed of any one of a polysilicon film, a nitride film, an oxide film, an amorphous carbon film and SiLK.

Images