KR20060077196A - Filter module - Google Patents

Abstract

The present invention relates to a filter module for image data, and more particularly, a 1D-DWT (1-Dimension Discrete Wavelet Transform) filter that performs a role of filtering input images by subbands in JPEG2000, the next-generation still image compression standard. It is about a module. There are two types of DWT filtering used in JPEG2000, a structure based on a convolution operation and a structure based on a lifting. The present invention is to improve the performance of a structure based on a convolution operation.

The filter module of the present invention comprises: an input register for sequentially latching image data by one pixel; A multiplier comprising a plurality of multipliers for multiplying a value stored in the input register by a predetermined filter coefficient; A coefficient selector comprising a plurality of coefficient selectors for selecting filter coefficients to be applied to each multiplier; A multiplication register unit comprising a plurality of multiplication registers for storing multiplication operation values of the multipliers; And an add-shift register unit for performing an addition operation and a shift on each stored value of each multiply register in a predetermined order to generate a predetermined convolutionally operated data stream.

DWT, JPEG2000, Convolution, Filter Module, Image Compression

Description

Filter module {FILTER MODULE}             

1 is a block diagram showing a 1D-DWT filter module according to the prior art,

Figure 2 is a block diagram showing one embodiment of a 1D-DWT filter module according to the present invention.

* Explanation of symbols for main parts of the drawings

110: input register 120: multiplication unit

140: coefficient selection unit 160: multiplication register

180: add-shift register section

The present invention relates to a filter module for image data, and more particularly, a 1D-DWT (1-Dimension Discrete Wavelet Transform) filter that performs a role of filtering input images by subbands in JPEG2000, the next-generation still image compression standard. It is about a module.

JPEG2000 supports better compression and improved encoding technology than MPEG. It uses DWT to provide high image compression and high picture quality with quantization and entropy coding. In the case of MPEG, the resolution is fixed so that the image is damaged when the image is scaled, while the image using DWT does not damage the image even when the image is enlarged or reduced. A wide range of applications is possible, and is particularly effective for compressing and restoring still images in digital cameras.

1 is a block diagram showing a DWT filter module according to the prior art. The illustrated DWT filter module comprises: an input register section consisting of nine registers in which input image data is shift buffered; An adder for summing registers of symmetric positions among the nine registers; An add register unit for storing an add operation result of the add unit; A multiplier comprising a plurality of multipliers for multiplying a value stored in each add register by a predetermined coefficient; A coefficient selector comprising a plurality of coefficient selectors for selecting the predetermined coefficients to be applied to each multiplier; A multiplication register unit for storing the operation result of the multiplication unit; And an output adder for adding a value stored in each component register of the multiplication register unit.

The structure is a so-called direct structure, in which the input image data is stored in nine shift registers, and the data calculated by the multiplication operation of the data stored in this register and the filter coefficient selected by the coefficient selector are added together. Get the filtered pixels.

Direct 1D-DWT structure as shown has a relatively large number of registers, there is a problem that the operation speed is slow due to the inefficient structure.

The present invention has been made to solve the above problems, and an object thereof is to provide a DWT filter module with a simpler structure and more efficient.

It is another object of the present invention to provide a DWT filter module having a faster operation speed.

The filter module of the present invention for achieving the above object has a structure inverting the direct 1D-DWT structure of the prior art. That is, a multiplication operation is performed directly with the filter coefficients without directly passing the input data through the shift register, and after the multiplication operation is completed, the addition operation according to the shift register is performed. Such a structure has no change in the number of multipliers and adders compared to the conventional direct 1D-DWT structure, but the number of registers is reduced and the inefficiency of the addition operation can be improved.

There are two types of DWT filtering used in JPEG2000, a structure based on a convolution operation and a structure based on a lifting. The present invention is for improving the performance of a structure based on a convolution operation. The convolution operation to be implemented by the present invention is shown in Equation 1 below.

0 <n≤N

(x [n]: 1-D input image sequence,

  y [n]: Filtered sequence for each subband of 1-D

  N: total number of image pixels

  y [2n-1]: Low pass filtered subband

  y [2n]: High pass filtered subband

  h [k]: Low pass filter coefficients

  g [k]: high pass filter coefficients

  Nh, Ph: maximum k value and minimum k value of the low pass filter coefficients

  Ng, Pg: maximum k value and minimum k value of high pass filter coefficient)

In the above formula, h [k] and g [k] are representative Daubechies 9/7 filter coefficients and specific values are shown in Table 1 below.

k Low-pass Filter High-pass Filter 0 h0 0.6029490182363579 g0 1.115087052456994 ± 1 h1 0.2668641184428723 g1 -0.5912717631142470 ± 2 h2 -0.07822326652898785 g2 -0.05754352622849957 ± 3 h3 -0.01686411844287495 g3 0.09127176311424948 ± 4 h4 0.02674875741080976

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

(Example)

The filter module of the present embodiment as shown in FIG. 2 includes an input register 110 for sequentially latching image data by one pixel; A multiplier comprising a plurality of multipliers for multiplying a value stored in the input register 110 by a predetermined filter coefficient; A coefficient selector (140) comprising a plurality of coefficient selectors for selecting filter coefficients to be applied to each multiplier; A multiplication register unit (160) comprising a plurality of multiply registers for storing multiply operation values of the multipliers; And an add-shift register unit 180 for performing an addition operation and a shift on each stored value of each multiply register in a predetermined order to generate a predetermined convolutional data stream.

The illustrated input register 110 is for latching each pixel value of the image data input in the sequence form by the time necessary for the operation of the multiplier. When the operation of inputting and multiplying image data is precisely synchronized, there is no need for a separate latch device, or there is a separate latch at the output terminal of the device output to the filter module of the present embodiment, or a separate latch is provided at the multiplier. May not be provided with the input register.

The illustrated multiplier 120 is composed of five multipliers T0 to T4. Each multiplier T0 to T4 stores the latch values of the input register 110 and the filter coefficients determined by the coefficient selectors X0 to X4. Multiply and store the result in each corresponding multiplication register (M1 to M5). In the present embodiment, each multiplier T0 to T4 may be implemented as a four-stage pipelined booth multiplier.

Table 1 shows high filtering coefficients and low filtering coefficients to be applied in the multiplier. The coefficient set in Table 1 applies when the low pass filtering coefficient is used up to the fourth harmonic term and the high pass filtering coefficient is used up to the third harmonic term.

The illustrated coefficient selector 140 is composed of five coefficient selectors X0 to X4, and the first coefficient selector X0 includes a high pass filtering coefficient g0 and a low pass filtering coefficient h0 for the 0th harmonic term. The second coefficient selector (X1) selects one of the high pass filtering coefficient (g1) and the low pass filtering coefficient (h1) for the first harmonic term, and the third coefficient selector (X2) selects the second harmonic Select one of the high pass filtering coefficient (g2) and the low pass filtering coefficient (h2) for the term, and the fourth coefficient selector (X3) selects the high pass filtering coefficient (g3) and the low pass filtering coefficient (for the third harmonic term). h3), the fifth coefficient selector X4 selects one of the coefficient of zero and the low pass filtering coefficient h4 for the fourth harmonic term.

As shown, the coefficient selector 140 once has a low pass filtering coefficient h0 for the zeroth harmonic term, a high pass filtering coefficient g1 for the first harmonic term, and a low pass for the second harmonic term. Select the filtering coefficient (h2), the high pass filtering coefficient for the third harmonic term (g3), and the low pass filtering coefficient for the fourth harmonic term (h4), the next time the high pass filtering coefficient for the zeroth harmonic term ( g0), the low pass filtering coefficient for the first harmonic term (h1), the high pass filtering coefficient for the second harmonic term (g2), the low pass filtering coefficient for the third harmonic term (h3), and the coefficient of zero. Repeat the process.

The illustrated add-shift register unit 180 includes nine addition-shift latches RA0 to RA8 for latching a value obtained by adding a predetermined addition value to the previous stored value. The stored value of the last stage multiplication register M4 is input to the first stage latch latch RA0 and the last stage of the add-shift latch RA8, and the stored value of the fourth stage multiplication register M3 is the second stage add-shift. The stored values of the third-stage multiply register (M2) are input to the latch (RA1) and the eighth-stage add-shift latch (RA7), and the third-stage add-shift latch (RA2) and the seventh-stage add-shift latch (RA6). The stored value of the second-stage multiply register (M1) is input to the fourth-stage add-shift latch (RA3) and the sixth-stage add-shift latch (RA5), and the stored value of the first-stage multiply register (M0) is fifth. It is input to the stage add-shift latch RA4.

Hereinafter, the conversion process of the image data stream by the filter module of the present embodiment will be described.

Each pixel data via the input register 110 is weighted by applying predetermined filtering coefficients by five multipliers T0 to T4, respectively, and then stored in five multiplication registers M0 to M4, respectively. . The output values of the multiplication registers M0 to M4 are summed in the order determined by the add-shift register unit 180, and finally, image data subjected to DWT filtering is stored in the R9 register.

The input register 110 latches each pixel data constituting the image data stream one by one according to a clock, and transmits them to five multipliers T0 to T4. On the other hand, each of the add-shift latches RA0 to RA8 constituting the add-shift register unit 180 adds the corresponding multiplication register stored value to the previous shift latch in accordance with a clock, so that the final add register R9 The sum of nine pixel values whose corresponding filtering coefficient is weighted is stored. The coefficient selectors X0 to X4 initially select the above coefficients shown in the figure, and then operate in such a manner that the below coefficients shown in the figure are selected. Therefore, in the last stage addition register R9, h4 and h3 at odd numbered clocks. , a summation is generated for the nine pixel values multiplied by the filtering coefficients in the order of h2, h1, h0, h1, h2, h3, and h4, and g3, g2, g1, g0, g1, g2, And a summation value for the seven pixel values multiplied by the filtering coefficients in the order of g3.

For example, assuming that input pixel data comes in as x [1], x [2], x [3], ..., the result of the calculation of x [1] · h4 in the first clock pulse period results in the M4 register. Passed through is stored in the R1 register. In the second clock pulse period, x [2] · h3 is stored in the R2 register by performing an addition operation with the R1 register through the M3 register. Repeating the above process, DWT filtered output image data y [1] and y [2] are expressed as in Equation 2 below.

y [1] =

(x [1] .h4) + (x [2] .h3) + (x [3] .h2) + (x [4] .h1) + (x [5] .h0) +

(x [6] h1) + (x [7] h2) + (x [8] h3) + (x [9] h4)

y [2] =

(x [2] .0) + (x [3] .g3) + (x [4] .g2) + (x [5] .g1) + (x [6] .g0) +

(x [7] .g1) + (x [8] .g2) + (x [9] .g3) + (x [10] .0)

As a result, y {2n-1] is divided into a low pass region by a convolution operation with the low pass filtering coefficient, and y [2n] is divided into a high pass region by a convolution operation with the high pass filtering coefficient.

On the other hand, the multiplication operation of the filtering coefficient and the input data uses the point that ± k values are symmetrical with respect to the harmonic coefficient 0, and the width of the filtering operation of 9 pixels is converted into 5 multipliers. Can be implemented to perform.

On the other hand, a carry bit is generated every time the addition operation is performed. In the above structure, the bit depth is limited to 32 bits to prevent the bit depth from increasing each time through the R1 to R9 shift latches. Can be implemented.                     

Although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto, and the technical spirit of the present invention and the claims to be described below by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents.

For example, in the above description, the name of the present invention is defined as a filter module, and each component is described based on its function. However, adders, registers, and multipliers constituting each component are well-known by hardware and It can be implemented in software. Therefore, the filter module of the present invention can also be a general-purpose computer equipment installed with the software for performing the above functions, each of the components can be a board-type equipment consisting of independent elements, each of the components mounted on a single chip It may be a semiconductor element.

By implementing the filter module according to the present invention, there is an effect that the addition operation can be performed more efficiently than the prior art. In addition, since the number of registers for storing the intermediate calculation value can be reduced, when implementing the filter module in hardware, there is an effect of reducing the area of implementation.

Since the above effects can be usefully used for convolution-based DWT filtering, there is an effect of improving the performance of the device or device for image compression.

Claims (8)

An input register for sequentially latching image data by one pixel; A multiplier comprising a plurality of multipliers for multiplying a value stored in the input register by a predetermined filter coefficient; A coefficient selector comprising a plurality of coefficient selectors for selecting filter coefficients to be applied to each multiplier; A multiplication register unit comprising a plurality of multiplication registers for storing multiplication operation values of the multipliers; An add-shift register section for performing an addition operation and a shift of each stored value of each multiplication register in a predetermined order to generate a data stream to which a predetermined convolution operation is applied; Filter module comprising a. The method of claim 1, The output of the filter module, the odd-numbered output is a low pass filtering, the even output is a high pass filtering, The highest harmonic term applied to the low pass filtering or the high pass filtering is ± k (k is an integer). The method of claim 2, wherein the multiplication unit, And a multiplier k + 1 for multiplying the latch value of the input register by a predetermined filter coefficient and outputting the result. The method of claim 1, wherein the multiplication unit, Filter module, a four-stage pipelined booth multiplier multiplier. The method of claim 2, wherein the coefficient selector comprises k + 1 coefficient selectors, The first coefficient selector selects one of the high pass filtering coefficient and the low pass filtering coefficient for the zeroth harmonic term, The second coefficient selector selects one of the high pass filtering coefficient and the low pass filtering coefficient for the first harmonic term, The third coefficient selector implements a scheme of selecting one of the high pass filtering coefficient and the low pass filtering coefficient for the second harmonic term up to the kth harmonic term. A filter module in which a non-existent filtering coefficient is applied as a coefficient of zero if only one of a high pass filtering coefficient or a low filter filtering coefficient for a particular order harmonic term is present. The method of claim 2, wherein the coefficient selector, Once, select low pass filtering coefficients for even harmonic terms and high pass filtering coefficients for odd harmonic terms, Next, the filter module repeats the process of selecting the high pass filtering coefficients for the even harmonic terms and the low pass filtering coefficients for the odd harmonic terms. The method of claim 3, wherein the add-shift register unit, And a 2k + 1 add-shift latch for latching a value obtained by adding a predetermined addition value to the previous stored value. The method of claim 7, wherein the add-shift register unit, The stored value of the last stage (k + 1) stage multiplication register is input to the first stage addition-shift latch and the last stage (2k + 1 stage) addition-shift latch. The stored value of the kth multiplication register is input to the 2nd stage add-shift latch and the 2nd stage add-shift latch. The stored value of the k-1 multiplication register is inputted to the 3rd-stage add-shift latch and the 2k-1st-stage add-shift latch. The filter module of the first stage multiplication register is input to the add-shift latch of the k + 1 stage.

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