KR20060076662A - Charge Trap Insulator Memory Device - Google Patents

Abstract

The charge trap insulator memory device of the present invention improves retention characteristics in a nano scale charge trap insulator memory device, and a plurality of charge trap insulator cell arrays are stacked in a vertical direction by using a plurality of cell insulating layers. To increase the cell integrated capacity. To this end, a plurality of serially connected memories in which data applied through the bit line is stored in the charge trap insulator or data stored in the charge trap insulator is output to the bit line according to the potential applied to the upper word line and the lower word line. Cell; A first switching element for selectively connecting a bit line and the plurality of memory cells according to a state of a first selection signal; And a second switching element for selectively connecting the sensing line and the plurality of memory cells according to the state of the second selection signal, wherein the P-type float channel varies in resistance according to the polarity of the charge trap insulator; And a P-type drain region and a P-type source region formed on both sides of the P-type float channel.

Description

Charge trap insulator memory device

1 is a cross-sectional view of a memory cell of a charge trap insulator memory device according to the prior art.

2A is a cross-sectional view of a unit memory cell cut in a direction parallel to a word line.

2B is a cross-sectional view of the unit memory cell cut in a direction perpendicular to the word line.

FIG. 2C is a circuit diagram in which a unit memory cell illustrated in FIG. 2B is defined in a circuit.

3A and 3B are diagrams for explaining an operation of writing and reading the high level data " 1 " of the charge trap insulator memory device according to the present invention.

4 is a detailed conceptual diagram illustrating a read operation of data "1" shown in FIG. 3B.

5A and 5B are diagrams for describing an operation of writing and reading the low level data “0” of the charge trap insulator memory device according to the present invention.

FIG. 6 is a detailed conceptual diagram illustrating a read operation of the low level data “0” shown in FIG. 5B.

7 is a diagram illustrating a unit memory cell array of a charge trap insulator memory device according to the present invention.

FIG. 8 is a conceptual diagram illustrating a read operation of row data “0” in the unit memory cell array illustrated in FIG. 7.

FIG. 9 is a conceptual diagram for describing a read operation of row data “0” in the unit memory cell array illustrated in FIG. 7.

10A and 10B are cross-sectional views illustrating a connection relationship between the memory cells Q1 and Qm and the switching elements N1 and N2 shown in FIG. 7.

11 is a circuit diagram illustrating a memory cell array structure of the charge trap insulator memory device according to the present invention.

12 is a view for explaining the write operation of the charge trap insulator memory device according to the present invention.

13 is a timing diagram illustrating a data “1” write operation of the charge trap insulator memory device according to the present invention.

14 is a timing diagram illustrating a data " 1 " holding or a data " 0 " write operation of the charge trap insulator memory device according to the present invention.

15 is a timing diagram illustrating an operation of sensing data stored in a memory cell of the charge trap insulator memory device according to the present invention.

The present invention relates to a charge trap insulator memory device, and more particularly, to improve retention characteristics in a nano scale charge trap insulator memory device, and to use a plurality of cell insulating layers. A technology for increasing cell integration capacity by stacking a plurality of charge trap insulator cell arrays in a vertical direction.

1 is a cross-sectional view of a memory cell of a charge trap insulator memory device according to the prior art.

The memory cell of the charge trap insulator memory device includes an N-type drain region 4 and an N-type source region 6 formed on the P-type substrate 2, and a first insulating layer sequentially formed on the channel region. (8), charge trap insulator 10, second insulating layer 12, and word line 14;

In the memory cell of the conventional charge trap insulator memory device having such a configuration, the channel resistance of the memory cell is changed by the state of the charge (Carge) stored in the charge trap insulator 10.

In other words, if electrons are stored in the charge trap insulator 10, positive channel charges are induced in the channel, and thus the memory cell is in a high resistance channel state and is turned off.

On the other hand, if holes are stored in the charge trap insulator 10, negative (-) channel charges are induced in the channel, and thus the memory cell is in a low resistance channel state.

In this manner, the charge trap insulator can be selected and written to operate as a nonvolatile memory cell.

However, the memory cell of the above-described conventional charge trap insulator memory device has a problem in that it is difficult to implement a normal operation due to retention characteristics, etc., when the cell size decreases.

In particular, the memory cells of the nano-scale level charge trap insulator structure have a weak holding property even at low voltage stress, and thus, a method of applying an arbitrary voltage to the word line at the time of read cannot be applied. have.

An object of the present invention to solve the above problems is to enable the memory cell of the nanoscale level charge trap insulator structure to operate at a low voltage.

Another object of the present invention for solving the above problems is to increase the cell integration capacity by stacking a plurality of charge trap insulator cell array in a vertical direction using a plurality of cell insulating layers.

In the charge trap insulator memory device of the present invention for achieving the above object, the data applied through the bit line is stored in the charge trap insulator or stored in the charge trap insulator according to the potential applied to the upper word line and the lower word line. A plurality of serially connected memory cells in which data is output to the bit line; A first switching element for selectively connecting a bit line and the plurality of memory cells according to a state of a first selection signal; And a second switching element configured to selectively connect a sensing line and the plurality of memory cells according to a state of a second selection signal, the plurality of memory cells comprising: a first insulating layer formed on the lower word line; A P-type flow channel formed on the first insulating layer and having a resistance changed according to the polarity of the charge trap insulator; A P-type drain region and a P-type source region formed at both sides of the P-type float channel; A second insulating layer formed on the P-type float channel; The charge trap insulator formed on the second insulating layer; And a third insulating layer formed above the charge trap insulator and below the upper word line.

In addition, the charge trap insulator memory device of the present invention for achieving the above object is arranged in the row direction, a plurality of upper word lines and a plurality of lower word lines parallel to each other; A plurality of bit lines arranged in a column direction; A plurality of sensing lines arranged in a vertical direction with the plurality of bit lines; A plurality of memory cell arrays disposed in an area where the plurality of upper word lines and the plurality of lower word lines and the plurality of bit lines cross each other; And a plurality of sense amplifiers for sensing and amplifying data carried on the bit lines in a one-to-one correspondence with the plurality of bit lines, wherein each of the plurality of memory cell arrays comprises an upper word line and a lower word; A plurality of serially connected memory cells in which data applied through a bit line is stored in a charge trap insulator or data stored in the charge trap insulator is output to the bit line according to a potential applied to a line; A first switching element for selectively connecting a bit line and the plurality of memory cells according to a state of a first selection signal; And a second switching element configured to selectively connect a sensing line and the plurality of memory cells according to a state of a second selection signal, the plurality of memory cells comprising: a first insulating layer formed on the lower word line; A P-type float channel formed on the first insulating layer and having a resistance changed according to a polarity of the charge trap insulator; A P-type drain region and a P-type source region formed at both sides of the P-type float channel; A second insulating layer formed on the P-type float channel; The charge trap insulator formed on the second insulating layer; And a third insulating layer formed above the charge trap insulator and below the upper word line.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A is a cross-sectional view of a unit memory cell cut in a direction parallel to a word line.

First, a bottom word line 16 is formed on the bottom layer, and an upper word line 18 is formed on the top layer. The lower word line 16 and the upper word line are arranged in parallel with each other.

The first insulating layer 20, the float channel 22, the second insulating layer 24, the charge trap insulator 26, and the third insulating layer 28 are sequentially formed on the lower word line 10. do. Here, the float channel 22 is formed using a P-type semiconductor.

2B is a cross-sectional view of the unit memory cell cut in a direction perpendicular to the word line.

First, a bottom word line 16 is formed on the bottom layer, and an upper word line 18 is formed on the top layer. The lower word line 16 and the upper word line are arranged in parallel with each other.

The first insulating layer 20, the float channel 22, the second insulating layer 24, the charge trap insulator 26, and the third insulating layer 28 are sequentially formed on the lower word line 10. do. Here, the P-type drain 30 and the P-type source 32 are formed on both sides of the float channel 22.

In addition, the float channel 22, the P-type drain 30, and the P-type source 32 may be in the form of carbon nanotubes, or may include silicon, germanium, and organic semiconductors. And other materials.

In the unit memory cell of the charge trap insulator memory device according to the present invention formed as described above, the channel resistance of the memory cell changes according to the state of charge stored in the charge trap insulator 26.

That is, if electrons are stored in the charge trap insulator 26, positive channel charges are induced in the channel of the memory cell, and thus the memory cell is turned off as a high resistance channel state.

On the other hand, if holes are stored in the charge trap insulator 26, negative charges are induced in the channel, and thus the memory cell is turned on in the low resistance channel state.

In this way, the charge trap insulator 26 can be selected and written to operate as a nonvolatile memory cell.

The unit memory cell of the present invention having such a configuration is intended to be represented as a symbol shown in FIG. 2C.

3A and 3B are diagrams for explaining an operation of writing and reading the high level data " 1 " of the charge trap insulator memory device according to the present invention.

First, FIG. 3A is a conceptual diagram illustrating a write operation of high level data "1".

The ground voltage GND is applied to the lower word line 16, and a negative voltage −V is applied to the upper word line 18. At this time, the drain region 30 and the source region 32 are in a ground voltage GND state.

In this case, a voltage is applied between the charge trap insulator 26 and the channel region 22 by the voltage distribution of the capacitor between the first insulating layer 20, the second insulating layer 24, and the third insulating layer 28. Ground, electrons are released into the channel region 22 to accumulate positive charge in the charge trap insulator 26. Therefore, the charge trap insulator 26 is in a state where positive charges are accumulated.

3B is a conceptual diagram showing a read operation of the high level data "1".

When the ground voltage GND is applied to the upper word line 18 and a positive voltage + Vread is applied to the lower word line 16, negative charges are applied to the upper and lower portions 22a and 22b of the channel region 22. Induced depletion layers are formed respectively to block the current path so that the channel region 22 is turned off.

4 is a detailed conceptual diagram illustrating a read operation of data "1" shown in FIG. 3B.

The depletion layer is formed on the upper portion 22a of the channel 22 by the positive charge stored in the charge trap insulator 26, and when the positive voltage + Vread is applied to the lower word line 16, the lower portion of the channel 22 is applied. A depletion layer is also formed at (22b) so that the current path of the channel 22 is blocked by the depletion layers 22a and 22b at the top and the bottom, so that it is in a high resistance state and is turned off.

At this time, if a slight voltage difference is applied between the drain 30 and the source 32, the channel 22 is off, so that a small off current flows.

5A and 5B are diagrams for describing an operation of writing and reading the low level data “0” of the charge trap insulator memory device according to the present invention.

First, FIG. 5A is a conceptual diagram illustrating a write operation of low level data "0".

When the negative voltage -V is applied to the drain region 30, the source region 32, and the lower word line 18, and the ground voltage GND is applied to the upper word line 18, the electrons of the channel region 22 The electrons are accumulated in the charge trap insulator 26 by moving to the charge trap insulator 26.

5B is a conceptual diagram illustrating a read operation of the low level data "0".

If a ground voltage GND is applied to the lower word line 16 and the upper word line 18, and a slight voltage difference is applied between the drain region 30 and the source region 32, a large on current flows because the channel is turned on. .

FIG. 6 is a detailed conceptual diagram illustrating a read operation of the low level data “0” shown in FIG. 5B.

A positive voltage + Vread is applied to the lower word line 16 to form a depletion layer on the lower portion 22b of the channel 22. However, a depletion layer is not formed on the upper portion of the channel 22. Flow.

At this time, when a slight voltage difference is applied between the drain 30 and the source 32, the channel 22 is turned on, so a large amount of on current flows.

As described above, in the read mode, the upper word line 18 and the lower word line 16 are set to the ground voltage GND so that voltage stress is not applied to the charge trap insulator 26, thereby improving the retention characteristics of the memory cell.

Accordingly, the depletion channel memory cell of the nanoscale level charge trap insulator structure of the present invention is capable of low voltage operation.

7 is a diagram illustrating a unit memory cell array of a charge trap insulator memory device according to the present invention.

The unit memory cell array includes a plurality of memory cells Q1 to Qm and switching elements N1 and N2. Here, the plurality of memory cells Q1 to Qm are connected in series, and the first switching device N1 is applied with the first selection signal SEL_1 to the gate terminal to selectively connect the bit line BL and the memory cell Q1, and the second switching device N2 is The second selection signal SEL_2 is applied to the gate terminal to selectively connect the sensing line S / L and the memory cell Qm.

The plurality of memory cells Q1 to Qm are selectively connected by the upper word lines WL_1 to WL_m and the lower word lines BWL_1 to BWL_m that are connected in series between the switching elements N1 and N2 and driven by the same row address decoder. The detailed configuration of each of the memory cells Q1 to Qm is as shown in FIGS. 2A and 2B.

FIG. 8 is a conceptual diagram illustrating a read operation of row data “0” in the unit memory cell array illustrated in FIG. 7. Here, the case where high level data "1" is stored in all the memory cells Q1-Q5 is demonstrated.

In this case, the ground voltage GND is applied to all upper word lines WL_1 to WL_5, and a positive read voltage + Vread is applied to the lower word line BWL_1 of the selected memory cell Q1. The ground voltage GND is applied to the remaining unselected lower word line BWL_1.

In this case, the ground voltage GND is applied to the upper word lines WL_2 to WL_5 and the lower word lines BWL_2 to BWL_5 for the remaining unselected memory cells Q2 to Q5. Accordingly, the depletion layer is formed in the upper portion 22a of the channel region 22 by the charge stored in the charge trap insulator 26, but the depletion layer is not formed in the lower portion 22b, and the channel is turned on.

On the other hand, in the selected memory cell Q1, the depletion layer 22b is formed under the channel region 22 by the read voltage + Vread applied to the lower word line BWL_1, and the polarity of the charge stored in the charge trap insulator 26 is reduced. As a result, a depletion layer 22b is formed on the channel region 22. As a result, the channel 22 is turned off by the depletion layers 22a and 22b formed in the channel region 22, thereby blocking the current path from the source region 32 to the drain region 30. Therefore, data "1" stored in the selected memory cell Q1 can be read in the read operation mode.

FIG. 9 is a conceptual diagram for describing a read operation of row data “0” in the unit memory cell array illustrated in FIG. 7. Here, an example will be described in which the low level data "0" is stored in the selected memory cell Q1 and the high level data "1" is stored in all the remaining memory cells Q2 to Q5.

In this case, the ground voltage GND is applied to all word lines WL_1 to WL5, and a positive read voltage + Vread is applied to the lower word line BWL_1 of the selected memory cell Q1. The ground voltage GND is applied to all remaining unselected lower word lines BWL_2 to BWL_5.

Accordingly, a positive read voltage + Vread is applied to the lower word line BWL_1 of the selected memory cell Q1 so that a depletion layer is formed at the lower portion 22b of the channel region 22, but is stored in the charge trap insulator 26. Since the depletion layer is not formed in the upper portion 22a of the channel region 22 due to the polarity of the charge, the state is turned on. In addition, although a depletion layer is formed on the upper portion 22a of the channel region 22 due to the polarity of the charge stored in the memory cells Q2 to Q5 that are not selected, the ground voltage GND is applied to the lower word line BWL_1, so that the channel region 22 is formed. Since the depletion layer is not formed in the lower part 22b of, it is turned on.

Accordingly, the channel regions 22 of all the memory cells Q1 to Q5 are turned on so that current flows from the source region 32 to the drain region 30. Thus, data "0" stored in the selected memory cell Q1 can be read in the read operation mode.

10A and 10B are cross-sectional views illustrating a connection relationship between the memory cells Q1 and Qm and the switching elements N1 and N2 shown in FIG. 7.

The switching elements N1 and N2 are formed on the insulating layer 36 formed on the gate 34, the P-type channel region 38 formed on the insulating layer 36, and the N-type drain formed on both sides of the P-type channel region 38. The region 40 and the N-type source region 42 are included.

Referring to FIG. 10A, the N-type source region 42 of the switching element N1 is connected to the bit line BL through a contact plug, and the N-type drain region 22 is the P-type source region 32 of the memory cell Q1. ) And via contact plug and connection line CL1.

10B, the N-type source region 42 of the switching element N2 is connected to the bit line BL through a contact plug, and the N-type drain region 22 is the P-type source region of the memory cell Qm. 32 is connected via a contact plug and a connection line CL1.

Here, the connection line CL1 connecting the memory cells Q1 and Qm and the switching elements N1 and N2 is made of a metallic conductor.

11 is a circuit diagram illustrating a memory cell array structure of the charge trap insulator memory device according to the present invention.

The memory cell array structure of the charge trap insulator memory device includes a plurality of unit memory cell arrays 44 shown in FIG. 7, and is commonly connected to a plurality of bit lines BL_1 to BL_n in a column direction, and a plurality of upper portions in a row direction. The word lines WL_1 to WL_m, the lower word lines BWL_1 to BWL_m, the first selection signal SEL_1, the second selection signal SEL_2, and the sensing lines S / L_1 to S / L_n are commonly connected. Here, the plurality of bit lines BL_1 to BL_n are connected in one-to-one correspondence with the plurality of sense amplifiers 36.

 12 is a view for explaining the write operation of the charge trap insulator memory device according to the present invention.

The write operation cycle of the charge trap insulator memory device according to the present invention may be divided into two sub operation regions. That is, data "1" is written in the first sub operation area, and data "1" written in the first sub operation area is stored or data "0" is written in the second sub operation area.

If a high voltage is applied to the bit line BL for a predetermined period when the data "1" is to be preserved, the value of the data "1" written in the first sub-operation area is stored in the memory cell.

13 is a timing diagram illustrating a data “1” write operation of the charge trap insulator memory device according to the present invention. Here, an example in which the first memory cell Q1 of the first unit memory cell array 44 shown in FIG. 11 is selected will be described.

First, the t0 section is a precharge section of the memory cell, and all signals and lines are precharged to the ground voltage VSS.

When the first select signal SEL_1 and the second select signal SEL_2 transition to a high level in the period t1 and t2 and the switching elements N1 and N2 are turned on, the bit line BL_1 and the source terminal of the memory cell Q1 are connected, and the sensing line S / L and the drain terminal of the memory cell Qm are connected. In this case, the plurality of upper word lines WL_1 to WL_m, the plurality of lower word lines BWL_1 to BWL_m, the bit line BL_1, and the sensing line S / L_1 maintain a low level state.

When a negative voltage VNEG is applied to the word line WL_1 connected to the selected memory cell Q1 in the period t3 and t4, a high voltage is applied to the depletion channel layer between the upper word line WL_1 and the channel region 22 as shown in FIG. 3A. Electrons may be emitted to region 22 to write data "1".

In the periods t5 and t6, the upper word line WL_1 transitions to the ground voltage VSS to complete the write operation.

The first selection signal SEL_1 and the second selection signal SEL_2 transition to a low level in a period t7 to turn off the switching elements N1 and N2 to become a precharge period.

14 is a timing diagram illustrating a data " 1 " holding or a data " 0 " write operation of the charge trap insulator memory device according to the present invention. Here, an example in which the first memory cell Q1 of the first unit memory cell array 44 shown in FIG. 11 is selected will be described.

First, the t0 section is a precharge section of the memory cell, and all signals and lines are precharged to the ground voltage VSS.

When the first selection signal SEL_1 transitions to a high level in the periods t1 and t2, the first switching device N1 is turned on to connect the bit line BL_1 to the source terminal of the selected memory cell Q1.

At this time, the second selection signal SEL_2 becomes the negative voltage VNEG and the second switching element N2 is turned off, and the remaining lower word lines BWL_2 to BWL_m, which are not connected to the selected memory cell Q1, become the negative voltage VNEG to form a current path. do.

Accordingly, data applied to the bit line BL can be delivered to all the cells Q1 to Qm.

 In this case, the plurality of upper word lines WL_1 to WL_m, the bit line BL_1, and the sensing line S / L_1 maintain a low level state.

If the data to be written to the selected memory cell Q1 is "0" in the period t3, the bit line BL_1 transitions to the negative voltage VNEG, and if the data line "1" stored in the selected memory cell Q1 is to be maintained, the bit line BL_1 is low level. Keep it.

Subsequently, when the lower word line BWL_1, to which the selected memory cell Q1 is connected, transitions to a negative voltage VNEG in a period t4, as shown in FIG. 5A, the P-type channel region 22 of the memory cell Q1 selected by the upper word line WL_1, as shown in FIG. 5A. Electrons accumulate in the. Therefore, when a negative voltage VNEG is applied to the lower word line BWL_1 and a threshold voltage difference occurs, channel electrons flow into the charge trap insulator 26. Accordingly, data "0" can be written in the selected memory cell Q1.

On the other hand, when the data "1" stored in the selected memory cell Q1 is to be kept as it is, the bit line BL_1 is maintained at the ground voltage VSS to generate a voltage difference between the upper word line WL_1 and the P-type channel region 22 of the selected memory cell Q1. Data "1" can be saved.

The lower word line BWL_1 transitions back to the ground voltage VSS state in the period t5, and the bit line BL_1 transitions to the ground voltage VSS state in the period t6 to complete the high data “1” sustain operation or the low data “0” write operation.

In a period t7, the first selection signal SEL_1, the second selection signal SEL_2, and the remaining unselected lower word lines BWL_2 to BWL_m transition to a low level to become a precharge period.

15 is a timing diagram illustrating an operation of sensing data stored in a memory cell of the charge trap insulator memory device according to the present invention. Here, an example in which the first memory cell Q1 of the first unit memory cell array 44 shown in FIG. 11 is selected will be described.

First, the t0 section is a precharge section of the memory cell, and all signals and lines are precharged to the ground voltage VSS.

When the first selection signal SEL_1 and the second selection signal SEL_2 transition to a high level in the period t1 and the switching elements N1 and N2 are turned on, the bit line BL_1 and the source terminal of the selected memory cell Q1 are connected and the sensing line S / L And the drain terminal of the memory cell Qm are connected. In this case, the plurality of upper word lines WL_1 to WL_m, the plurality of lower word lines BWL_1 to BWL_m, the bit line BL_1, and the sensing line S / L_1 maintain a low level state.

The lower word line BWL_1 connected to the selected memory cell Q1 transitions to a high level in a period t2, and the remaining plurality of lower word lines BWL_2 to BWL_m maintain a low level. Accordingly, all of the plurality of memory cells Q2 to Qm except the selected memory cell Q1 are turned on so that the source terminal of the selected memory cell Q1 is connected to the ground voltage VSS.

At this time, all of the word lines WL_1 to WL_m maintain the ground voltage VSS state, so that the current flows between the bit line BL_1 and the sensing line S / L according to the polarity formed in the selected memory cell Q1.

When the sense amplifier enable signal S / A becomes high level in the period t3 and the sense amplifier 46 is operated to apply the sensing voltage VS to the bit line BL_1, the bit line BL_1 of the bit line BL_1 depends on the polarity stored in the selected memory cell Q1. The current flow is determined.

That is, as shown in FIG. 3B, it can be seen that data "1" is stored in the selected memory cell Q1 when no current is applied to the bit line BL_1.

On the other hand, as shown in FIG. 5B, when a current of a predetermined value or more flows through the bit line BL_1, it can be seen that data “0” is stored in the selected memory cell Q1.

When the sense amplifier enable signal S / A becomes the ground voltage VSS in the period t4 and the operation of the sense amplifier 46 is stopped, the bit line BL_1 transitions to the low level to complete the sensing operation.

In the period t5, the lower word line BWL_1 to which the selected memory cell Q1 is connected transitions to the ground voltage.

In the period t6, the first selection signals SEL_1 and the second SEL_2 transition to a low level, and the switching elements N1 and N2 are turned off.

As described above, the present invention does not destroy the data of the cell during the read operation using the Non Destructive Read Out (NDRO) method.

As described above, the charge trap insulator memory device according to the present invention has an effect of overcoming a scale down phenomenon in a memory cell structure using a nano trap level charge trap insulator.

In addition, the charge trap insulator memory device according to the present invention has the effect of stacking a plurality of charge trap insulator cell arrays in a cross-sectional direction using a plurality of cell insulating layers to increase the integrated capacity of a cell by the number of stacks of the cell array. .

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are claimed in the following claims It should be seen as belonging to a range.

Claims (18)

A plurality of serially connected memory cells in which data applied through the bit line is stored in the charge trap insulator or data stored in the charge trap insulator is output to the bit line according to potentials applied to the upper word line and the lower word line; A first switching element for selectively connecting a bit line and the plurality of memory cells according to a state of a first selection signal; And A second switching device for selectively connecting the sensing line and the plurality of memory cells in accordance with the state of the second selection signal, The plurality of memory cells A first insulating layer formed on the lower word line; A P-type float channel formed on the first insulating layer and having a resistance changed according to a polarity of the charge trap insulator; A P-type drain region and a P-type source region formed at both sides of the P-type float channel; A second insulating layer formed on the P-type float channel; The charge trap insulator formed on the second insulating layer; And And a third insulating layer formed above the charge trap insulator and below the upper word line. The method of claim 1, When high level data is written to the selected memory cell, Maintaining the turn-on state of the first switching element and the second switching element, applying a negative voltage to the upper word line, and connecting the lower word line, the bit line, and the sensing line to a ground voltage. A charge trap insulator memory device. The method of claim 2, And the upper word line of all other memory cells except for the selected memory cell is connected to a ground voltage. The method of claim 2, When maintaining the high level data stored in the selected memory cell, The first switching device maintains a turn on state, the second selection signal becomes a negative voltage, the second switching device maintains a turn off state, applies a negative voltage to the selected lower word line, And the upper word line and the bit line maintain a ground voltage. The method of claim 4, wherein And the lower word line of all other memory cells except the selected memory cell is connected to a negative voltage. The method of claim 2, When low level data is written to the selected memory cell, The first switching device maintains a turn on state, the second selection signal becomes a negative voltage, the second switching device maintains a turn off state, applies a negative voltage to the selected lower word line, And the upper word line maintains a ground voltage, and a negative voltage is applied to the bit line. The method of claim 6, And the lower word line of all other memory cells except for the selected memory cell is connected to a negative voltage. The method of claim 1, When sensing data stored in the selected memory cell, The first switching element and the second switching element remain turned on, the upper word line and the sensing line are connected to a ground voltage, and a high level read voltage is applied to the lower word line to which the selected memory cell is connected. And a sensing voltage is applied to the bit line. The method of claim 8, And the lower word line of all other memory cells except for the selected memory cell is connected to a ground voltage. A plurality of upper word lines and a plurality of lower word lines arranged in a row direction and parallel to each other; A plurality of bit lines arranged in a column direction; A plurality of sensing lines arranged in a vertical direction with the plurality of bit lines; A plurality of memory cell arrays disposed in an area where the plurality of upper word lines and the plurality of lower word lines and the plurality of bit lines cross each other; And a plurality of sense amplifiers for sensing and amplifying data carried on the bit lines in a one-to-one correspondence with the plurality of bit lines. Each of the plurality of memory cell arrays A plurality of serially connected memory cells in which data applied through the bit line is stored in the charge trap insulator or data stored in the charge trap insulator is output to the bit line according to potentials applied to the upper word line and the lower word line; A first switching element for selectively connecting a bit line and the plurality of memory cells according to a state of a first selection signal; And A second switching device for selectively connecting the sensing line and the plurality of memory cells in accordance with the state of the second selection signal, The plurality of memory cells A first insulating layer formed on the lower word line; A P-type float channel formed on the first insulating layer and having a resistance changed according to a polarity of the charge trap insulator; A P-type drain region and a P-type source region formed at both sides of the P-type float channel; A second insulating layer formed on the P-type float channel; The charge trap insulator formed on the second insulating layer; And And a third insulating layer formed above the charge trap insulator and below the upper word line. The method of claim 10, When high level data is written to the selected memory cell, Maintaining the turn-on state of the first switching element and the second switching element, applying a negative voltage to the upper word line, and connecting the lower word line, the bit line, and the sensing line to a ground voltage. A charge trap insulator memory device. The method of claim 11, And the upper word line of all other memory cells except for the selected memory cell is connected to a ground voltage. The method of claim 11, When maintaining the high level data stored in the selected memory cell, The first switching device maintains a turn on state, the second selection signal becomes a negative voltage, the second switching device maintains a turn off state, applies a negative voltage to the selected lower word line, And the upper word line and the bit line maintain a ground voltage. The method of claim 13, And the lower word line of all other memory cells except for the selected memory cell is connected to a negative voltage. The method of claim 11, When low level data is written to the selected memory cell, The first switching device maintains a turn on state, the second selection signal becomes a negative voltage, the second switching device maintains a turn off state, applies a negative voltage to the selected lower word line, And the upper word line maintains a ground voltage, and a negative voltage is applied to the bit line. The method of claim 15, And the lower word line of all other memory cells except for the selected memory cell is connected to a negative voltage. The method of claim 10, When sensing data stored in the selected memory cell, The first switching element and the second switching element remain turned on, the upper word line and the sensing line are connected to a ground voltage, and a high level read voltage is applied to the lower word line to which the selected memory cell is connected. And a sensing voltage is applied to the bit line. The method of claim 17, And the lower word line of all other memory cells except for the selected memory cell is connected to a ground voltage.

Images