KR20060074052A - Array substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to an array substrate for a liquid crystal display device using a polysilicon thin film transistor as a driving element and a switching element, and a manufacturing method thereof.

The present invention solves the problem of decreasing the aperture ratio due to the increase of the contact hole size when forming the source and drain electrodes of the polysilicon thin film transistor and the increase of parasitic capacitance by reducing the distance between the gate electrode and the source and drain electrodes. An array substrate for a liquid crystal display device and a method of manufacturing the same are provided.

Description

Array substrate for liquid crystal display device and manufacturing method thereof {Method of fabricating the same of an Array substrate for a Liquid Crystal Display Device}             

1 is a schematic plan view of a liquid crystal display device having a polycrystalline thin film transistor.

2A to 2F are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor of the prior art.

3 is an enlarged cross-sectional view of A of FIG. 2F;

4A to 4H are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor according to a first embodiment of the present invention.

FIG. 5 is an enlarged cross-sectional view of B of FIG. 4G; FIG.

6 is an enlarged cross-sectional view of a part of an array substrate including a driving device and a switching device of a polysilicon thin film transistor according to a second embodiment of the present invention;

<Description of the symbols for the main parts of the drawings>

111: insulating substrate 113: buffer layer

115: polysilicon layer 117: gate insulating film

119: gate electrode 121: interlayer insulating film                 

123: protective layer 125: source electrode

127: drain electrode 129: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device, and more particularly to a method for manufacturing a polysilicon thin film transistor used as a switching element or driving element of a liquid crystal display device.

Thin-film transistors formed in liquid crystal displays are mainly used for amorphous silicon as an active layer, but have a low mobility of electrons and holes, and are replaced by polycrystalline silicon that can be implemented as complementary (CMOS: Complemental Mental-Oxide Silicon) transistors. to be.

1 is a schematic plan view of a liquid crystal display device having a polysilicon thin film transistor composed of a switching element and a driving element.

As illustrated, the insulating substrate 3 may be largely defined as a display unit D1 and a non-display unit D2, and a plurality of pixels P are arranged in a matrix form on the display unit D1, and a switching device for each pixel. T and the pixel electrode 21 connected thereto are formed.

In addition, the gate line GL extending along one side of the pixel P and the data line DL perpendicular to the gate line GL.                         

The non-display part D2 includes driving circuit parts DP and GP, and the driving circuit parts DP and GP are located on one side of the substrate 3 to apply a signal to the gate wiring GL. And a data driving circuit part DP positioned on the other side of the substrate 3, which is not parallel thereto, to apply a signal to the data line DL.

In addition, the gate and data driving circuit units GP and DP are connected to an external signal input terminal OL.

The gate and data driving circuit units GP and DP control an internal signal input through the external signal input terminal OL therein and control the display to the pixel unit P through the gate and data lines GL and DL, respectively. Means for supplying signals and data signals.

2A to 2G are cross-sectional views illustrating a manufacturing process of a polysilicon thin film transistor according to the prior art.

In the thin film transistor according to the related art, as shown in FIG. 2A, a transparent insulating substrate 3 is prepared and a buffer layer 5 is formed on the insulating substrate 3.

Next, as shown in FIG. 2B, after depositing amorphous silicon (a-Si) on the substrate 3 on which the buffer layer 5 is formed and undergoing dehydrogenation, an island shape is formed through a crystallization process and a mask process. The active pattern 7 is formed.

Next, as shown in FIG. 2C, one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) on the substrate 3 on which the active pattern 7 is formed; A metal layer (not shown) is continuously deposited to form a gate insulating film 9 and a gate electrode 11.

Next, although not shown, an ohmic region is formed by doping impurity (n + or p +) ions into the active pattern 7 corresponding to both sides of the gate electrode 11.

Next, as shown in FIG. 2D, one of an inorganic insulating material group including silicon oxide (SiO ₂ ) and silicon nitride (SiN _x ) is deposited on the substrate 3 on which the active pattern 7 is formed. An interlayer insulating film 13 including holes 23a and 23b is formed.

Next, as shown in FIG. 2E, source and drain electrodes 15 and 17 contacting the active pattern 7 doped with impurities exposed through the contact holes 23a and 23b are formed.

Next, as shown in FIG. 2F, a protective layer 19 is formed on the substrate 3 on which the source and drain electrodes 15 and 17 are formed.

3 is an enlarged cross-sectional view of part A of FIG. 2F.

In general, in the case of inductively coupled plasma (ICP) equipment, when forming the contact hole of the interlayer insulating layer 13, only one etching process is performed to etch, but the use of the ICP equipment is expensive because the ICP equipment is expensive. Therefore, a contact hole is formed in the interlayer insulating film 13 by using an inexpensive reactive ion etching (RIE) device.

However, RIE equipment uses two different dry etching processes, {1} over {2} of the thickness of the interlayer insulating layer 13 of the contact hole forming part, and the other {1} over {2} using a wet etching process. Eggplant etching process should be performed.                         

This is a disadvantage that takes too long time only by the dry etching process in the RIE equipment, and also has the disadvantage that the size of the contact hole is formed when the wet etching process only proceeds, these two etching processes are used in parallel.

Due to the two etching processes, a critical dimension bias is etched to a size different from that of the mask pattern, whereby the area D of the contact hole is wider than the design value area.

The area D of the contact hole is formed from about 4 μm × 4 μm to about 8 μm × 8 μm.

Therefore, the source and drain electrodes 17 formed in the contact hole are also formed wide, thereby causing a problem of reducing the aperture ratio.

In addition, as the distance between the source and drain electrodes 17 and the gate electrode 11 is partially approached by the CD bias, a parasitic capacitance that degrades the image quality of the display may be increased.

The present invention has been proposed to solve the above-described problem, and the present invention has a first object to solve the problem of reducing the aperture ratio by reducing the size of the contact hole, and a second object to minimize the increase of the parasitic capacity. .

In order to achieve the above object, the present invention provides an insulating substrate; An active pattern formed on the substrate; A gate insulating film and a gate electrode sequentially formed on the active pattern; An interlayer insulating layer covering the gate electrode and including a first contact hole partially exposed at both ends of the active pattern; A protective layer formed on the interlayer insulating layer and surrounding the inside of the first contact hole and including a second contact hole to re-expose portions of both ends of the active pattern; A thin film transistor for a liquid crystal display device includes a source and a drain electrode contacting an active pattern exposed through the second contact hole.

An insulating substrate; An active pattern formed on the substrate; A gate insulating film and a gate electrode sequentially formed on the active pattern; An interlayer insulating layer covering the gate electrode and including a first contact hole partially exposed at both ends of the active pattern; A protective layer formed on the interlayer insulating layer and surrounding the inside of the first contact hole and including a second contact hole to re-expose portions of both ends of the active pattern; Source and drain electrodes in contact with the active pattern exposed through the second contact hole; An array substrate for a liquid crystal display device including a pixel electrode in contact with the drain electrode is provided.

A pixel region including a switching region and a substrate in which a driving region is defined; First active patterns formed in the switching region of the substrate, second and third active patterns formed in the driving region; A gate insulating layer formed on each of the active patterns; Respective gate electrodes formed on the gate insulating film; An interlayer insulating layer formed on the gate electrodes and including first contact holes partially exposed at both ends of the active patterns; A protective layer formed on the interlayer insulating layer, surrounding the inside of the first contact hole, and including a second contact hole to partially re-expose both ends of the active pattern; Source and drain electrodes in contact with each active pattern exposed through the second contact hole; An array substrate for driving integrated circuit liquid crystal display devices includes a pixel electrode in contact with a drain electrode of the switching region.

A buffer layer is formed between the substrate and the gate electrode, and the protective layer and the interlayer insulating layer may be formed of the same material of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ), respectively, or silicon nitride (SiN _x ). Alternatively, silicon oxide (SiO ₂ ) may be formed of different materials, respectively.

The first and second active patterns are divided into a first active region (channel region), a second active region (omic region), and an LDD region, and n + ions are doped in the second active region (omic region). N-ion is doped in the LDD region, and impurities are not doped in the first active region (channel region), and the third active pattern includes a first active region (channel region) and a second region. It is formed as an active region (ohmic region), and is not doped in the first active region (channel region), and the p + ion is doped in the second active region (ohmic region).

The gate electrode may be positioned in a region corresponding to the first active region (channel region) of the active pattern.

Preparing an insulating substrate; Forming an active pattern by forming an amorphous silicon layer on the substrate and crystallizing it; Forming a gate insulating film and a gate electrode on the active pattern; Forming an ohmic region by doping impurities at both ends of the exposed active pattern; Forming an interlayer insulating film including a first contact hole partially exposed at both ends of the doped active pattern; Forming a protective layer formed on the interlayer insulating layer, surrounding the exposed first contact hole and including a second contact hole re-exposing a part of both ends of the active pattern; And forming a source and a drain electrode contacting the active pattern exposed through the second contact hole.

Preparing an insulating substrate; Forming an active pattern by forming an amorphous silicon layer on the substrate and crystallizing it; Forming a gate insulating film and a gate electrode on the active pattern; Forming an ohmic region by doping impurities at both ends of the exposed active pattern; Forming an interlayer insulating film including a first contact hole partially exposed at both ends of the doped active pattern; Forming a protective layer formed on the interlayer insulating layer, surrounding the exposed first contact hole and including a second contact hole re-exposing a part of both ends of the active pattern; Forming source and drain electrodes in contact with the active pattern exposed through the second contact hole; Forming a pixel electrode in contact with the drain electrode

It provides an array substrate manufacturing method for a liquid crystal display device comprising a.

Defining a substrate as a pixel region including a switching region and a driving region; Forming an active pattern in the switching region and the driving region of the substrate; Forming a gate insulating film on each of the active patterns; Forming respective gate electrodes on the gate insulating film; Doping n-, n + and p + impurity ions on the active pattern; Forming an interlayer insulating layer formed on the active pattern doped with each impurity and a first contact hole that exposes both ends of each active pattern by etching the interlayer insulating layer; Forming a protective layer on the interlayer insulating layer, surrounding the exposed sidewalls of each of the exposed first contact holes, and including a second contact hole to partially re-expose both ends of the active pattern; Forming respective source and drain electrodes in contact with each active pattern through the exposed second contact holes; And forming a pixel electrode in contact with a drain electrode of the switching region.

And a buffer layer formed on the front surface of the substrate as one selected from a group of inorganic insulating materials including silicon nitride or silicon oxide, wherein the protective layer and the interlayer insulating film are made of the same material of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ). Each can be formed or can be formed of a different material of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ), respectively.

The first and second active patterns may be formed of a first active region (channel region), a second active region (omic region), and an LDD region, and doped n + ions in the second active region (omic region). And n-ion in the LDD region and not in the first active region (channel region), wherein the third active pattern includes a first active region (channel region) and a second active region (omic region). Is doped in the first active region (channel region) and doped with p + ions in the second active region (omic region).

The gate electrode may be formed in a region corresponding to the first active region (channel region) of the active pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4H are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor according to a first embodiment of the present invention.

As shown in FIG. 4A, a transparent insulating substrate 111 is prepared, and a buffer layer 113 is formed on the insulating substrate 111.

The buffer layer 113 uses one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ).

Next, as shown in FIG. 4B, amorphous silicon (a-Si) is deposited on the substrate 111 on which the buffer layer 113 is formed, and then dehydrogenated to form an island-shaped active pattern 115. .

Next, as shown in FIG. 4C, a gate insulating film 117 and a gate electrode 119 are formed. In this process, silicon nitride (SiN _x ) or the like is formed on the substrate 111 on which the active pattern 115 is formed. A gate insulating film 117 is formed by depositing one selected from the group of inorganic insulating materials including silicon oxide (SiO ₂ ), and a gate electrode 119 is formed by depositing and patterning a metal on the gate insulating film 117. .

Next, although not shown, an ohmic region is formed by doping impurity (n + or p +) ions into the active pattern 115 corresponding to both sides of the gate electrode 119.

Next, as shown in FIG. 4D, an inorganic insulating material such as silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) is deposited on the substrate 111 on which the gate insulating film 117 and the gate electrode 119 are formed. The interlayer insulating layer 121 is formed and patterned to form first contact holes 131a and 131b exposing the active patterns 115 doped with impurities to correspond to both sides of the gate electrode 119.

Next, as shown in FIG. 4E, the protective layer 123 is formed by depositing silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) on the interlayer insulating layer 121 on which the first contact hole is formed.

The interlayer insulating layer 121 and the protective layer 123 may be formed of one of the same groups of inorganic insulating materials, and may also be formed of different inorganic insulating materials.

That is, the interlayer insulating layer 121 and the protective layer 123 may be formed of the same silicon oxide (SiO ₂ ), or the interlayer insulating layer 121 and the protective layer 123 are formed of silicon nitride (SiN _x ). can do. In addition, the interlayer insulating layer 121 may be formed of silicon oxide (SiO ₂ ), and the protective layer 123 may be formed of silicon nitride (SiN _x ), or vice versa.

Next, as shown in FIG. 4F, the protective layer 123 is patterned to form second contact holes 132a and 132b for re-exposing the active pattern 115 doped with the impurity.

In this case, the protective layer 123 is configured to surround the inside of the first contact hole (131a and 131b of FIG. 4D). Therefore, the second contact hole can be formed much smaller than the area of the conventional first contact hole.

At this time, the areas of the second contact holes 132a and 132b are formed to have a size of about 3 μm × 3 μm or less.

Next, as shown in FIG. 4G, a metal layer is deposited and patterned on the substrate 111 on which the protective layer 123 including the second contact holes (132a and 132b of FIG. 4F) having the smaller size is deposited. Source and drain electrodes 125 and 127 are formed to contact the active pattern 115 doped with impurities exposed through the second contact hole 132a and 132b of FIG. 4F.

In other words, the source and drain electrodes 125 and 127 are formed to contact the active pattern 115 exposed through the second contact holes 132a and 132b of the protective layer 123, and the protective layer 123 It is formed at the top of the.

Next, as shown in FIG. 4H, the pixel electrode 129 is formed.

The pixel electrode 129 is in contact with the drain electrode 127 and is a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) having excellent transmittance on the entire surface of the substrate 111. It is formed by depositing a selected one of the.

5 is an enlarged cross-sectional view of B of FIG. 4G.

As illustrated, one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ), surrounding the inside of the first contact hole (131a and 131b of FIG. 4D), and The protective layer 123 is formed on the front surface.

Next, by patterning the E region of the protective layer 123, and forming a second contact hole (132a, 132b of Fig. 4f) for re-exposing the active pattern (not shown), the protection surrounding the inside of the contact hole The area of the contact hole is reduced by the layer 123.

When the source and drain electrodes 127 are formed in the reduced contact hole, the formation area of the source and drain electrodes 127 is reduced as shown, and the overall plane of the source and drain electrodes is also reduced.

In addition, as the area of the contact hole decreases, the distance between the source and drain electrodes and the gate electrode is increased, thereby reducing the parasitic capacitance.

6 is an enlarged cross-sectional view of a portion of an array substrate including a driving device and a switching device of a polysilicon thin film transistor according to a second embodiment of the present invention.

CMOS elements and n-type thin film transistors are disposed in the driving circuit regions A and B and the switching region C of the substrate 211, and the pixel electrodes 227 contacting the n-type thin film transistors in the pixel region P. This is made up.

As illustrated, a buffer layer 213 is formed on the insulating substrate 211, and the first to third actives are respectively formed in the driving circuit regions A and B and the switching region C on the buffer layer 213. Patterns 215a, 215b, and 215c are constructed.

The first to third active patterns 215a, 215b, and 215c are patterns of active layers, and each of the first to third active patterns 215a, 215b, and 215c may be defined as a first active region V1 and a second active region V2. have.

A gate insulating film 217 is formed on an entire surface of the substrate 211 including the first to third active patterns 215a, 215b, and 215c, and the active patterns 215a, 215b, and 215c are disposed on the gate insulating film 217. Each gate electrode 219 is formed to correspond to the first active region V1 (channel region) of the ().

An interlayer insulating film 221 is formed on the entire surface of the substrate 211 on which the gate electrode 219 is formed, and the interlayer insulating film 221 and the gate insulating film 217 below are etched to form the active patterns 215a and 215b. , Each first contact hole (not shown) exposing each second active region V2 (ohmic region) of the second and second regions 215c is formed.

A protective layer 223 is formed on the interlayer insulating layer 221 including each of the first contact holes (not shown). The protective layer 223 is formed to surround the inside of each first contact hole.

Next, each of the second contact holes (not shown) may be etched to re-expose each of the second active regions V2: the ohmic regions of the active patterns 215a, 215b, and 215c. Is formed.

Source and drain electrodes 225a and 225b are formed to contact the second active regions V2 (ohmic regions) of the exposed active patterns 215a, 215b, and 215c through the second contact holes.

In the above-described configuration, the first active pattern 215a of the driving circuit regions A and B and the switching region C and the second active region V2 of the second active pattern 215b are formed of gate electrodes ( N-ion-doped LDD (Lightly Doped Drain) region F adjacent to both sides 219 and n-ion-doped ohmic region except for LDD region F.

In the pixel region P, a pixel electrode 227 connected to the drain electrode 225a of the switching region C is formed.

     By reducing the size of the contact hole, the metal layer of the source and drain electrodes formed in contact with the contact hole is also formed in a small area, thereby improving the aperture ratio.

In addition, since the distance between the gate electrode and the source and drain electrodes is secured by the protective layer, the parasitic capacitance is reduced.

The present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention.

As described above, since the size of the contact hole is reduced by the protective layer surrounding the inside of the contact hole according to the present invention, there is an effect of solving the problem of reducing the aperture ratio caused by the contact hole.

In addition, there is an effect of reducing the parasitic capacitance caused by the close distance between the source and drain electrodes and the gate electrode.

Claims (16)

An insulating substrate; An active pattern formed on the substrate; A gate insulating film and a gate electrode sequentially formed on the active pattern; An interlayer insulating layer covering the gate electrode and including a first contact hole partially exposed at both ends of the active pattern; A protective layer formed on the interlayer insulating layer and surrounding the inside of the first contact hole and including a second contact hole to re-expose portions of both ends of the active pattern; Source and drain electrodes in contact with the active pattern exposed through the second contact hole Thin film transistor for liquid crystal display device comprising a. An insulating substrate; An active pattern formed on the substrate; A gate insulating film and a gate electrode sequentially formed on the active pattern; An interlayer insulating layer covering the gate electrode and including a first contact hole partially exposed at both ends of the active pattern; A protective layer formed on the interlayer insulating layer and surrounding the inside of the first contact hole and including a second contact hole to re-expose portions of both ends of the active pattern; Source and drain electrodes in contact with the active pattern exposed through the second contact hole; A pixel electrode in contact with the drain electrode Array substrate for a liquid crystal display device comprising a. A pixel region including a switching region and a substrate in which a driving region is defined; First active patterns formed in the switching region of the substrate, second and third active patterns formed in the driving region; A gate insulating layer formed on each of the active patterns; Respective gate electrodes formed on the gate insulating film; An interlayer insulating layer formed on the gate electrodes and including first contact holes partially exposed at both ends of the active patterns; A protective layer formed on the interlayer insulating layer and surrounding the inside of the first contact hole, the protective layer including respective second contact holes partially re-exposing both active patterns; Source and drain electrodes in contact with each active pattern exposed through the second contact hole; A pixel electrode in contact with the drain electrode of the switching region Drive circuit integrated liquid crystal display device array substrate comprising a. The selected term of any one of claims 1 to 3, A thin film transistor for liquid crystal display device comprising a buffer layer between the substrate and the gate electrode. The selected term of any one of claims 1 to 3, The protective layer and the interlayer insulating film is formed of different materials of silicon nitride (SiN _x) or silicon oxide (SiO ₂₎ of the can formed of the same material and, or, a silicon nitride (SiN _x) or silicon oxide (SiO ₂₎ A thin film transistor for a liquid crystal display device, characterized in that. The method of claim 3, wherein The first and second active patterns are divided into a first active region (channel region), a second active region (omic region), and an LDD region, and n + ions are doped in the second active region (omic region). An array substrate for an integrated liquid crystal display device as claimed in claim 1, wherein n-ion is doped in the LDD region and impurities are not doped in the first active region (channel region). The method of claim 3, wherein The third active pattern is formed of a first active region (channel region) and a second active region (omic region), and is not doped in the first active region (channel region), and the second active region (omic region). An array substrate for a drive circuit-integrated liquid crystal display device, wherein p + ions are doped. The method of claim 6, And the gate electrode is positioned in a region corresponding to the first active region (channel region) of the active pattern. Preparing an insulating substrate; Forming an active pattern by forming an amorphous silicon layer on the substrate and crystallizing it; Forming a gate insulating film and a gate electrode on the active pattern; Forming an ohmic region by doping impurities at both ends of the exposed active pattern; Forming an interlayer insulating film including a first contact hole partially exposed at both ends of the doped active pattern; Forming a protective layer formed on the interlayer insulating layer, surrounding the exposed first contact hole and including a second contact hole re-exposing a part of both ends of the active pattern; Forming source and drain electrodes in contact with the active pattern exposed through the second contact hole Thin film transistor manufacturing method for a liquid crystal display device comprising a. Preparing an insulating substrate; Forming an active pattern by forming an amorphous silicon layer on the substrate and crystallizing it; Forming a gate insulating film and a gate electrode on the active pattern; Forming an ohmic region by doping impurities at both ends of the exposed active pattern; Forming an interlayer insulating film including a first contact hole partially exposed at both ends of the doped active pattern; Forming a protective layer formed on the interlayer insulating layer, surrounding the exposed first contact hole and including a second contact hole re-exposing a part of both ends of the active pattern; Forming source and drain electrodes in contact with the active pattern exposed through the second contact hole; Forming a pixel electrode in contact with the drain electrode Array substrate manufacturing method for a liquid crystal display device comprising a. Defining a substrate as a pixel region including a switching region and a driving region; Forming an active pattern in the switching region and the driving region of the substrate; Forming a gate insulating film on each of the active patterns; Forming respective gate electrodes on the gate insulating film; Doping n-, n + and p + impurity ions on the active pattern; Forming an interlayer insulating layer formed on the active pattern doped with each impurity and a first contact hole that exposes both ends of each active pattern by etching the interlayer insulating layer; Forming a protective layer on the interlayer insulating layer, surrounding the exposed sidewalls of each of the exposed first contact holes, and including a second contact hole to partially re-expose both ends of the active pattern; Forming respective source and drain electrodes in contact with each active pattern through the exposed second contact holes; Forming a pixel electrode in contact with the drain electrode of the switching region Array circuit manufacturing method for a drive circuit-integrated liquid crystal display device comprising a. 12. The method according to any one of claims 9 to 11, wherein And a buffer layer formed on the front surface of the substrate, wherein the buffer layer is formed of one selected from the group of inorganic insulating materials including silicon nitride or silicon oxide. 12. The method according to any one of claims 9 to 11, wherein The protective layer and the interlayer insulating film is formed of different materials of silicon nitride (SiN _x) or silicon oxide (SiO ₂₎ of the can formed of the same material and, or, a silicon nitride (SiN _x) or silicon oxide (SiO ₂₎ A method of manufacturing an array substrate for a liquid crystal display device, characterized in that. The method of claim 11, The first and second active patterns are formed of a first active region (channel region), a second active region (omic region), and an LDD region. The second active region (omic region) is doped with n + ions, and LDD A method of manufacturing an array substrate for an integrated liquid crystal display device, characterized in that the region is doped with n-ions and not doped with the first active region (channel region). The method of claim 11, The third active pattern is formed of a first active region (channel region) and a second active region (omic region). The third active pattern is not doped in the first active region (channel region). A method of manufacturing an array substrate for an integrated liquid crystal display device, wherein the p + ions are doped. The method of claim 14, And the gate electrode is formed in a region corresponding to the first active region (channel region) of the active pattern.

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