KR20060070734A - Nonvolatile Memory Device and Its Program Verification Method - Google Patents

Abstract

The present invention relates to a nonvolatile memory device and a program verification method thereof, which perform two-page program verification by separating a sensing node during program verification. The page buffer includes a sensing node separator that separates the sensing node into a sensing node connected to an even bit line and a sensing node connected to an odd bit line during program verification.

Page buffer, program verify, verify time

Description

Non-volatile memory device and method for verifying successful programming             

1 is a circuit diagram illustrating a NAND flash memory device according to a preferred embodiment of the present invention.

FIG. 2 is a timing diagram for describing an operation of the NAND flash memory device of FIG. 1.

3 is a flowchart illustrating a program verification method of the NAND flash memory device of FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: memory cell array 200: bit line selection unit

300: page buffer 310: sensing node separation unit

320: precharge unit 330: main register

340: Cache register 350: program verification unit

360: Pass / fail detector

The present invention relates to a NAND flash memory device, and more particularly, to a nonvolatile memory device and a program verification method thereof capable of reducing verification time by performing two-page program verification.

There is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function that rewrites data at regular intervals. Here, the program refers to an operation of writing data to a memory cell.

For high integration of memory devices, a NAND type flash memory device is developed in which a plurality of memory cells are connected in series (that is, structures in which adjacent cells share a drain or a source with each other) to form a string. It became. Unlike NOR-type flash memory devices, NAND-type flash memory devices are memory devices that read information sequentially.

A NAND type flash memory device uses a page buffer to store a large amount of information or to read stored information in a short time. The page buffer receives a large amount of data from an input / output pad and provides the memory cells or stores and outputs data of the memory cells. In general, a page buffer is generally composed of a single register for temporarily storing data. However, in recent years, a dual register is used to increase program speed when programming a large amount of data in a NAND type flash memory device.

Conventionally, only one page has been programmed for one program time. The program throughput is 21.12 Mb / s, since 528 bytes can be programmed in one page programming. However, with increasing capacities, program speeds must be made faster. Although a two-page program has been developed to meet these demands, there is a problem in that there is no verify scheme.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a nonvolatile memory device capable of performing two-page program verification and a verification method thereof.

A nonvolatile memory device according to a preferred embodiment of the present invention, which is designed to achieve the above object, comprises: an array of memory cells connected to first and second bit lines; And a page buffer connected to the first or second bit line through a sensing node, wherein the page buffer is connected to the sensing node connected to the first bit line and the sensing node connected to the second bit line during program verification. Sensing node separation unit for separating into a sensing node; The main register maintains an initial voltage level when no data is programmed in the memory cells connected to the first bit line, and changes the initial voltage level when data is programmed in the memory cells connected to the first bit line. ; If no data is programmed in the memory cells connected to the second bit line, the voltage level is maintained at an initial state. If data is programmed in the memory cells connected to the second bit line, the voltage register is changed from the initial state. ; And outputting a first signal for program verification at a first voltage level when the voltage level of the main register or the cache register is maintained at an initial state, and outputting the first signal for a program verification at a first voltage level. And a program verifying unit which outputs one signal in a floating state.

In accordance with another aspect of the present invention, there is provided a method of verifying a program of a nonvolatile memory device, including: an array of memory cells connected to first and second bit lines; And a page buffer connected to the first and second bit lines through a sensing node and having a main register and a cache register, the nonvolatile memory device comprising: connecting the sensing node to the first bit line during program verification. Separating the sensing node into a sensing node connected to the second bit line; When data is programmed in memory cells connected to the first or second bit line, the voltage level of the main register or the cache register is changed from an initial state, and memory cells connected to the first or second bit line. Maintaining a voltage level of the main register or the cache register in an initial state when no data is programmed in the memory; And when the voltage level of the main register or the cache register maintains the initial state, generates a first signal for program verification at the first voltage level, and changes the voltage level of the main register or the cache register from the initial state. In this case, the step of generating the first signal in a floating state.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating a NAND flash memory according to a preferred embodiment of the present invention.

Referring to FIG. 1, a NAND type flash memory device includes an array of memory cells 100 and a page buffer 300 connected to bit lines BLe and BLo.

The page buffer 300 includes a bit line selection unit 200, a sensing node separation unit 310, a precharge unit 320, a main register 330, a cache register 340, a program verification unit 350, and a pass. / Fail detection unit 350 is included.

The bit line selector 200 includes NMOS transistors N1-N4. The NMOS transistor N1 is turned on by the discharge signal DISCHe to apply the control signal VIRPWR to the even bit line BLe. The NMOS transistor N2 is turned on by the discharge signal DISCHo to apply the control signal VIRPWR to the odd bit line BLo. In the read operation, the control signal VIRPWR of 0 V is applied to the selected bit line, while in the program operation, the control signal VIRPWR of the power supply voltage VCC is applied to the selected bit line. In addition, the NMOS transistor N3 is turned on by the bit line select signal BSLe to connect the even bit line BLe and the sensing node SO. The NMOS transistor N4 is turned on by the bit line selection signal BSLo to connect the odd bit line BLo and the sensing node SO.

The sensing node separation unit 310 is configured to separate or connect the sensing node SO and includes a transfer gate TG11 that is turned off by the program signals M_PGM and M_PGMb. The transfer gate TG11 is turned on when data is programmed into the memory cell to connect the sensing node SO, and is turned off when verifying whether or not data is programmed in the memory cell to turn the sensing node SO into an even bit line. ) And an odd bit line (BLo), which are turned on to precharge the sensing node for program verification.

The precharge unit 320 is for precharging the sensing node SO to logic high during program verification. One end of the precharge unit 320 is connected to the power supply voltage VCC and the other end of the precharge signal PRECHb is connected to the sensing node SO. It is composed of a PMOS transistor (P11) is turned on / off by receiving a. The precharge unit 310 precharges the sensing node SO to logic high when the precharge signal PRECH is input to logic low to verify the program after the program is finished. When the program is a pass, that is, when data is programmed in the memory cell, the sensing cell SO is precharged to logic high because the memory cell is charged (logic high). In contrast, when a program fails, i.e., when data is not programmed in the memory cell, the memory cell is empty, so the signal of the sensing node SO is discharged to the memory cell connected to the selected bit line so that the logic low do.

The main register 330 includes a main latch L1 and NMOS transistors N11, N12, and N13. One end of the NMOS transistor N11 is connected to the sensing node SO, is connected to the node QB of the other main latch L1, and receives the program signal PGM1 through the gate. The NMOS transistor N11 is turned on when programming data into the memory cell and turned off during program verification. One end of the NMOS transistor N12 is connected to the node QBb of the main latch L1 and is turned on / off by receiving a signal of the sensing node SO through a gate. When data is programmed in the memory cell connected to the even bit line BLe, the NMOS transistor N12 is turned on by receiving a signal of the sensing node SO of logic high as a gate. One end of the NMOS transistor N13 is connected to the other end of the NMOS transistor N11, the other end thereof is connected to the ground voltage VSS, and is turned on / off by receiving the main latch signal MLH through the gate. The NMOS transistor N13 is turned on when a logic latched main latch signal MLH is applied to a gate when data is programmed in a memory cell connected to the even bit line BLe. The main latch L1 constitutes a latch with inverters IV11 and IV12. When data is not programmed in the memory cell connected to the even bit line BLe, the initial voltage level state, that is, the node QBb is logic high, the node If QB remains logic low and NMOS transistors N11 and N12 are turned on when data is programmed in the memory cell, node QBb is turned logic low and node QB is turned logic high.

The cache register 340 includes a cache latch L2 and NMOS transistors N14-N18. The NMOS transistor N16 is connected between the node QAb of the cache latch L2 and the input / output line IO and is turned on / off by receiving a data input signal DI through a gate. The NMOS transistor N16 transfers data input from the input / output line IO to the node QAb of the cache latch L2. This NMOS transistor N16 is turned on when programming data into the memory cell and turned off during program verification. The NMOS transistor N15 is connected between the node QAb of the cache latch L2 and the node SO and is turned on / off by receiving a data transfer signal TRAN to the gate. The NMOS transistor N15 transfers the data stored in the cache latch L2 to the main latch L1 through the sensing node SO during the program operation, and is turned off during the program verification. One end of the NMOS transistor N16 is connected to the sensing node SO, the other end is connected to the node QA of the cache latch L2, and is turned on / off by receiving a program signal PGM2 through a gate. The NMOS transistor N16 programs data stored in the cache latch L2 into a memory cell during a program operation, and is turned off during program verification. One end of the NMOS transistor N17 is connected to the node QAb of the cache latch L2 and is turned on / off by receiving a signal of the sensing node S0 to the gate. When data is programmed in a memory cell connected to the odd bit line BLo, the NMOS transistor N17 is turned on by receiving a signal of a sensing node SO of logic high as a gate. One end of the NMOS transistor N18 is connected to the other end of the NMOS transistor N17, the other end is connected to the ground voltage VSS, and is turned on / off by receiving the cache latch signal CLH through the gate. When data is programmed in a memory cell connected to the odd bit line BLo, the NMOS transistor N17 is turned on by receiving the logic latch main latch signal MLH as a gate. The cache latch L2 constitutes a latch with inverters IV13 and IV14. When data is not programmed in the memory cell connected to the odd bit line BLo, the initial voltage level state, that is, the node QBb is logic high, the node If QB remains logic low and data is programmed in the memory cell, since the NMOS transistors N17 and N18 are all turned on, the node QBb is changed to logic low and the node QB is changed to logic high. The above-described NMOS transistors N17 and N18 are turned off when programming data to the memory cells and turned on during program verification.

The program verifying unit 350 is to verify whether or not data is programmed in the memory cell, and includes PMOS transistors P12 and P13. One end of the PMOS transistor P12 is connected to the power supply voltage VCC and is turned on / off by receiving a signal of the node QB of the main latch L1 through a gate. The PMOS transistor P12 is the PMOS transistor P12 because the node QB of the main latch L1 is logic high when the program is successful, that is, when data is programmed in the memory cell connected to the even bit line BLe. Is turned off to make the program verify signal nWDO float. In contrast, when the program fails, that is, when data is not programmed in the memory cell connected to the even bit line BLe, the PMOS transistor P12 is turned on because the node QB of the main latch L1 is logic low. To bring the program verify signal (nWDO) to logic high. One end of the PMOS transistor P13 is connected to the power supply voltage VCC and turned on / off by receiving a signal of the node QA of the cache latch L2 through a gate. The PMOS transistor P13 is a PMOS transistor P12 because the node QA of the cache latch L2 is logic high when the program is successful, that is, when data is programmed in the memory cell connected to the odd bit line BLo. ) Is turned off, causing the program verify signal nWDO to float. In contrast, when the program fails, that is, when data is not programmed in the memory cell connected to the odd bit line BLo, the PMOS transistor P13 is turned on because the node QB of the cache latch L2 is logic low. To bring the program verify signal (nWDO) to logic high.

The pass / fail detector 360 detects whether the program verification is a pass or a fail, and includes an NMOS transistor N19 and a NAND gate ND11. When the pass / fail check signal CHK is logic high, when the program verify signal nWDO is logic high because the data is not programmed in the memory cell connected to the selected bit line, the NMOS transistor N19 is also turned on. -ON, but fail to discharge node nWDO_e to logic low. This is because the NMOS transistor N19 is composed of a week transistor, so the current flows very small. This small current is absorbed by the logic high program verify signal (nWDO) and cannot transition the program verify signal (nWDO) from logic high to logic low. In this case, the NAND gate ND11 inverts the logic high pass / fail check signal CHK and the logic high program verify signal nWDO to output the pass / fail detection signal WDO to logic low, and erase the logic high. Determines that is a failure.

However, when the pass / fail check signal CHECK is logic high, the data is programmed in the memory cell connected to the selected bit line, and when the program verify signal nWDO is floating, the NMOS transistor N19 is turned on and programmed. The verification signal (nWDO) is logic low. This is because the program verify signal nWDO is in a floating state, so even if the NMOS transistor N19 is a week transistor, a very small current flows the program verify signal nWDO to logic low. In this case, the NAND gate ND11 inverts a logic high pass / fail check signal CHK and a logic low program verify signal nWDO to output a pass / fail detection signal WDO to logic high, and erase the logic high. Is determined to be a pass.

Hereinafter, a program verifying operation of a nonvolatile memory device will be briefly described with reference to FIGS. 1 and 2.

After the program is finished, the PMOS transistor P11 is turned on using the precharge signal PRECHb to precharge the node SO to logic high. The signal precharged at the node SO is charged when the data is programmed in the memory cell connected to the even bit line BLe. Therefore, the signal precharged at the node SO is not discharged through the bit line BLe. Therefore, it remains precharged. In this case, since the NMOS transistors N12 and N13 are turned on, the node QB of the main latch L1 is changed from logic high to logic low, and the node QB is changed from logic low to logic high. Then, the PMPOS transistor P12 is turned off and the program verify signal nWDO is in a floating state.

In contrast, when data is not programmed in a cell connected to the even bit line BLe, the memory cell is in an empty state, and thus a signal precharged to the sensing node SO is discharged through the bit line BLe. In this case, the NMOS transistors N12 and N13 are turned off, so that the node QBb and the node QB of the main latch L1 maintain their initial states (node QBb is logic high and node QB is logic low). Then, the PMOS transistor P12 is turned on so that the program verify signal nWDO becomes logic high.

The cache register 340 and the PMOS transistor P13 are used to verify whether data is programmed in a memory cell connected to the odd bit line BLO, and the operation of the cache register 340 is performed by the main register 330. The operation of the PMOS transistor P13 is the same as that of the PMOS transistor P12.

3 is a flowchart illustrating a program verifying method of the nonvolatile memory device of FIG. 1.

Referring to FIG. 3, first, two pages are programmed (S401), and then, whether or not data is programmed in a memory cell connected to an even bit line (S402), or data is stored in a memory cell connected to an odd bit line. Verifies whether or not is programmed (S403). At this time, as described above, it is determined whether the program is a pass or a fail (S404), if the program is a pass (PASS), the program is terminated (S405), and if the program is a fail (FAIL), the two-page program is executed again ( S401).

As described above, according to the present invention, it is possible to program verify two pages, which has the advantage of reducing the program verification time as compared with the prior art.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (12)

An array of memory cells connected to the first and second bit lines; And A page buffer connected to the first or second bit line through a sensing node, the page buffer A sensing node separation unit for separating the sensing node into a sensing node connected to the first bit line and a sensing node connected to the second bit line during program verification; The main register maintains an initial voltage level when no data is programmed in the memory cells connected to the first bit line, and changes the initial voltage level when data is programmed in the memory cells connected to the first bit line. ;  If no data is programmed in the memory cells connected to the second bit line, the voltage level is maintained at an initial state. If data is programmed in the memory cells connected to the second bit line, the voltage register is changed from the initial state. ; And  Outputting a first signal for program verification at a first voltage level when the voltage level of the main register or the cache register is maintained at an initial state; and when the voltage level of the main register or the cache register is changed from an initial state, 1. A nonvolatile memory device including a program verification unit configured to output a signal in a floating state. The method of claim 1, If the data is not programmed in the memory cells connected to the first or second bit line, the program verifying unit outputs the first signal to logic high, and the memory cell connected to the first or second bit line. A nonvolatile memory device outputting the first signal in a floating state when data is programmed. The method of claim 1, The program verifying unit may include: a first transistor configured to make the first signal logic high using a power supply voltage when the voltage level of the main register is changed from an initial state; And a second transistor configured to make the first signal logic high using the power supply voltage when the voltage level of the cache register is changed from an initial state. The method of claim 1, And a pass / fail detector for determining that the program is a fail when the first signal is at the first voltage level and determining that the program is a pass when the first signal is in the floating state. The method of claim 4, wherein The path / fail detection unit may include a logic element configured to logically combine the first signal and a second signal for checking a path / fail of the program verification and output a path / fail detection signal; And And a discharge transistor configured to discharge the input node, to which the first signal is input, from among the input nodes of the logic device to a logic low. The method of claim 1, And a precharge unit configured to precharge the sensing node to logic high for the program verification. The method of claim 6, If the signal precharged to the sensing node is discharged to memory cells connected to the first or second bit line, data is not programmed in the memory cell, and the signal precharged to the sensing node is the first or second signal. A nonvolatile memory device in which data is programmed in memory cells unless discharged to memory cells connected to a second bit line. An array of memory cells connected to the first and second bit lines; And a page buffer connected to the first or second bit line through a sensing node and having a main register and a cache register. Separating the sensing node into a sensing node connected to the first bit line and a sensing node connected to the second bit line during program verification; When data is programmed in memory cells connected to the first or second bit line, the voltage level of the main register or the cache register is changed from an initial state, and memory cells connected to the first or second bit line. Maintaining a voltage level of the main register or the cache register in an initial state when no data is programmed in the memory; And When the voltage level of the main register or the cache register maintains the initial state, the first signal for program verification is generated at the first voltage level, and the voltage level of the main register or the cache register is changed from the initial state. And generating the first signal in a floating state. The method of claim 8, Determining that the program operation is a fail when the first signal is generated at the first voltage level, and determining that the program operation is a pass when the first signal is generated in a floating state. Way. The method of claim 8, When the voltage level of the main register or the cache register is changed from the initial state, the first signal is generated at a logic high, and when the voltage level of the main register or the cache register is maintained at the initial state, the first signal is floated. Program Verification Method of Nonvolatile Memory Device Generated by. The method of claim 8, Precharging the sensing node for the program verification. The method of claim 11, If the signal precharged to the sensing node is not discharged to the memory cells connected to the first or second bit line, the voltage level of the main register or the cache register is changed from an initial state to the sensing node. And maintaining a voltage level of the main register or the cache register in an initial state when a precharged signal is discharged to memory cells connected to the first or second bit line.

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