KR20060068289A - Resistor Formation Method of Semiconductor Device - Google Patents
Resistor Formation Method of Semiconductor Device Download PDFInfo
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- KR20060068289A KR20060068289A KR1020040106941A KR20040106941A KR20060068289A KR 20060068289 A KR20060068289 A KR 20060068289A KR 1020040106941 A KR1020040106941 A KR 1020040106941A KR 20040106941 A KR20040106941 A KR 20040106941A KR 20060068289 A KR20060068289 A KR 20060068289A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 239000010408 film Substances 0.000 claims description 22
- 239000010409 thin film Substances 0.000 claims description 17
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/40—Resistors
- H10D1/47—Resistors having no potential barriers
- H10D1/474—Resistors having no potential barriers comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체소자의 레지스터 형성방법에 관한 것으로, 레지스터를 용이하게 형성하기 위하여, The present invention relates to a method for forming a register of a semiconductor device, in order to easily form a register,
금속배선의 형성공정후 상기 금속배선의 표면과 같은 위치에 레지스터를 형성하여 공정을 단순화시키고 후속 콘택식각공정을 용이하게 실시할 수 있도록 하여 반도체소자의 특성 열화를 방지함으로써 소자의 특성 및 신뢰성을 향상시킬 수 있도록 하는 기술이다. After forming the metal wiring, registers are formed at the same position as the surface of the metal wiring to simplify the process and facilitate the subsequent contact etching process to prevent deterioration of the characteristics of the semiconductor device, thereby improving the characteristics and reliability of the device. It's a technology that makes it possible.
Description
도 1a 내지 도 1f 는 본 발명의 제1실시예에 따른 반도체소자의 레지스터 형성공정을 도시한 단면도.1A to 1F are cross-sectional views illustrating a resistor forming process of a semiconductor device in accordance with a first embodiment of the present invention.
도 2a 내지 도 2d 는 본 발명의 제2실시예에 따른 반도체소자의 레지스터 형성공정을 도시한 단면도.2A to 2D are cross-sectional views illustrating a resistor forming process of a semiconductor device in accordance with a second embodiment of the present invention.
본 발명은 반도체소자의 레지스터 형성방법에 관한 것으로, 특히 RF ( radio frequency ) 소자의 중요 요소인 레지스터를 백엔드 공정 ( back end process ) 인 금속배선 공정에 적용하여 다양한 장점을 가지도록 하는 레지스터 ( resistor ) 의 형성하는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a resistor of a semiconductor device, and in particular, a resistor which has various advantages by applying a resistor, which is an important element of an RF (radio frequency) device, to a metal wiring process, which is a back end process. It relates to the technology of forming.
일반적으로, 레지스터는 전기, 전자 및 통신 분야에서 사용되며 캐패시터 ( capacitor ), 인덕터 ( inductor ) 와 함께 매우 중요한 수동 소자로서, 산업의 고도화에 따라 고기능, 초정밀 및 초소형 부품의 개발이 요구되고 있다. In general, resistors are used in the fields of electricity, electronics, and communication, and are very important passive elements together with capacitors and inductors, and according to the advancement of the industry, development of high-performance, ultra-precision and micro components is required.
이러한 요구에 부흥하기 위하여 저항체에 사용되는 재료의 특성이 적합해야 하며, 비저항치가 안정하고, 저항온도계수 ( temperature coefficient of resistance, TCR ) 가 작아야 한다.In order to meet these demands, the properties of the materials used in the resistors must be suitable, the resistivity must be stable, and the temperature coefficient of resistance (TCR) must be small.
이러한 저항소자로 박막 레지스터 ( thin film transistor, TFR ) 가 각종 소자에 탑재되고 있으며 다양한 형태로 구현되고 있다.As such a resistor, a thin film transistor (TFR) is mounted in various devices and implemented in various forms.
현재 대부분의 박막 레지스터 구현은 IMD ( inter metal dielectrics ) 사이나 금속배선 위에 복잡한 공정으로 구현되고 있다. Most thin film resistor implementations are currently implemented in complex processes between intermetal dielectrics (IMDs) or over metallization.
상기한 바와 같이 종래기술에 따른 반도체소자의 레지스터 형성방법은, IMD 사이나 금속배선 상에 복잡한 공정으로 형성하기 때문에 복잡한 공정에 따른 문제점이 유발될 수 있으며 그에 따른 소자의 특성 열화가 발생될 수 있는 문제점이 있다. As described above, in the method of forming a resistor of a semiconductor device according to the related art, a complex process may be formed between IMDs or on metal wires, which may cause a problem due to a complicated process, which may result in deterioration of device characteristics. There is a problem.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 금속배선의 형성공정 중에 간단한 방법으로 레지스터를 형성하여 공정을 단순화시키고 그에 따른 특성 열화를 최소화시킬 수 있도록 하는 반도체소자의 레지스터 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method of forming a resistor of a semiconductor device that can simplify the process and minimize the deterioration of characteristics by forming a resistor in a simple manner during the formation of metal wiring in order to solve the above problems of the prior art. The purpose is.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 레지스터 형성방법은, In order to achieve the above object, a method of forming a register of a semiconductor device according to the present invention,
금속배선이 형성된 반도체기판 상에 질화막 및 레지스터용 박막을 형성하는 공정과, Forming a nitride film and a thin film for a resistor on the semiconductor substrate on which the metal wiring is formed;
상기 레지스터용 박막을 패터닝하여 레지스터를 형성하는 공정과,Patterning the resist thin film to form a resistor;
후속 공정으로 상기 레지스터 및 금속배선에 콘택되는 금속배선을 형성하는 공정을 포함하는 것과,A subsequent step of forming a metal wire contacting the resistor and the metal wire;
상기 레지스터용 박막은 TaN 이나 TiN 으로 형성되는 것을 특징으로 한다. The resistor thin film is formed of TaN or TiN.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f 는 본 발명의 제1실시예에 따른 반도체소자의 레지스터 형성방법을 도시한 단면도이다. 1A to 1F are cross-sectional views illustrating a method of forming a resistor in a semiconductor device according to a first embodiment of the present invention.
도 1a를 참조하면, 반도체기판(미도시) 상부에 제1산화막(11), 제1질화막(13) 및 제2산화막(15)을 적층한다. Referring to FIG. 1A, a
그 다음, 다마신 방법으로 제1금속배선을 형성한다. Then, the first metal wiring is formed by the damascene method.
상기 다마신 방법은 다음과 같다. The damascene method is as follows.
먼저, 금속배선 콘택마스크(미도시) 및 금속배선 마스크(미도시)를 이용한 사진식각공정으로 상기 반도체기판을 노출시키는 제1콘택홀(17) 및 제1금속배선 영역(19)을 형성한다. First, a
상기 제1콘택홀(17) 및 제1금속배선 영역(19)의 표면에 확산방지막(21)을 형성하고 상기 제1콘택홀(17) 및 제1금속배선 영역(19)을 매립하는 Cu 박막(23)을 전체표면상부에 형성하고 이를 평탄화식각하여 제1금속배선을 형성한다. 이때, 상기 평탄화식각공정은 CMP 공정으로 실시한다. Cu thin film forming a
도 1b를 참조하면, 전체표면상부에 제2질화막(25) 및 레지스터용 박막(27)인 TaN 및 TiN을 형성한다.
Referring to FIG. 1B, TaN and TiN, which are the
도 1c를 참조하면, 레지스터용 박막(27) 상에 감광막패턴(29)을 형성한다. 이때, 상기 감광막패턴(29)은 레지스터 마스크(미도시)를 이용한 노광 및 현상공정으로 형성한 것이다. Referring to FIG. 1C, a
도 1d를 참조하면, 상기 감광막패턴(29)을 마스크로 하여 상기 레지스터용 박막(27)을 식각하여 레지스터(31)를 형성한다. Referring to FIG. 1D, the resistor
이때, 상기 제2질화막(25)이 소정두께 식각된다. At this time, the
도 1e를 참조하면, 상기 감광막패턴(29)을 제거하고, 상기 레지스터(31) 표면을 포함한 전체표면상부에 소정두께의 제3질화막(33)을 형성한다. Referring to FIG. 1E, the
그 다음, 전체표면상부에 제3산화막(35), 제4질화막(37), 제4산화막(38) 및 제5산화막(39)을 형성한다. 이때, 상기 제3산화막(35)은 FSG ( Fluorinated Silica Glass ) 로 형성한 것이고, 상기 제5산화막(39)은 SRO 로 형성한 것이다. Then, a
도 1f를 참조하면, 금속배선 마스크(미도시) 및 콘택마스크(미도시)를 이용한 사진식각공정으로 상기 제1금속배선(23) 및 레지스터(31)를 노출시키는 제2콘택홀(41) 및 제2금속배선 영역(42)을 형성하고 그 표면에 확산방지막(43)을 형성하고 이들을 매립하는 Cu 박막(45)을 형성한 다음, 평탄화식각공정인 CMP 공정을 실시하여 제2금속배선을 형성한다.Referring to FIG. 1F, a
이때, 상기 제5산화막(39)은 상기 CMP 공정시 모두 제거된다. At this time, all of the
도 2a 내지 도 2d 는 본 발명의 제2실시예에 따른 반도체소자의 레지스터 형성방법을 도시한 단면도이다. 2A through 2D are cross-sectional views illustrating a method of forming a resistor in a semiconductor device according to a second embodiment of the present invention.
도 2a를 참조하면, 반도체기판 상에 제1금속배선(51)을 형성하고 상기 제1금 속배선(51)과 평탄화된 제1산화막(53)을 형성한다. Referring to FIG. 2A, a
전체표면상부에 제1질화막(55) 및 레지스터용 박막(57)을 형성하고 그 상부에 상기 레지스터용 박막(57) 상에 제1감광막패턴(59)을 형성한다. A
이때, 상기 제1감광막패턴(59)은 레지스터 마스크(미도시)를 이용한 노광 및 현상공정으로 형성한 것이다. In this case, the first
도 2b를 참조하면, 상기 제1감광막패턴(63)을 마스크로 하여 레지스터용 박막(57)을 식각하여 레지스터(63)를 형성한 다음, 상기 제1감광막패턴(59)을 제거한다. Referring to FIG. 2B, the resist
이때, 상기 제1질화막(55)은 상부로부터 일정두께 식각된다. At this time, the
도 2c를 참조하면, 전체표면상부에 제2산화막(65)을 형성하고 그 상부에 제2감광막패턴(67)을 형성한다.Referring to FIG. 2C, a
이때, 상기 제2감광막패턴(67)은 제2금속배선 콘택마스크(미도시)를 이용한 노광 및 현상공정으로 형성한 것이다.In this case, the second
도 2d를 참조하면, 상기 제2감광막패턴(67)을 마스크로 하여 상기 제2산화막(65)을 식각함으로써 상기 제1금속배선(51) 및 레지스터(63)를 노출시키는 제2금속배선 콘택홀(69)을 형성하고 이를 매립하는 제2금속배선 콘택플러그(71)를 텅스텐으로 형성한다.Referring to FIG. 2D, the second metal wiring contact hole exposing the
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 레지스터 형성방법은, 금속배선 물질인 Cu 박막을 식각장벽층으로 사용하여 레지스터의 패터닝 공정 을 용이하게 실시할 수 있도록 함으로써 공정을 단순화시키고, 레지스터의 표면에 질화막을 형성하여 레지스터의 특성 열화를 방지할 수 있으며, 레지스터를 금속배선의 표면에 위치시킴으로써 식각공정을 용이하게 실시할 수 있는 효과를 제공한다. As described above, the method for forming a resistor of a semiconductor device according to the present invention simplifies the process by making the patterning process of a resistor easy by using a Cu thin film, which is a metallization material, as an etch barrier layer. By forming a nitride film on the surface of the resistor, it is possible to prevent deterioration of the characteristics of the resistor, and by placing the resistor on the surface of the metal wiring, the etching process can be easily performed.
아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.
Claims (2)
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| KR1020040106941A KR20060068289A (en) | 2004-12-16 | 2004-12-16 | Resistor Formation Method of Semiconductor Device |
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