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KR20060068200A - Gate Forming Method of Semiconductor Device - Google Patents

Gate Forming Method of Semiconductor Device Download PDF

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KR20060068200A
KR20060068200A KR1020040106831A KR20040106831A KR20060068200A KR 20060068200 A KR20060068200 A KR 20060068200A KR 1020040106831 A KR1020040106831 A KR 1020040106831A KR 20040106831 A KR20040106831 A KR 20040106831A KR 20060068200 A KR20060068200 A KR 20060068200A
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film
forming
substrate
layer
gate
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황선환
김동석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 소자의 리프레쉬 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성방법을 개시한다. 개시된 본 발명은, 소자분리막을 구비한 반도체 기판 상에 제1감광막 패턴을 형성하는 단계; 상기 제1감광막 패턴을 사용하여 기판을 리세스하는 단계; 상기 기판 결과물 상에 산화막을 형성하는 단계; 상기 산화막 상에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 제2감광막 패턴을 형성하는 단계; 상기 제2감광막 패턴을 사용하여 폴리실리콘막 및 산화막을 차례로 식각하는 단계; 상기 산화막이 노출되도록 폴리실리콘막에 에치백을 실시하는 단계; 상기 잔류된 산화막이 제거되도록 기판 결과물에 대해 세정 공정을 실시하는 단계; 상기 기판 결과물 상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막을 포함한 기판 결과물 상에 폴리실리콘막과 텅스텐 실리사이드막 및 하드마스크막을 차례로 형성하는 단계; 및 상기 하드마스크막과 텅스텐 실리사이드막 및 폴리실리콘막을 식각하여 게이트를 형성하는 단계;를 포함한다.The present invention discloses a method for forming a gate of a semiconductor device capable of improving the refresh characteristics of the device. The present invention discloses a method of forming a photoresist pattern on a semiconductor substrate having an isolation layer; Recessing a substrate using the first photoresist pattern; Forming an oxide film on the substrate resultant; Forming a polysilicon film on the oxide film; Forming a second photoresist film pattern on the polysilicon film; Sequentially etching the polysilicon layer and the oxide layer using the second photoresist pattern; Etching back the polysilicon film to expose the oxide film; Performing a cleaning process on a substrate resultant to remove the remaining oxide film; Forming a gate oxide layer on the substrate resultant; Sequentially forming a polysilicon film, a tungsten silicide film, and a hard mask film on a substrate resultant including the gate oxide film; And etching the hard mask layer, the tungsten silicide layer, and the polysilicon layer to form a gate.

Description

반도체 소자의 게이트 형성방법{METHOD FOR FORMING GATE OF SEMICONDUCTOR DEVICE}METHOOD FOR FORMING GATE OF SEMICONDUCTOR DEVICE

도 1a 내지 도 1e는 종래 기술에 따른 리세스 채널을 갖는 반도체 소자의 게이트 형성방법을 설명하기 위한 공정별 단면도.1A to 1E are cross-sectional views illustrating processes for forming a gate of a semiconductor device having a recess channel according to the related art.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 공정별 단면도.2A to 2F are cross-sectional views illustrating processes for forming a gate of a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

11 : 반도체 기판 12 : 소자분리막11 semiconductor substrate 12 device isolation film

13 : 제1반사방지막 14 : 제1감광막 패턴13: first antireflection film 14: first photosensitive film pattern

15 : 산화막 16 : 폴리실리콘막15: oxide film 16: polysilicon film

17 : 제2반사방지막 18 : 제2감광막 패턴17: second antireflection film 18: second photosensitive film pattern

19 : 게이트 산화막 20 : 폴리실리콘막19 gate oxide film 20 polysilicon film

21 : 텅스텐 실리사이드막 22 : 하드마스크막21 tungsten silicide film 22 hard mask film

23 : 게이트23: gate

본 발명은 반도체 소자의 게이트 형성방법에 관한 것으로, 보다 상세하게는, 소자의 리프레쉬 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성방법에 관한 것이다.The present invention relates to a method of forming a gate of a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device capable of improving the refresh characteristics of the device.

최근, 고집적 모스펫(MOSFET) 소자의 디자인 룰이 100nm급 레벨로 급격히 감소함에 따라 그에 대응하는 셀 트랜지스터의 채널 길이도 매우 감소되는 실정이다. 또한, 반도체 기판의 도핑 농도 증가로 인한 전계(Electric field) 증가에 따른 접합 누설 전류 증가 현상으로 인해 기존의 플래너(planer) 채널 구조를 갖는 트랜지스터의 구조로는 리프레쉬 특성을 향상시키는 데 그 한계점에 이르렀다. 이에 따라, 유효 채널 길이(effective channel length)를 확보할 수 있는 다양한 형태의 리세스 채널(recess channel)을 갖는 모스펫 소자의 구현에 대한 아이디어 및 실제 공정개발 연구가 활발히 진행되고 있다.Recently, as the design rule of a high-density MOSFET device rapidly decreases to a 100 nm level, the channel length of a corresponding cell transistor is also greatly reduced. In addition, due to the increase in the junction leakage current due to the increase in the electric field due to the increased doping concentration of the semiconductor substrate, the transistor structure having the planar channel structure has reached its limit in improving the refresh characteristics. . Accordingly, studies on the implementation of the MOSFET and the actual process development research have been actively conducted on the implementation of a MOSFET having various types of recess channels capable of securing an effective channel length.

도 1a 내지 도 1e는 종래 기술에 따른 리세스 채널을 갖는 반도체 소자의 게이트 형성방법을 설명하기 위한 공정별 단면도이다.1A to 1E are cross-sectional views illustrating processes for forming a gate of a semiconductor device having a recess channel according to the related art.

도 1a에 도시된 바와 같이, 소자분리막(2)이 형성된 반도체 기판(1) 상에 제1하드마스크막(3)을 형성한 다음, 상기 제1하드마스크막 상에 감광막 패턴(미도시)을 형성한다.As shown in FIG. 1A, a first hard mask layer 3 is formed on the semiconductor substrate 1 on which the device isolation layer 2 is formed, and then a photoresist pattern (not shown) is formed on the first hard mask layer. Form.

도 1b에 도시된 바와 같이, 상기 감광막 패턴을 식각 마스크로 이용하여 제1하드마스크막(3)과 소자분리막(2)에 인접한 기판(1)의 액티브 영역을 리세스하여 단차가 형성된 액티브 영역을 형성한다.As shown in FIG. 1B, using the photoresist pattern as an etching mask, the active region of the substrate 1 adjacent to the first hard mask layer 3 and the isolation layer 2 is recessed to form an active region having a step difference. Form.

도 1c에 도시된 바와 같이, 상기 기판 상에 잔류된 제1하드마스크막(3)을 제 거한 후에 기판 결과물 상에 게이트 산화막(4)을 형성한다. 그 다음, 상기 기판(11) 내에 불순물 이온주입을 실시하여 웰(미도시)영역을 형성한 후에 트랜지스터의 문턱 전압을 조절하기 위해 불순물 이온주입을 실시한다. As shown in FIG. 1C, the gate oxide film 4 is formed on the substrate resultant after removing the first hard mask film 3 remaining on the substrate. After the impurity ion implantation is performed in the substrate 11 to form a well (not shown) region, impurity ion implantation is performed to adjust the threshold voltage of the transistor.

도 1d에 도시된 바와 같이, 상기 게이트 산화막(4)을 포함하는 기판 결과물 상에 도핑된 폴리실리콘막(5)과 텅스텐 실리사이드막(6) 및 제2하드마스크막(7)을 차례로 형성한다.As shown in FIG. 1D, a doped polysilicon film 5, a tungsten silicide film 6, and a second hard mask film 7 are sequentially formed on the substrate product including the gate oxide film 4.

도 1e에 도시된 바와 같이, 상기 제2하드마스크막(7)과 텅스텐 실리사이드막(6) 및 도핑된 폴리실리콘막(5)을 차례로 식각하여 단차가 형성된 액티브 영역에 게이트(8)를 형성한다.As shown in FIG. 1E, the second hard mask layer 7, the tungsten silicide layer 6, and the doped polysilicon layer 5 are sequentially etched to form a gate 8 in the stepped active region. .

그러나, 도 1b에서와 같이, 리세스 채널 구조를 갖는 트랜지스터를 형성하기 위해 기판 리세스시 버티칼 식각(Vertical Etch)을 진행함에 따라 식각된 기판의 가장자리 부분(A)이 샤프한 프로파일을 갖게 된다. 이로 인해, 식각된 기판의 가장자리 부분에 스트레스가 집중됨에 따라 소자의 리프레쉬 특성이 저하되는 문제점이 있다.However, as shown in FIG. 1B, as the vertical etching is performed to form the transistor having the recess channel structure, the edge portion A of the etched substrate has a sharp profile. As a result, as the stress is concentrated on the edge of the etched substrate, there is a problem in that the refresh characteristics of the device are deteriorated.

따라서, 본 발명은 상기와 같은 종래의 제반 문제점들을 해결하기 위해 안출된 것으로서, 소자의 리프레쉬 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a gate of a semiconductor device capable of improving the refresh characteristics of the device, which has been devised to solve the conventional problems as described above.

상기와 같은 목적을 달성하기 위하여, 소자분리막을 구비한 반도체 기판 상 에 제1감광막 패턴을 형성하는 단계; 상기 제1감광막 패턴을 사용하여 기판을 리세스하는 단계; 상기 기판 결과물 상에 산화막을 형성하는 단계; 상기 산화막 상에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 제2감광막 패턴을 형성하는 단계; 상기 제2감광막 패턴을 사용하여 폴리실리콘막 및 산화막을 차례로 식각하는 단계; 상기 산화막이 노출되도록 폴리실리콘막에 에치백을 실시하는 단계; 상기 잔류된 산화막이 제거되도록 기판 결과물에 대해 세정 공정을 실시하는 단계; 상기 기판 결과물 상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막을 포함한 기판 결과물 상에 폴리실리콘막과 텅스텐 실리사이드막 및 하드마스크막을 차례로 형성하는 단계; 및 상기 하드마스크막과 텅스텐 실리사이드막 및 폴리실리콘막을 식각하여 게이트를 형성하는 단계;를 포함한다.In order to achieve the above object, forming a first photosensitive film pattern on a semiconductor substrate having a device isolation film; Recessing a substrate using the first photoresist pattern; Forming an oxide film on the substrate resultant; Forming a polysilicon film on the oxide film; Forming a second photoresist film pattern on the polysilicon film; Sequentially etching the polysilicon layer and the oxide layer using the second photoresist pattern; Etching back the polysilicon film to expose the oxide film; Performing a cleaning process on a substrate resultant to remove the remaining oxide film; Forming a gate oxide layer on the substrate resultant; Sequentially forming a polysilicon film, a tungsten silicide film, and a hard mask film on a substrate resultant including the gate oxide film; And etching the hard mask layer, the tungsten silicide layer, and the polysilicon layer to form a gate.

여기에서, 상기 기판을 150∼500Å의 두께로 리세스 한다.Here, the substrate is recessed to a thickness of 150 to 500 kPa.

상기 산화막을 형성하는 단계는 750∼1000℃의 온도에서 O2 분위기로 진행거나 또는 TCA 가스를 사용하여 수행한다.The forming of the oxide film is performed in an O 2 atmosphere at a temperature of 750 to 1000 ° C. or by using a TCA gas.

상기 폴리실리콘막은 500∼1500Å의 두께로 형성한다.The polysilicon film is formed to a thickness of 500 to 1500 kPa.

상기 에치백을 실시하는 단계는 기판을 600∼1200Å 정도 식각한다.In performing the etch back, the substrate is etched about 600 to 1200 Å.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 공정별 단면도이다. 2A to 2G are cross-sectional views illustrating processes of forming a gate of a semiconductor device according to an exemplary embodiment of the present invention.                     

도 2a에 도시된 바와 같이, 소자분리막(12)을 구비한 반도체 기판(11) 상에 반사방지막(13)을 형성한 후에 상기 반사방지막(13) 상에 제1감광막 패턴(14)을 형성한다.As shown in FIG. 2A, after forming the anti-reflection film 13 on the semiconductor substrate 11 having the device isolation film 12, the first photoresist pattern 14 is formed on the anti-reflection film 13. .

도 2b에 도시된 바와 같이, 상기 제1감광막 패턴(14)을 식각 마스크로 하여 제1반사방지막(13) 및 기판(11)을 리세스 한다. 이때, 기판을 150∼500Å의 두께로 리세스한다. 이어서, 상기 잔류된 제1감광막 패턴(14) 및 제1반사방지막(13)을 제거한다.As shown in FIG. 2B, the first anti-reflection film 13 and the substrate 11 are recessed using the first photoresist pattern 14 as an etch mask. At this time, the substrate is recessed to a thickness of 150 to 500 kPa. Subsequently, the remaining first photoresist layer pattern 14 and the first antireflection layer 13 are removed.

그 다음, 상기 기판 결과물 상에 산화막(15)을 형성한다. 이때, 산화막을 형성하기 위한 산화 공정은 750∼1000℃의 온도에서 O2 분위기로 진행거나 또는 TCA 가스를 사용하여 공정을 진행할 수 있다. 여기에서, 산화막(15)은 후속의 식각 공정에서 기판 표면을 보호하기 식각정지막의 역할을 한다.An oxide film 15 is then formed on the substrate product. At this time, the oxidation process for forming the oxide film may be carried out in an O 2 atmosphere at a temperature of 750 ~ 1000 ℃ or may be carried out using a TCA gas. Here, the oxide film 15 serves as an etch stop film to protect the substrate surface in a subsequent etching process.

도 2c에 도시된 바와 같이, 상기 산화막 상에 폴리실리콘막(16)을 형성한 다음, 상기 폴리실리콘막(16) 상에 제2반사방지막(17) 및 제2감광막 패턴(18)을 차례로 형성한다. 이때, 폴리실리콘막은 500∼1500Å의 두께로 형성한다.As shown in FIG. 2C, a polysilicon film 16 is formed on the oxide film, and then a second anti-reflection film 17 and a second photoresist film pattern 18 are sequentially formed on the polysilicon film 16. do. At this time, the polysilicon film is formed to a thickness of 500 to 1500 kPa.

도 2d에 도시된 바와 같이, 상기 제2감광막 패턴(18)을 식각 마스크로 하여 제2반사방지막(17), 폴리실리콘막(16) 및 산화막(15)을 차례로 식각한다. 이때, 습식식각 공정을 통해 기판 하부와 측면의 산화막을 제거한다. 이어서, 상기 잔류된 제2감광막 패턴(18) 및 제2반사방지막(17)을 제거한다. As shown in FIG. 2D, the second anti-reflection film 17, the polysilicon film 16, and the oxide film 15 are sequentially etched using the second photoresist film pattern 18 as an etching mask. At this time, the oxide film on the lower side and the side of the substrate is removed through a wet etching process. Subsequently, the remaining second photoresist layer pattern 18 and the second antireflection layer 17 are removed.

도 2e에 도시된 바와 같이, 상기 산화막이 노출되도록 폴리실리콘막(16)에 에치백을 실시한다. 이때, 폴리실리콘막(16)에 에치백을 실시할 때에 기판이 함께 식각되는데, 600∼1200Å 정도 식각된다. 그 다음, 상기 기판 결과물에 대해 세정 공정을 실시하여 잔류된 산화막을 제거한다.As shown in FIG. 2E, the polysilicon film 16 is etched back to expose the oxide film. At this time, the substrate is etched together when the polysilicon film 16 is etched back, which is etched at about 600 to 1200 kPa. Next, a cleaning process is performed on the substrate resultant to remove the remaining oxide film.

도 2f에 도시된 바와 같이, 상기 기판 결과물 상에 게이트 산화막(19)을 형성한 후에 상기 게이트 산화막(19) 상에 도핑된 폴리실리콘막(20), 텅스텐 실리사이드막(21) 및 하드마스크막(22)을 차례로 형성한다. 상기 하드마스크막(22), 텅스텐 실리사이드막(21) 및 도핑된 폴리실리콘막(20)을 차례로 식각하여 기판의 액티브 영역 상에 게이트(23)를 형성한다.As shown in FIG. 2F, a polysilicon film 20, a tungsten silicide film 21, and a hard mask film doped on the gate oxide film 19 after the gate oxide film 19 is formed on the substrate product are formed. 22) are formed in sequence. The hard mask layer 22, the tungsten silicide layer 21, and the doped polysilicon layer 20 are sequentially etched to form a gate 23 on the active region of the substrate.

본 발명에선는 감광막 패턴을 형성하기 전에 반사방지막을 형성하였으나, 기판 상에 반사방지막 형성을 생략하고 감광막 패턴을 형성할 수 있다.In the present invention, the anti-reflection film was formed before the photoresist pattern was formed, but the anti-reflection film was omitted on the substrate to form the photoresist pattern.

이상, 본 발명을 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.

이상에서와 같이, 본 발명은 리세스 채널 구조를 갖는 트랜지스터를 형성하기 위해 기판 리세스시 산화막 및 폴리실리콘막을 형성한 후에 식각을 진행함으로써 식각된 기판의 가장자리 부분이 라운딩(Rounding) 된 프로파일을 얻을 수 있다. 이로 인해, 식각된 기판의 가장자리 부분에 스트레스가 집중되는 방지하여 소자의 리프레쉬 특성을 향상시킬 수 있다.As described above, according to the present invention, by forming an oxide film and a polysilicon film during substrate recess to form a transistor having a recess channel structure, etching is performed to obtain a rounded profile of the edge of the etched substrate. have. As a result, stress may be prevented from being concentrated on the edge portion of the etched substrate, thereby improving refresh characteristics of the device.

Claims (5)

소자분리막을 구비한 반도체 기판 상에 제1감광막 패턴을 형성하는 단계;Forming a first photoresist pattern on a semiconductor substrate having an isolation layer; 상기 제1감광막 패턴을 사용하여 기판을 리세스하는 단계;Recessing a substrate using the first photoresist pattern; 상기 기판 결과물 상에 산화막을 형성하는 단계;Forming an oxide film on the substrate resultant; 상기 산화막 상에 폴리실리콘막을 형성하는 단계;Forming a polysilicon film on the oxide film; 상기 폴리실리콘막 상에 제2감광막 패턴을 형성하는 단계;Forming a second photoresist film pattern on the polysilicon film; 상기 제2감광막 패턴을 사용하여 폴리실리콘막 및 산화막을 차례로 식각하는 단계;Sequentially etching the polysilicon layer and the oxide layer using the second photoresist pattern; 상기 산화막이 노출되도록 폴리실리콘막에 에치백을 실시하는 단계;Etching back the polysilicon film to expose the oxide film; 상기 잔류된 산화막이 제거되도록 기판 결과물에 대해 세정 공정을 실시하는 단계;Performing a cleaning process on a substrate resultant to remove the remaining oxide film; 상기 기판 결과물 상에 게이트 산화막을 형성하는 단계;Forming a gate oxide layer on the substrate resultant; 상기 게이트 산화막을 포함한 기판 결과물 상에 폴리실리콘막과 텅스텐 실리사이드막 및 하드마스크막을 차례로 형성하는 단계; 및Sequentially forming a polysilicon film, a tungsten silicide film, and a hard mask film on a substrate resultant including the gate oxide film; And 상기 하드마스크막과 텅스텐 실리사이드막 및 폴리실리콘막을 식각하여 게이트를 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.And forming a gate by etching the hard mask layer, the tungsten silicide layer, and the polysilicon layer. 제 1 항에 있어서, 상기 기판을 150∼500Å의 두께로 리세스 하는 것을 특징 으로 하는 반도체 소자의 게이트 형성방법.The method of forming a gate of a semiconductor device according to claim 1, wherein the substrate is recessed to a thickness of 150 to 500 kV. 제 1 항에 있어서, 상기 산화막을 형성하는 단계는 750∼1000℃의 온도에서 O2 분위기로 진행거나 또는 TCA 가스를 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 1, wherein the forming of the oxide film is performed in an O 2 atmosphere at a temperature of 750 to 1000 ° C. or by using a TCA gas. 제 1 항에 있어서, 상기 폴리실리콘막은 500∼1500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of forming a gate of a semiconductor device according to claim 1, wherein said polysilicon film is formed to a thickness of 500-1500 GPa. 제 1 항에 있어서, 상기 에치백을 실시하는 단계는 기판을 600∼1200Å 정도 식각하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 1, wherein the etching back is performed by etching the substrate about 600 to 1200 Å.
KR1020040106831A 2004-12-16 2004-12-16 Gate Forming Method of Semiconductor Device Withdrawn KR20060068200A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100780629B1 (en) * 2006-11-15 2007-11-30 주식회사 하이닉스반도체 Method of manufacturing semiconductor device having recess gate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100780629B1 (en) * 2006-11-15 2007-11-30 주식회사 하이닉스반도체 Method of manufacturing semiconductor device having recess gate
US7575974B2 (en) 2006-11-15 2009-08-18 Hynix Semiconductor Inc. Method for fabricating semiconductor device including recess gate

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