KR20060068993A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

A semiconductor memory device and a method of manufacturing the same are provided. The semiconductor memory device is disposed on a semiconductor substrate, and includes a first interlayer insulating layer including a lower electrode contact, a cylindrical lower electrode positioned on a lower electrode contact, and a portion of the cylindrical lower electrode disposed on the first interlayer insulating layer. Includes a second interlayer insulating film.

Double Layer, Cylindrical Capacitors, Bit Line

Description

Semiconductor memory device and method for manufacturing the same {Semiconductor memory device and method for fabricating the same}

1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

2 to 8 are diagrams sequentially illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

100: semiconductor substrate 102: device isolation film

110: gate electrode 112: first interlayer insulating film

114: first etch stop film 116: second interlayer insulating film

118: second etch stop layer 120: lower electrode contact hole

122: lower electrode contact 124: first bit line contact hole

126: first bit line contact 128: sacrificial insulating film

129 mold 130: conductive film for lower electrode

132: sacrificial film 134: lower electrode

136: dielectric film 138: upper electrode

140: cylindrical capacitor 142: third interlayer insulating film

144: second bit line contact hole 146: second bit line contact                 

148: wiring contact hole 150: wiring contact

152: bit line 154: wiring

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to an etching process for forming a bit line contact hole, which can prevent a capacitor from falling due to an increase in the height of a capacitor in a semiconductor memory device having a CUB structure. The present invention relates to a semiconductor memory device and a method of manufacturing the same that can be more effectively performed.

Memory (eg, DRAM) devices have a rapidly decreasing area of unit cells as the degree of integration increases. Accordingly, the area of the capacitor to be formed in the memory device is also reduced. However, even if the area where the capacitor is to be formed is reduced, the minimum capacitance that determines the storage capacity of the memory device must be maintained. Therefore, the capacitance of the capacitor must be increased within the limited area.

As a method of increasing the capacitance of the capacitor, there is a method of using a material having a high dielectric constant as the dielectric film, a method of reducing the thickness of the dielectric, or a method of increasing the surface area of the electrode.

Among these, when a material having a high dielectric constant is used as the dielectric film, a metal-insulator-metal (MIM) capacitor using a metal instead of polycrystalline silicon, which is used for a conventional capacitor electrode, is used. In order to increase the surface area of the electrode, a method of increasing the height of the capacitor is used.

However, when the height of the capacitor is increased in a limited area, there is a problem in that the yield of the semiconductor device decreases because the capacitor collapses.

In addition, in the memory device having a capacitor under bitline (CUB) structure in which a capacitor is formed under the bit line, the height of the bit line contact for forming the bit line also increases as the height of the capacitor increases. In the process of forming the bit line contact, there is a problem that it is difficult to form the same bit line contact hole in the upper CD (Critical Dimension) and the lower CD during the etching process for forming the bit line contact hole.

In addition, during the etching process for forming the bit line contact hole, a contact hole connecting the upper electrode of the capacitor and the wiring is also formed. However, since the difference in the depth of the bit line contact hole and the contact hole connecting the wiring is large, there is a problem that the upper electrode may be etched while forming the bit line contact hole and the wiring contact hole.

An object of the present invention is to provide a semiconductor memory device and a method of manufacturing the same, which can prevent the capacitor from collapsing when the semiconductor memory device is formed and can more effectively perform an etching process for forming a bit line contact hole.

Another object of the present invention is to provide such a semiconductor memory device.                         

The technical problem to be achieved by the present invention is not limited to the above-mentioned problem, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a semiconductor memory device according to an embodiment of the present invention is disposed on a semiconductor substrate, and includes a first interlayer insulating layer including a lower electrode contact, a cylindrical lower electrode and a lower electrode contact disposed on a lower electrode contact. And a second interlayer insulating film positioned on the first interlayer insulating film and surrounding a portion of the cylindrical lower electrode.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor memory device, the method including: (a) stacking a first interlayer insulating film and a second interlayer insulating film on a semiconductor substrate on which a gate electrode is formed; Partially etching the resultant to form a lower electrode contact and a first bit line contact connected to the semiconductor substrate, (c) depositing a sacrificial insulating film on the resultant and partially removing the sacrificial insulating film, the second interlayer insulating film, and a portion of the lower electrode contact; Etching to form a mold exposing the first interlayer insulating film, (d) forming a lower electrode along the mold and selectively removing the sacrificial insulating film constituting the mold; and (e) lower electrode and second interlayer insulating film. And conformally forming a dielectric film and an upper electrode to complete the cylindrical capacitor.

Specific details of other embodiments are included in the detailed description and the drawings.                     

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, a device isolation layer 102 is formed on the semiconductor substrate 100 to separate the active region and the field region, and the gate electrodes 110 are positioned on the semiconductor substrate 100. The source and drain regions 111 are positioned in the semiconductor substrate 100 between the gate electrodes 110.

An interlayer insulating layer and an etch stop layer formed of a double layer are positioned on the semiconductor substrate 100 on which the gate electrodes 110 are formed. In detail, the first interlayer insulating layer 112, the first etch stop layer 114, the second interlayer insulating layer 116, and the second interlayer insulating layer 116 are sequentially formed on the semiconductor substrate 100.

A lower electrode contact 122 is formed in the first interlayer insulating layer 112 and the first etch stop layer 114 to be electrically connected to the source and drain regions 111 of the semiconductor substrate 100. A first bit line contact 126 is formed in the interlayer insulating layer and the etch stop layer formed of the double layer to be electrically connected to the other source and drain regions 111 of the semiconductor substrate 100. Accordingly, the first bit line contact 126 is formed to be higher than the lower electrode contact 122 by a predetermined height.

In addition, a cylindrical capacitor 140 electrically connected to the lower electrode contact 122 is positioned on the lower electrode contact 122. The cylindrical capacitor 140 includes a lower electrode 134, a dielectric layer 136, and an upper electrode 138. In the cylindrical capacitor 140, the dielectric film 136 and the upper electrode 138 are conformally formed along the inside and the outside of the lower electrode 134 to increase the capacitance of the capacitor. A portion of the dielectric layer 136 and the upper electrode 138 are positioned on the second etch stop layer 118. In addition, the cylindrical capacitor 140 is a metal-insulator-metal (MIM) capacitor including a dielectric film 136 having a high dielectric constant, a lower electrode 134 and an upper electrode 138 formed of a metal material.

A portion of the lower portion of the cylindrical capacitor 140 is positioned in the second interlayer insulating layer 116 and the second etch stop layer 118 to support the cylindrical capacitor 140 so that the capacitor collapses as the height of the capacitor increases. To prevent them.

The third interlayer insulating layer 142 is positioned on the cylindrical capacitor 140 and the second etch stop layer 118. The second bit line contact 146 and the wiring contact 150 are positioned in the third interlayer insulating layer 142. In this case, the second bit line contact 144 is connected to the first bit line contact 126 that is raised from the lower electrode contact 122. The wiring contact 150 is connected to the upper electrode 138 positioned on the second etch stop layer 118. Unlike the related art, the second bit line contact 146 and the wiring contact 150 may have a level difference between the dielectric layer 136 and the upper electrode 138 positioned on the second etch stop layer 118. do.

The bit line 152 and the wiring 154 made of a metal material are positioned on the third interlayer insulating layer 142 including the second bit line contact 146 and the wiring contact 150. The bit line 152 is electrically connected to the source and drain regions 111 of the semiconductor substrate 100 by the second bit line contact 146 and the first bit line contact 126. The wiring 154 is connected to the upper electrode 138 of the cylindrical capacitor 140 by the wiring contact 150.

Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 2 to 8.

2 through 8 are diagrams sequentially illustrating a method of manufacturing a semiconductor memory in accordance with an embodiment of the present invention.

As shown in FIG. 2, the gate electrodes 110 are formed on the semiconductor substrate 100 in which the active region and the field region are separated by the device isolation layer 102 using a general method. The source and drain regions 111 are formed by implanting ions into the semiconductor substrate 100 between the gate electrodes 110.

Next, the interlayer insulating layer and the etch stop layer are sequentially stacked and repeatedly formed on the semiconductor substrate 100 on which the gate electrodes 110 are formed, thereby forming the interlayer insulating layer and the etch stop layer as a double layer. In an exemplary embodiment, the first interlayer insulating layer 112, the first etch stop layer 114, the second interlayer insulating layer 116, and the second etch stop layer 118 are sequentially formed on the semiconductor substrate 100. It is formed by vapor deposition. In this case, the second interlayer insulating layer 116 and the second etch stop layer 118 may serve to prevent the capacitor from falling down in a cylindrical shape. In addition, a portion of the bit line contact may be formed as high as the height at which the second interlayer insulating layer 116 and the second etch stop layer 118 are formed, thereby reducing the etching depth of the bit line contact to be formed after the formation of the capacitor. .

In this case, the interlayer insulating films 112 and 116 are made of silicon oxide (SiO ₂ ), which is a commonly used insulating material. The etch stop layers 114 and 118 are made of SiON or SiN.

Next, as shown in FIG. 3, an interlayer insulating layer in which a lower electrode contact 122 and a first bit line contact 126 electrically connected to the source and drain regions 111 of the semiconductor substrate 100 are formed as a double layer, and It forms in an etch stop film.

The method of forming the lower electrode contact 122 and the first bit line contact 126 is formed in a double layer using an etching mask that defines an area in which the lower electrode contact 122 and the first bit line contact 126 are to be formed. A portion of the interlayer insulating layer and the etch stop layer are sequentially etched until the source and drain regions 111 formed on the semiconductor substrate 100 are exposed. When the interlayer insulating layer and the etch stop layer are partially etched as described above, the lower electrode contact hole 120 and the first bit line contact hole 124 are formed.                     

The barrier metal film is deposited in the lower electrode contact hole 120 and the first bit line contact hole 124 formed as described above, and then filled with a metal material therein, followed by chemical mechanical polishing (CMP) or etch-back. The lower electrode contact 122 and the first bit line contact 126 are formed.

At this time, the barrier metal film is a material such as TiN or Ti + TiN is used to improve the contact of the contact, and to prevent the diffusion of impurities during metal material deposition. The metal material filled in the lower electrode contact hole 120 and the first bit line contact hole 124 may be W, Ti, or TiN, or a combination thereof.

Next, as shown in FIG. 4, a mold 129 for forming the cylindrical capacitor 140 is formed. The method of forming the mold 129 may include a sacrificial insulating layer 128 for forming a mold 129 on an interlayer insulating layer and an etch stop layer including a lower electrode contact 122 and a first bit line contact 126. Deposit. In this case, a silicon oxide film may be used as the sacrificial insulating layer 128, and the height of the capacitor to be formed by a subsequent process may be determined according to the height of the sacrificial insulating layer 128.

After the sacrificial insulating layer 128 is deposited, dry etching is performed using an appropriate etching gas until an upper portion of the lower electrode contact 122 formed in the first interlayer insulating layer 112 is exposed using an etching mask such as a photoresist pattern. As a result, the mold 129 is formed. In detail, the mold 129 is formed by partially etching the sacrificial insulating layer 128, the second etching blocking layer 118, the second interlayer insulating layer 116, and the first etching blocking layer 114. At this time, a portion of the lower electrode contact 122 formed in the second interlayer insulating layer 116 and the second etch stop layer 118 is also etched.

As an etching method for forming the mold 129, the lower electrode contact 122 is exposed by first etching the sacrificial insulating layer 128 to the second etch stop layer 118 using an etching mask. Next, the second etch stop layer 118, the second interlayer insulating layer 116, and the first etch stop layer 114 are etched, and then the lower electrode contact 122 made of a metal material is etched into the first interlayer insulating layer 112. It is etched until it is exposed to complete the mold 129 for forming the capacitor.

As another etching method for forming the mold 129, the sacrificial insulating layer 128 is etched to expose the lower electrode contact 122, and then the lower electrode contact 122 made of a metal material is first formed into the first interlayer insulating layer 112. The upper portion is etched, and the mold 129 for forming the capacitor is completed by etching the second etch stop layer 118, the second interlayer insulating layer 116, and the first etch stop layer 114.

When the mold 129 is formed in the above manner, the sacrificial insulating film 128, the second etch stop film 118, the second interlayer insulating film 116, and the first etch stop film 114 are formed of CHF ₃ or CF. _A fluorine-based etching gas such as ₄ is etched by using different etching selectivity. In addition, when the material of the lower electrode contact 122 is tungsten (W), the lower electrode contact 122 may be etched using BCl ₃ + Cl ₂ , CF ₄ + Cl ₂ + O _2, or SF ₆ as an etching gas. .

In addition, another etching method for forming the mold 129 may include a sacrificial insulating film 128, a second etching blocking film 118, a second interlayer insulating film 116, and a first etching stop using an appropriate etching gas. A portion of the film 114 and the lower electrode contact 122 are simultaneously etched to complete the mold 129. In this case, as the etching gas, the gases of CHF ₄ , CF ₄ , BCl ₃ + Cl ₂ , CF ₄ + Cl ₂ + O _2, and SF ₆ may be mixed and etched, or the amount of Ar in the etching gas may be added to increase the physical etch specific gravity. Etch it up.

In addition, when the mold 129 is formed, only the sacrificial insulating layer 128, the second etch stop layer 118, and the second interlayer insulating layer 116 may be etched to form the mold 129. In this case, since the lower electrode contact 122 is not etched, a mold 129 having a bend formed therein is formed. The mold 129 may be formed only when there is no deterioration in the step coverage of the dielectric layer 136 in a subsequent process.

After the process is completed, a step is formed between the lower electrode contact 122 and the first bit line contact 126 by the thickness of the second interlayer insulating layer 116 and the second etch stop layer 118.

Next, as shown in FIG. 5, the lower electrode conductive film 130 is conformally deposited along the mold 129 formed above. The lower electrode conductive layer 130 is a metal layer, and the lower portion thereof is electrically connected to the lower electrode contact 122. At this time, the lower electrode conductive film 130 is formed of TiN, TaN, WN, Ru, Pt, Ir, RuO ₂ or IrO ₂ or a combination thereof.

After depositing the conductive film 130 for the lower electrode as described above, a sacrificial film 132 filling the inside of the conductive film 130 for the lower electrode is formed. In this case, the sacrificial layer 132 is formed to perform a planarization process for separating the lower electrode. As the sacrificial layer 132, an insulating material such as silicon oxide, a photosensitive layer, or the like may be used. As the planarization process, a chemical mechanical polishing or etch back process is performed until the top of the mold 129 is exposed. After this is done, the sacrificial layer 132 remains inside the separated lower electrode conductive layer 130.

Next, after the sacrificial layer 132 and the sacrificial insulating layer 128 are wet-etched and removed, the cylindrical lower electrode 134 as shown in FIG. 6 is completed. In the wet etching process of removing the sacrificial layer 132 and the sacrificial insulating layer 128, the etchant includes a LAL solution or an HF solution. The wet etching process of removing the sacrificial layer 132 and the sacrificial insulating layer 128 is prevented by the second etch stop layer 118 formed under the sacrificial insulating layer 128.

Since a portion of the lower lower electrode 134 completed as described above is positioned in the second etch stop layer 118 and the second interlayer insulating layer 116, the lower side surface of the lower electrode 134 may be the second etch stop layer 118 and the second etch stop layer 118. It is supported by the second interlayer insulating film 116. Therefore, the height of the lower electrode 134 is increased to prevent the capacitor from falling down.

Subsequently, as illustrated in FIG. 7, the dielectric film 136 and the upper electrode 138 are conformally deposited along the lower electrode 134 to complete the cylindrical capacitor 140. In this case, the dielectric layer 136 and the upper electrode 138 are deposited to have a predetermined thickness inside and outside the lower electrode 134, thereby increasing the area of the capacitor. A portion of the dielectric layer 136 and the upper electrode 138 are deposited on the second etch stop layer 118. In this case, the dielectric layer 136 is formed of a material having a high dielectric constant, and the upper electrode 138 is formed of the same metal material as the lower electrode 134 and formed of a MIM capacitor.

At this time, the dielectric layer 136 is made of a high-k material which is one selected from HfO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , La ₂ O _3, ZrO _2, or a combination thereof. The upper electrode 138 is made of any one of TiN, TaN, WN, Ru, Pt, Ir, RuO ₂ or IrO ₂ or a combination thereof.

The cylindrical capacitor 140 thus formed has a different etching depth between a portion of the second bit line contact (see 146 in FIG. 8) and the wiring contact (see 150 in FIG. 8) formed by a subsequent process. Unlike the conventional concave capacitor, which has a thicker thickness, the upper electrode 138 may have a thinner thickness. A portion of the second bit line contact (see 146 in FIG. 8) and the wiring contact (see 150 in FIG. 8) formed by the subsequent process are as thick as the thickness of the dielectric film 136 and the upper electrode 138 of the cylindrical capacitor. Because of the difference, when over-etching is concerned when forming the wiring contact (see 150 of FIG. 8), the cylindrical capacitor 140 may be completed by increasing only the horizontal thickness without increasing the side thickness of the upper electrode 138.

After completing the cylindrical capacitor 140 in this manner, the upper portion of the first bit line contact 126 to form a second bit line contact (see 146 in FIG. 8) connected to the first bit line contact 126. The predetermined region of the cylindrical capacitor located at is etched. Accordingly, an upper portion of the first bit line contact 126 included in the interlayer insulating layer and the etch stop layer formed of the double layer is exposed.

As such, the upper portion of the first bit line contact 126 is exposed, and a third interlayer insulating layer 142 filling the cylindrical capacitor 140 is formed as shown in FIG. 8. In this case, O ₃ TEOS (SOG), TOSZ, and Sub-Atmospheric (CVD) -CVD, which are materials having excellent gap filling, may be used as the third interlayer insulating layer 142.

After the third interlayer insulating layer 142 is formed on the cylindrical capacitor 140, the second bit line contact hole 144 is partially etched by partially etching the third interlayer insulating layer 142 using an etching mask such as a photoresist pattern. The wiring contact hole 148 is formed at the same time. In this case, the second bit line contact hole 144 is connected to the first bit line contact hole 124 formed below, and the wiring contact hole 148 is connected to the upper electrode 138 of the capacitor.

As such, when the second bit line contact hole 144 is formed, the first bit line contact 126 is formed at the lower portion of the second bit line contact hole 144 to form an etch depth. Decreases. Therefore, in the related art, the upper CD and the lower CD of the second bit line contact hole may be kept the same, unlike the lower CD (critical dimension) reduced when the second bit line contact hole 144 is formed.

The etch depth of the second bit line contact hole 144 and the etch depth of the wiring contact hole 148 are generated by the thickness of the upper electrode 138 and the dielectric layer 136 of the capacitor. Therefore, in the related art, the height difference between the second bit line contact hole 144 and the wiring contact hole 148 is large so that the horizontal thickness of the upper electrode 138 of the capacitor is sufficiently thick, unlike the upper electrode 138 of the capacitor. Lower surfaces of the upper electrode 138 may be prevented from being overetched.

After forming the second bit line contact hole 144 and the wiring contact hole 148 in this manner, a metal material is deposited in the second bit line contact hole 144 and the wiring contact hole 148 to form the second bit. The line contact 146 and the wiring contact 150 are completed. In this case, the second bit line contact 146 and the wiring contact 150 may first deposit a barrier metal film and then a metal material. In this case, the barrier metal film is formed of a TiN or Ti + TiN material for increasing contact of the contact and preventing diffusion of the metal material. And the metal material is W, Ti or TiN or a combination thereof is used.

As described above, after depositing the metal material filling the second bit line contact hole 144 and the wiring contact hole 148, the planarization process is performed. Then, by depositing and patterning Cu or Al for forming the bit line 152 and the wiring 154, the bit line 152 and the wiring 154 are formed as shown in FIG.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

 As described above, according to the semiconductor memory device and a method of manufacturing the same, a portion of the bit line contact may be formed higher than the height of the lower electrode contact by forming the interlayer insulating film and the etch stop layer as a double layer. Therefore, since the height of the remaining bit line contacts to be formed later is reduced, the etching process for forming the bit line contacts can be more effectively performed.

In addition, since a portion of the interlayer insulating layer and the etch stop layer formed of the double layer support the cylindrical capacitor, the capacitor may be prevented from falling due to the height increase.

In addition, by forming a dielectric film and an upper electrode inside and outside the lower electrode, a step difference between a portion of the bit line contact and the wiring contact formed after the capacitor is formed may be reduced, thereby preventing overetching of the upper electrode when forming the wiring contact. .

Claims (15)

A first interlayer insulating layer on the semiconductor substrate and including a lower electrode contact; A cylindrical lower electrode positioned on the lower electrode contact; And And a second interlayer insulating layer disposed on the first interlayer insulating layer and surrounding a portion of the cylindrical lower electrode. The method of claim 1, And a dielectric film and an upper electrode conformally formed along the cylindrical lower electrode and the second interlayer insulating film. The method of claim 2, A first bit line contact positioned in the first interlayer insulating layer and the second interlayer insulating layer and connected to the semiconductor substrate, and a third bit interlayer insulating layer located on the resultant and connected to the first bit line contact; A semiconductor memory device manufacturing method further comprising a two bit line contact. The method of claim 3, wherein And a wiring contact disposed in the third interlayer insulating layer and connected to the upper electrode. (a) depositing a first interlayer insulating film and a second interlayer insulating film on a semiconductor substrate on which the gate electrode is formed; (b) partially etching the resultant to form a lower electrode contact and a first bit line contact connected to the semiconductor substrate; (c) depositing a sacrificial insulating film on the resultant, and partially etching the sacrificial insulating film, the second interlayer insulating film and the lower electrode contact to form a mold exposing the first interlayer insulating film; (d) forming a lower electrode along the mold and selectively removing the sacrificial insulating film constituting the mold; And (e) forming a dielectric film and an upper electrode conformally along the lower electrode and the second interlayer insulating film to complete a cylindrical capacitor. The method of claim 5, The step (a) further comprises the step of forming a first etch stop layer on the first interlayer insulating film and a second etch stop layer on the second interlayer insulating film. The method of claim 6, Stacking an insulating film on the cylindrical capacitor and forming a second bit line contact connected to the first bit line contact and a wiring contact connected to the upper electrode;  The method of claim 6, The first etch stop layer and the second etch stop layer are formed by depositing SiON or SiN. The method of claim 5, The lower electrode contact, the first bit line contact, and the second bit line contact are formed by depositing W, Ti, TiN, or a combination thereof. The method of claim 5, In the step (c), the sacrificial insulating film and the second interlayer insulating film are sequentially partially etched until the first interlayer insulating film is exposed, and the lower electrode contact is partially etched until the first interlayer insulating film is exposed. A semiconductor memory device manufacturing method comprising the steps of. The method of claim 5, Step (c) partially etching the sacrificial insulating film until the lower electrode contact is exposed, etching the lower electrode contact until the first interlayer insulating film is exposed, and the second interlayer insulating film is And partially etching the first interlayer insulating film until the first interlayer insulating film is exposed. The method of claim 10 or 11, And etching the second interlayer insulating layer using CHF ₄ or CF ₄ as an etching gas. The method of claim 10 or 11, Etching the portion of the lower electrode contact using BCl ₃ + Cl ₂ , CF ₄ + Cl ₂ + O ₂ or SF ₆ . The method of claim 5, In the step (c), the portion of the sacrificial insulating film, the second interlayer insulating film and the lower electrode contact are simultaneously partially etched. The method of claim 14, A portion of the second interlayer insulating layer and the lower electrode contact may include an etching gas having Ar added to a combination of CHF ₄ , CF ₄ , BCl ₃ + Cl ₂ , CF ₄ + Cl ₂ + O _2, and SF ₆ , or a combination thereof. A method of manufacturing a semiconductor memory device by etching.

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