KR20060065467A - Method and apparatus for providing dual variable clock for low power wireless packet communication - Google Patents

Abstract

The present invention relates to wireless packet communication, and more particularly, to a method and apparatus for enabling low power communication by providing a driving clock optimized for a physical layer execution unit and a higher layer execution unit of a physical layer in a wireless packet communication system. It is about. According to the present invention, a method for providing a dual variable clock in a wireless packet communication system logically divided into a lower performer performing a function of a physical (PHY) layer and a higher performer performing a higher layer of the physical layer. This is provided. The method includes: measuring a real data transmission / reception rate at a predetermined period, providing a first clock frequency (F ₁ ) based on the measured value, and providing a first clock to the higher performing unit; Determining a transmission mode of the wireless packet communication system, identifying a predetermined second clock frequency F ₂ corresponding to the determined transmission mode, and providing a second clock to the lower performing unit; Include.

Wireless packet communication system, low power, dual variable clock

Description

Method and apparatus for providing variable dual clocks for low-power wireless packet communication

1 is a block diagram of a wireless packet communication system to which a dual variable clock providing apparatus according to the present invention is applied.

Figure 2 is a block diagram showing the detailed structure of a dual variable clock providing apparatus according to an embodiment of the present invention.

The present invention relates to wireless packet communication, and more particularly, to a method and apparatus for enabling low power communication by providing a dual variable clock optimized for a physical layer execution unit and an upper layer execution unit of a physical layer in a wireless packet communication system. It is about.

Power consumption in CMOS (Complimentary Metal Oxide Silicon) digital circuits is mainly due to the charge / discharge of the load capacitor. In this case, since power consumption is linearly proportional to the driving clock frequency, it is desirable to optimize the driving clock frequency in order to reduce power consumption. In this regard, low-power processors (Transmeta's Crusoe, IBM's 405LP, Intel's Xscale, and the latest mobile Pentium) are available with an optimal drive voltage for the optimal drive clock frequency, allowing for variable drive voltage and drive frequency.

Prior art in the art includes techniques for on-demand circuitry (ASIC) including clock control that can dynamically change frequency in accordance with the data processing requirements of a mobile device (US 6,564,329 B1), when predetermined applications are executed or in advance. Technology related to the control system for changing the CPU clock speed in accordance with the processing request of the device when servicing the determined interrupt (Korean Patent Publication No. 10-2001-0099880), CPU clock speed according to the operating mode of the system operating system A technique for controlling a CPU clock speed to reduce power consumption by varying the power consumption (Korean Patent Publication No. 10-2004-0076678), a Mac layer processing structure capable of power management utilizing the characteristics of a battery, and characteristics of a battery A study on the bus structure that enables power management (Communications, 2002. ICC 2002. IEEE International Conference on Volume: 2 Pages: 669-674 vol. 2) and studies aiming to achieve low power (Solid-State Circuits, IEEE Journal of Volume: 38, Pages: 2001-2009).

Wireless packet communication devices according to wireless access protocol standards such as Bluetooth (IEEE 802.15.1), WLAN (IEEE 802.11a / b / g), WiMAX (IEEE 802.16d / e), etc. In the case of 8 transmission modes of 6, 9, 12, 18, 24, 36, 48 and 54 Mbps) and packet retransmission function are supported.

In general, a wireless packet communication apparatus supporting multiple transmission modes operates in a transmission mode suitable for a propagation environment among a plurality of transmission modes defined in protocols defined in each standard by analyzing headers of received packets. For example, when the radio wave environment becomes poor, the wireless communication device operates by switching to a low transmission rate transmission mode. In this case, the clock frequency provided to ensure a high transmission rate is inefficient in terms of power consumption for a transmission mode with a low transmission rate.

On the other hand, when the other party does not receive the previously transmitted packet, the radio communication apparatus retransmits the packet. In this case, the actual data rate may be lower than the data rate expected in the transmission mode. For example, assuming that an IEEE 802.11g wireless communication device supporting eight transmission modes of 6, 9, 12, 18, 24, 36, 48, and 54 Mbps operates in a transmission mode of 18 Mbps. The transmission rate is 13 Mbps. In this case, there is a problem in that power is unnecessarily consumed by using a driving clock frequency optimized only for a transmission mode of 18 Mbps.

Accordingly, an object of the present invention is to provide a dual variable clock providing method and apparatus for providing a variable clock optimized for each of the transmission mode and the actual data rate for low power operation of the wireless packet communication system. .

Another object of the present invention is to provide a variable clock optimized for a transmission mode to a physical layer function performing unit and a variable clock optimized for an actual data rate to a higher layer performing unit of a physical layer for low power driving of a wireless packet communication system. To provide a dual variable clock providing method and apparatus.

According to an aspect of the present invention, a dual variable clock is provided in a wireless packet communication system logically divided into a lower performer performing a function of a physical (PHY) layer and a higher performer performing a higher layer of the physical layer. A method is provided for doing this. The method includes: measuring a real data transmission / reception rate at a predetermined period, providing a first clock frequency (F ₁ ) based on the measured value, and providing a first clock to the higher performing unit; Determining a transmission mode of the wireless packet communication system, identifying a predetermined second clock frequency F ₂ corresponding to the determined transmission mode, and providing a second clock to the lower performing unit; Include.

According to another aspect of the present invention, an apparatus for providing a dual variable clock in a wireless packet communication system is provided. The wireless packet communication system is logically divided into a lower performing unit performing a function of a physical (PHY) layer and an upper performing unit performing an upper layer of the physical layer, and the dual variable clock providing apparatus is actually divided at a predetermined period. First clock providing means for measuring a data transmission / reception rate, setting a first clock frequency (F ₁ ) based on the measured value, and providing the first clock to the higher performing unit, and transmission of the wireless packet communication system determining a mode, and comprises said second clock selection corresponding to the determined transmission mode (F ₂₎ a second clock providing means for identifying the frequency to provide the second clock on the sub-performing unit.

Hereinafter, with reference to the embodiments shown in the accompanying drawings, the present invention will be described in detail by way of example. However, the following detailed description is provided for illustrative purposes only and should not be construed as limiting the inventive concept to any particular physical configuration.

1 is a block diagram of a wireless packet communication system to which a dual variable clock providing apparatus according to the present invention is applied. As shown in FIG. 1, a wireless packet communication system includes a first unit 110 performing an operation related to an upper layer (eg, a media access control (MAC) layer) of a physical layer (PHY), and retransmission. The second unit 120 performs an operation related to a physical (PHY) layer including a function, and a variable clock providing apparatus 130 suitable for each of the first unit and the second unit.

According to the present invention, the first unit 110 performs the operation according to the clock optimized for the actual data rate provided by the first clock provider 132, and the second unit 120 is the second clock provider The operation will be performed according to a clock optimized for the transmission mode provided by 134.

When the retransmission operation by the second unit 120 does not receive an ACK packet indicating that a packet previously transmitted from the counterpart communication device is normally received within a predetermined time period, or receives a NAK packet indicating that the reception process of the other party has failed. Is performed on. The receiving communication device includes a process of analyzing the received MAC packet header, verifying the integrity of the MAC packet header, and verifying data integrity (CRC check). A NAK packet is sent to the sender's communication device indicating the failure.

The variable clock providing apparatus 130 is connected to the first unit 110 and the second unit 20, and the first unit 110 whose computing power required for communication depends on the actual transfer rate is optimized for the actual transfer rate. The second unit 120 provides a first clock, and a second clock optimized for the transmission mode is provided to the second unit 120 whose computing power required for communication depends on the transmission mode.

2 is a block diagram showing the detailed structure of the variable clock providing apparatus 130 according to an embodiment of the present invention. As shown, the variable clock providing apparatus 130 periodically calculates an actual transmission / reception rate of a packet, calculates a first clock frequency that is optimal for the actual transmission / reception rate, and provides the first clock providing unit to the first unit 110. 132 and a second clock providing unit 134 for providing the second unit 120 with an optimal second clock determined experimentally according to the transmission mode.

Specifically, the first clock provider 132 may include a transmission counter indicating the number of transmission data read by the transmission memory 202 and the second unit 120 in which data to be transmitted by the first unit 110 is stored. 208, a reception memory 210 in which data received by the second unit 120 is stored, a reception counter 216 indicating the number of received data processed by the first unit 110, and a transmission and reception The first clock setting unit 218 sets the first clock using the values of the counters 208 and 210.

Here, the data start position and end position stored in the transmission memory 202 are referred to by the transmission data start pointer (T_start_pointer, 204) and the transmission data end pointer (T_last_pointer, 206), respectively. The start position and end position are referenced by the received data start pointer R_start_pointer 212 and the received data end pointer R_last_pointer 214, respectively.

Here, the T_last_pointer 206 is managed by the first part 110 and the T_start_pointer 204 is managed by the second part 120. That is, when the transmission data is stored in the transmission memory 202 by the first unit 110, the T_last_pointer 206 points to the block location where the last data is stored. When the transmission data is read by the second unit 120 for actual data transmission, the T_start_pointer 204 is moved by the number of data blocks read and the transmission counter 208 is incremented by the number of read data.

At this time, when the T_last_pointer 206 exceeds the T_start_pointer 204, this means that the first unit 110 continuously records data to be transmitted in the memory in a state where the transmission is delayed in the second unit 120. . In this case, whether to abandon existing data and send new data or continue to send existing data is defined in each communication standard. If the standard is to give up the old data and send new data, when the T_last_pointer 206 exceeds the T_start_pointer 204, the T_start_pointer 204 should be moved as much as the data to be abandoned.

Unlike the case of transmission, the R_start_pointer 212 of the reception memory 210 is managed by the first unit 110, and the R_last_pointer 214 is managed by the second unit 120. When received data is stored in the receiving memory by the second unit 120, the R_last_pointer 214 indicates the location where the last data is stored. Each time the received data is processed by the first unit 110, the R_start_pointer 212 is moved by the processed data, and the received counter 216 is increased by the number of processed data.

At this time, it is assumed that the R_last_pointer 214 exceeds the R_start_pointer 212 means that the first part 110 processes the data slower than expected in the system, and therefore, does not occur in the system according to the present invention. If the data reception in the second unit 120 is faster than the data processing speed in the first unit 110, the corresponding data is lost and the second unit 120 sends a NAK packet to the counterpart.

The first clock setting section 218 executed in the period T reads the values of the transmission counter 208 and the reception counter 216 in the i-th cycle (after reading, resets each of the transmission / reception counters to zero), The actual transmission rate and reception rate in the i th period are calculated according to the following equation.

Here, R _t [i] represents the actual transmission rate in the i th cycle, Ct [i] is the transmission counter value in the i th cycle, T is the period, and L _p is the minimum unit length of the transmission data.

Where Rr [i] is the actual reception rate in the i-th cycle, Cr [i] is the reception counter value in the i-th cycle, T is the period, and Lp is the minimum unit length of the received data.

The first clock setting unit 218 sets the optimal first clock frequency F [i + 1] for the i + 1th period according to the following equation by using the actual transmission / reception rate calculated in the ith period. .

F ₁ [i + 1] = (A _t XR _t [i] + B _t ) + (A _r XR _r [i] + B _r ), i = 0, 1, 2,...

Where A _t , B _t , A _r and B _r values are constants. In order to determine the values of A _t and B _t , an environment in which only ACK packets are artificially received and only transmissions are performed at a transmission rate Rt can be obtained by measuring and linearly fitting a first clock necessary for various Rt. have. Similarly, A _r and B _r values establish an environment in which only ACK packets are artificially transmitted and only received at the reception rate R _r (transmitting side to R _r ) to measure the first clock needed for various R _r . And linear fitting.

At this time, if the value of the period T is too small, additional power loss is increased in the calculation of the clock F ₁ [i + 1], and if the value of the period T is too long, the optimization is delayed and it is difficult to reduce the power loss. In general, considering that the scheduling period of the real-time computer operating system is about 10 ms, the value of the period T is appropriately 10 to 100 ms.

Meanwhile, the second clock setting unit 220 refers to the correspondence table 222 that stores the optimal clock values F ₂ [i], i = 1, 2, ..., n for each transmission mode, and refers to the second clock. Set the value. Correspondence table 222 stores the optimal clock value determined experimentally for each possible transmission mode of the communication device. That is, when the number of possible transmission modes of the system is n, the optimum second clock frequency F ₂ [i] is stored for each index (i = 1, 2, ..., n).

Various algorithms exist for determining the transmission mode of a communication device, but one embodiment of the algorithm is described below. In order to determine the optimal transmission mode of the second unit 120, the following algorithm is performed every period T. If the current highest transmission mode and the actual transmission rate is higher than the lower one transmission mode, the current transmission mode is maintained, otherwise the UpStayDown process is performed. The UpStayDown process adjusts the transmission mode by one step, as in the past transmission mode if the ratio of the past actual transmission rate to the current actual transmission rate is less than 0.9, and the current transmission mode is changed from the past when the ratio is larger than 1.1. Keep it.

That is, when the current transmission mode is changed upward compared to the past, the future transmission mode change method is changed upward compared to the present, and similarly, when the current transmission mode is changed downward, the future transmission mode change method is downward changed.

The present invention has been described above with reference to the preferred embodiments, which are merely examples and are not intended to limit the present invention, and those skilled in the art to which the present invention pertains do not depart from the essential characteristics of the present invention. It will be appreciated that various modifications and applications are not possible that are not illustrated above.

For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

The present invention is a wireless communication system characterized by the transmission and retransmission function using multiple transmission modes such as Bluetooth (IEEE 802.15.1), broadband wireless LAN (IEEE 802.11a / b / g), WiMAX (IEEE 802.16d / e) By dividing the structure of the system into a first part and a second part, and dynamically varying the drive clocks for the divided parts, respectively, it is possible to achieve low power for each of the first and second parts. have. According to the present invention, in the case of ignoring hardware and software overhead, it is theoretically possible to reduce power consumption by (13/18) ² as compared with the related art.

Claims (11)

10. A method for providing a dual variable clock in a wireless packet communication system logically divided into a lower performer performing a function of a physical (PHY) layer and a higher performer performing a higher layer of the physical layer. Way, A first clock providing step of measuring an actual data transmission / reception rate at a predetermined period, setting a first clock frequency F ₁ based on the measured value, and providing the first clock to the upper performing unit; A second clock providing step of determining a transmission mode of the wireless packet communication system, identifying a predetermined second clock frequency F ₂ corresponding to the determined transmission mode, and providing the second clock to the lower performing unit. Dual variable clock providing method comprising a. The method of claim 1, wherein the first clock providing step includes calculating an actual transmission rate (R _t ) and a reception rate (R _r) based on Equation 4 at a predetermined period.

, Here, R _t [i] and R _r [i] represent the actual transmission rate and reception rate in the i th cycle, and C _t [i] represent the number of transmission data read by the subordinate execution section in the i th cycle. A value, C _r [i], is a value representing the number of received data processed by the higher performing unit in the i th cycle, T is a period period, and L _p is a minimum unit length of transmission / reception data. 3. The method of claim 2, wherein the providing of the first clock sets the first clock frequency (F ₁ ) according to Equation 5 below. F ₁ [i + 1] = (A _t XR _t [i] + B _t ) + (A _r XR _r [i] + B _r ) Where F ₁ [i + 1] represents the first clock frequency in the i + 1 th cycle, R _t [i] represents the actual transmission rate in the i th cycle, and R _r [i] represents the i th cycle The actual reception at, where A _t , B _t , A _r and B _r are constants. 4. The method of claim 3, wherein the constants A _t and B _t values are obtained by measuring and linearly fitting the first clock frequency for various transmission rates (R _t ) in an environment where only transmissions are performed. The method of claim 3, wherein The constant A _r and B _r values are obtained by measuring and linearly fitting the first clock frequency for various reception rates (R _r ) in an environment where only reception is performed. The method of claim 1, wherein the predetermined period is 10 to 100 ms. 2. The method of claim 1, wherein providing the second clock comprises determining a transmission mode of the wireless packet communication system by analyzing a header of a received packet. The method of claim 1, wherein the providing of the second clock comprises determining a second clock frequency corresponding to the transmission mode by referring to a corresponding table storing the clock frequency optimized for each transmission mode of the wireless packet communication system. How to provide a clock. The method of claim 1, wherein the retransmission of the packet is performed by the lower function unit based on the second clock. The NAK of claim 9, wherein the retransmission operation of the packet fails to receive an ACK message indicating that the pre-transmitted packet has been properly received from the counterpart communication device within a predetermined period, or a NAK indicating a failure to receive a pretransmitted packet from the counterpart communication device. A method of providing a dual variable clock that is performed when a message is received. An apparatus for providing a dual variable clock in a wireless packet communication system, wherein the wireless packet communication system includes a lower performer performing a function of a physical (PHY) layer and an upper performer performing an upper layer of the physical layer. Logically divided, the dual variable clock providing apparatus, First clock providing means for measuring an actual data transmission / reception rate at a predetermined period, setting a first clock frequency F ₁ based on the measured value, and providing the first clock to the upper performing unit; A second clock providing means for determining a transmission mode of the wireless packet communication system and to identify a second clock (F ₂₎ frequency selected to correspond to the determined transmission mode to provide the second clock on the sub-performing unit Dual variable clock providing apparatus comprising a.

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