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KR20060062392A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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Publication number
KR20060062392A
KR20060062392A KR1020040101213A KR20040101213A KR20060062392A KR 20060062392 A KR20060062392 A KR 20060062392A KR 1020040101213 A KR1020040101213 A KR 1020040101213A KR 20040101213 A KR20040101213 A KR 20040101213A KR 20060062392 A KR20060062392 A KR 20060062392A
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relacs
oxide layer
etching
photoresist pattern
contact hole
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Korean (ko)
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조성윤
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자 제조 공정 중 콘택홀 형성 공정에 관한 것으로, 산화물층이 형성된 기판 상에 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 팬턴을 식각 베리어로 사용하여 상기 산화물층을 일정 깊이로 부분 식각하는 단계; 상기 산화물층이 부분 식각된 기판 전체 구조 상부에 RELACS 코팅 물질을 도포하는 단계; 상기 RELACS 코팅 물질에 대한 베이킹을 수행하여 상기 포토레지스트 패턴의 측벽 부분에 비수용성 RELACS 코팅막이 크로스링크되도록 하는 단계; 크로스링크 되지 않은 상기 RELACS 코팅 물질을 제거하는 단계; 상기 비수용성 RELACS 코팅막이 크로스링크된 상기 포토레지스트 패턴을 식각 베리어로 사용하여 상기 산화물층의 나머지 부분을 식각하는 단계; 및 상기 포토레지스트 패턴을 제거하는 단계를 포함한다.
The present invention relates to a process for forming a contact hole in a semiconductor device manufacturing process, comprising: forming a photoresist pattern on a substrate on which an oxide layer is formed; Partially etching the oxide layer to a predetermined depth using the photoresist pantone as an etching barrier; Applying a RELACS coating material over the entire structure of the substrate on which the oxide layer is partially etched; Performing baking on the RELACS coating material to crosslink the non-aqueous RELACS coating film to the sidewall portion of the photoresist pattern; Removing the RELACS coating material that is not crosslinked; Etching the remaining portion of the oxide layer using the photoresist pattern crosslinked by the water-insoluble RELACS coating layer as an etching barrier; And removing the photoresist pattern.

콘택홀, 보잉, 크로스링크, 부분 식각, RELACS, Contact hole, boeing, crosslink, partial etching, RELACS,

Description

반도체 소자의 콘택홀 형성 방법{METHOD FOR FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE} Contact hole formation method of a semiconductor device {METHOD FOR FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE}             

도1은 종래의 제1 금속배선 콘택 에칭 후 보잉 프로파일을 나타내는 도면.1 is a diagram illustrating a conventional bowing profile after etching a first metallization contact.

도2는 제1 금속배선 콘택 마스크 프로파일이 형성된 단면도.2 is a sectional view in which a first metallization contact mask profile is formed.

도3은 산화물층을 부분적으로 식각한 후의 단면도.3 is a cross-sectional view after partially etching an oxide layer.

도4는 RELACS 코팅 물질을 스핀 코팅하고, 베이킹 한 후의 크로스링커가 형성된 단면도.Fig. 4 is a cross sectional view in which a crosslinker is formed after spin coating and baking the RELACS coating material.

도5는 습식 현상후의 크로스링크되지 않은 RELACS 코팅 물질이 제거된 후의 단면도.5 is a cross-sectional view after removal of the non-crosslinked RELACS coating material after wet development.

도6은 후속하는 산화물층의 식각을 수행한 후의 단면도.Fig. 6 is a sectional view after performing etching of a subsequent oxide layer.

도7은 포토레지스트 패턴을 제거한 후의 단면도.
Fig. 7 is a sectional view after removing the photoresist pattern.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10: 기판 11: 산화물층10: substrate 11: oxide layer

12: 포토레지스트 패턴 13: RELACS 코팅막12: photoresist pattern 13: RELACS coating film

13a: 크로스링크된 RELACS 코팅막13a: crosslinked RELACS coating

본 발명은 반도체 소자의 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 콘택홀 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a contact hole forming process in a semiconductor device manufacturing process.

반도체 소자의 직접도가 증가함에 따라, 금속배선 콘택홀을 비롯한 콘택홀의 종횡비가 보다 높아지게 되어, 포토레지스트(photo resist) 선택비 부족, 콘택 오픈(contact open)의 능력 저하, 하부 CD(critical demension)의 부족, 프로파일 보잉(profile bowing) 등으로 인해 최소 공간이 감소된다는 문제점이 있었다.As the directivity of semiconductor devices increases, aspect ratios of contact holes, including metallization contact holes, become higher, resulting in a lack of photoresist selectivity, reduced contact open capability, and lower CD (critical demension). There is a problem that the minimum space is reduced due to lack of profile, profile bowing and the like.

특히, 제1 금속 배선 콘택과 같은 딥 콘택은 식각 타겟(Etch target)이 높아 산화물층 상부에 보잉(bowing)이 발생하게 되고(도1 참조), 이 보잉으로 인하여 최소 공간이 감소하게 되어, 마스크 상태에서 홀 직경을 늘린다고 해도 브리지(bridge)가 발생할 우려가 있었다.
In particular, a deep contact such as a first metal interconnection contact has a high etching target, so that bowing occurs on the oxide layer (see FIG. 1), and the bowing reduces the minimum space. Even if the hole diameter was increased in the state, there was a fear that a bridge would occur.

따라서, 본 발명은 딥 콘택홀의 상부에서 보잉이 발생하는 것을 방지할 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는데 그 목적이 있다.
Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of preventing bowing from occurring in an upper portion of a deep contact hole.

전술한 목적을 달성하기 위해, 본 발명에 따른 반도체 장치의 콘택홀 형성 방법은, 산화물층이 형성된 기판 상에 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 팬턴을 식각 베리어로 사용하여 상기 산화물층을 일정 깊이로 부분 식각하는 단계; 상기 산화물층이 부분 식각된 기판 전체 구조 상부에 RELACS 코팅 물질을 도포하는 단계; 상기 RELACS 코팅 물질에 대한 베이킹을 수행하여 상기 포토레지스트 패턴의 측벽 부분에 비수용성 RELACS 코팅막이 크로스링크되도록 하는 단계; 크로스링크 되지 않은 상기 RELACS 코팅 물질을 제거하는 단계; 상기 비수용성 RELACS 코팅막이 크로스링크된 상기 포토레지스트 패턴을 식각 베리어로 사용하여 상기 산화물층의 나머지 부분을 식각하는 단계; 및 상기 포토레지스트 패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.
In order to achieve the above object, the contact hole forming method of the semiconductor device according to the present invention, forming a photoresist pattern on a substrate on which an oxide layer is formed; Partially etching the oxide layer to a predetermined depth using the photoresist pantone as an etching barrier; Applying a RELACS coating material over the entire structure of the substrate on which the oxide layer is partially etched; Performing baking on the RELACS coating material to crosslink the non-aqueous RELACS coating film to the sidewall portion of the photoresist pattern; Removing the RELACS coating material that is not crosslinked; Etching the remaining portion of the oxide layer using the photoresist pattern crosslinked by the water-insoluble RELACS coating layer as an etching barrier; And removing the photoresist pattern.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기로 한다.
Hereinafter, a person skilled in the art to which the present invention pertains will be described in detail so that the technical spirit of the present invention can be easily implemented.

도2 내지 도7은 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 형성 공정을 나타내는 도면이다.2 to 7 are diagrams illustrating a process of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

본 실시예에 따른 콘택홀 형성 공정은, 먼저, 도2에 도시된 바와 같이, 콘택홀 마스크를 이용한 사진 및 식각 공정을 통해 기판(10) 상에 형성된 산화물층(11) 상에 포토레지스트 패턴(12)을 형성한다. In the process of forming a contact hole according to the present embodiment, first, as shown in FIG. 2, a photoresist pattern (not shown) is formed on an oxide layer 11 formed on the substrate 10 through a photolithography and an etching process using a contact hole mask. 12) form.

다음으로, 도3에 도시된 바와 같이, 포토레지스트 패턴을 식각 베리어로 사용하여 산화물층(11)을 일정 깊이로 부분 식각한다. 산화물층의 부분 식각 깊이는 콘택홀 내에 보잉이 발생되지 않는 정도의 타겟, 예를 들면, 전체 식각 깊이의 1/3 내지 1/4 정도의 깊이가 바람직하다.Next, as shown in FIG. 3, the oxide layer 11 is partially etched to a predetermined depth by using the photoresist pattern as an etching barrier. The partial etching depth of the oxide layer is preferably a target at which the bowing does not occur in the contact hole, for example, a depth of about 1/3 to 1/4 of the total etching depth.

다음으로, 도4에 도시된 바와 같이, RELACS(Resolution Enhancement Lithography Assisted by Chemical Shrink) 코팅 물질인 AZ R200을 포토레지스트 패턴(12) 상에 스핀-코팅하여 RELACS 코팅막(13)을 형성한다. AZ R200은 가용성 폴리머(Water-Soluble Polymer)와 크로스링커(Cross Linker)를 구성할 수 있다.Next, as shown in FIG. 4, the RELACS coating layer 13 is formed by spin-coating AZ R200, which is a Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) coating material, on the photoresist pattern 12. AZ R200 can form a water-soluble polymer and a cross linker.

이와 같이, RELACS 코팅막(13)을 형성한 후에는, 온도 120℃에서 20초 내지 70초간 베이킹을 수행한다. 도4는 베이킹으로 공정으로 인하여 포토레지스트 패턴(12)의 측벽과 상면에 RELACS 코팅막이 크로스링크되어 있는 상태를 도시하고 있다. 이러한 크로스링커(크로스링크된 RELACS 코팅막)(13a)는 포토레지스트 패턴(12)의 에지에 남아 있는 산(Acid)에 의한 촉매화 반응에 의해 형성된다.As such, after the RELACS coating layer 13 is formed, baking is performed at a temperature of 120 ° C. for 20 seconds to 70 seconds. 4 shows a state in which the RELACS coating film is crosslinked on the sidewalls and the top surface of the photoresist pattern 12 due to the baking process. This crosslinker (crosslinked RELACS coating film) 13a is formed by a catalysis reaction with an acid remaining at the edge of the photoresist pattern 12.

계속하여 도5에 도시된 바와 같이, RELACS 코팅막의 크로스링크되지 않은 부분을 23℃에서 50초 내지 100초 동안 AZ R2 현상액(Developer)을 사용하여 제거한다. 여기서, AZ R2 현상액은 물과 소량의 첨가물(additives)로 구성되어 있다. 도5는 크로스링크되지 않은 RELACS 코팅막(13)이 제거된 상태를 도시하고 있다. Subsequently, as shown in FIG. 5, the non-crosslinked portion of the RELACS coating film is removed using an AZ R2 developer at 23 ° C. for 50 to 100 seconds. Here, the AZ R2 developer is composed of water and a small amount of additives. 5 shows a state in which the non-crosslinked RELACS coating film 13 is removed.

도5에 도시한 바와 같이, 크로스링크된 RELACS 코팅막(13a)이 포토레지스트 패턴의 상부 측벽에 형성되어 콘택홀의 직경이 줄어든 상태가 되고, 이 상태에서 부분 식각된 산화물층(11)의 나머지 부분을 완전 식각한다. As shown in FIG. 5, the crosslinked RELACS coating layer 13a is formed on the upper sidewall of the photoresist pattern to reduce the diameter of the contact hole, and in this state, the remaining portion of the partially etched oxide layer 11 is removed. Etch completely.

도6은 콘택홀의 나머지 부분이 완전히 식각된 상태를 도시하고 있다. 도6에 도시된 바와 같이, 포토레지스트 패턴의 측벽에 형성된 크로스링크된 RELACS 코팅 막(13)으로 인해, 산화물층(11)의 측벽이 식각되는 것이 방지되기 때문에 콘택홀의 직경이 점점 커지고 상부의 보잉 역시 방지됨을 알 수 있다.6 illustrates a state in which the rest of the contact hole is completely etched. As shown in Fig. 6, the diameter of the contact hole becomes larger and the upper boeing is caused by the crosslinked RELACS coating film 13 formed on the sidewall of the photoresist pattern, since the sidewall of the oxide layer 11 is prevented from being etched. It can also be seen that it is prevented.

도7은 식각 대상으로 되는 산화물을 완전히 식각한 후 포토레지스트 패턴(12)를 제거한 상태를 도시하고 있다. 도7에 도시된 바와 같이, 콘택홀을 형성을 종료하였지만, 종래와 같은 보잉이 발생되지 않고, 산화물 상부의 콘택홀의 크기가 종래의 콘택홀에 비교하여 크게 증가되고, 부산물(By-Product)의 휘발성이 우수하여 콘택 오픈의 능력도 향상되며, 최소 공간의 크기도 증가하였음을 알 수 있다.FIG. 7 illustrates a state in which the photoresist pattern 12 is removed after the oxide to be etched is completely etched. As shown in Fig. 7, the contact hole is finished, but the conventional boeing does not occur, and the size of the contact hole on the oxide is greatly increased as compared with the conventional contact hole, and by-product Due to the excellent volatility, the ability of contact opening is improved and the minimum space size is also increased.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의해야 한다. 또한, 본 발명의 기술 분야의 통상의 지식을 가진자라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명에 의하면, 딥 콘택홀의 상부에서 발생되는 보잉을 방지하면서 콘택 상부 홀 직경을 넓혀 콘택 오픈의 능력을 향상시킬 수 있고, 보잉으로 인한 브리지를 방지할 수 있으며, 수직 프로파일(vertical profile)을 형성할 수 있다.According to the present invention, it is possible to increase the contact upper hole diameter while preventing the bowing generated in the upper portion of the deep contact hole to improve the ability of the contact open, to prevent the bridge due to the bowing, to form a vertical profile (vertical profile) can do.

Claims (4)

산화물층이 형성된 기판 상에 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern on the substrate on which the oxide layer is formed; 상기 포토레지스트 팬턴을 식각 베리어로 사용하여 상기 산화물층을 일정 깊이로 부분 식각하는 단계;Partially etching the oxide layer to a predetermined depth using the photoresist pantone as an etching barrier; 상기 산화물층이 부분 식각된 기판 전체 구조 상부에 RELACS 코팅 물질을 도포하는 단계;Applying a RELACS coating material over the entire structure of the substrate on which the oxide layer is partially etched; 상기 RELACS 코팅 물질에 대한 베이킹을 수행하여 상기 포토레지스트 패턴의 측벽 부분에 비수용성 RELACS 코팅막이 크로스링크되도록 하는 단계;Performing baking on the RELACS coating material to crosslink the non-aqueous RELACS coating film to the sidewall portion of the photoresist pattern; 크로스링크 되지 않은 상기 RELACS 코팅 물질을 제거하는 단계;Removing the RELACS coating material that is not crosslinked; 상기 비수용성 RELACS 코팅막이 크로스링크된 상기 포토레지스트 패턴을 식각 베리어로 사용하여 상기 산화물층의 나머지 부분을 식각하는 단계; 및Etching the remaining portion of the oxide layer using the photoresist pattern crosslinked by the water-insoluble RELACS coating layer as an etching barrier; And 상기 포토레지스트 패턴을 제거하는 단계Removing the photoresist pattern 를 포함하는 반도체 소자의 콘택홀 형성 방법.Contact hole forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 산화물층의 부분 식각 깊이는 완전 식각 깊이의 1/4 내지 1/3 의 깊이인 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The partial etching depth of the oxide layer is a contact hole forming method of the semiconductor device, characterized in that the depth of 1/4 to 1/3 of the complete etching depth. 제1항에 있어서,The method of claim 1, 상기 베이킹은 120℃의 온도에서 20초 내지 70초 동안 수행되는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The baking is performed for 20 seconds to 70 seconds at a temperature of 120 ℃ contact hole forming method of a semiconductor device. 제1항에 있어서,The method of claim 1, 상기 잔여 RELACS 코팅 물질의 제거 단계는 습식-현상(Wet-Developement)에 의해 수행되는 반도체 소자의 콘택홀 형성 방법.Removing the remaining RELACS coating material is performed by wet-development.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103177937A (en) * 2011-12-22 2013-06-26 台湾积体电路制造股份有限公司 Selective bias compensation for patterning steps in CMOS processes

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103177937A (en) * 2011-12-22 2013-06-26 台湾积体电路制造股份有限公司 Selective bias compensation for patterning steps in CMOS processes

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