KR20060062525A - Method of manufacturing semiconductor device having recess gate - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device having a recess gate. The recess gate forming process of the present invention includes forming a pad oxide layer and a pad nitride layer pattern on a semiconductor substrate to define an isolation region and an active region. Etching the silicon substrate of the device isolation region by a predetermined depth to form a first trench; forming a device isolation layer by filling a gap fill oxide layer in the first trench; and forming a recess region on the pad nitride layer of the active region. Defining a photoresist pattern, forming a second trench by etching the photoresist pattern with an etch mask to a predetermined depth of the pad nitride layer, the pad oxide layer, and the semiconductor substrate of the active region, and forming an inner wall of the second trench; Forming a gate oxide film on the substrate, and conducting conductivity over the entire surface of the product on which the gate oxide film is formed; Forming a film and an insulating film sequentially; forming a gate electrode by chemical mechanical polishing the insulating film until the upper surface of the pad nitride film is exposed; and removing the pad nitride film and the pad oxide film over the active region. And forming a gate spacer on sidewalls of the gate electrode, forming a source and a drain where the pad oxide layer and the pad nitride layer are removed, and generating a plug connecting the source and the drain.

Recess gate, damascene, misalignment, plug

Description

A method of manufacturing a semiconductor device having a recess gate {Method of manufacturing semiconducter with gate of recess gate}

1 to 18C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

***** Explanation of symbols for main parts of drawing *****

1: semiconductor substrate 2: pad oxide film

3: pad nitride film 4: first photosensitive film pattern

5: device isolation layer 6: second photoresist pattern

7: gate oxide film 8: gate conductive film

9: gate upper insulating film 10: gate spacer

11: plug

The present invention relates to a method of manufacturing a semiconductor device having a recess gate, and more particularly, in a DRAM memory cell according to high integration, to prevent misalignment of a recess region and a gate pattern formation region, thereby stabilizing device characteristics, and A method for manufacturing a semiconductor device having a recess gate capable of forming an aligned plug.

Recently, in order to manufacture a highly integrated memory or a highly integrated device (ULSI), the size and design rules of semiconductor devices are gradually reduced. However, as the design rule of the memory device manufacturing technology is less than 0.1μm, it is difficult to secure sufficient data retention time in the case of memory devices, especially DRAM. This is because as the size of the device decreases, the electric field strength increases due to the increased doping concentration, and as a result, the leakage current of the junction portion increases.

Accordingly, a method of increasing the channel length by using a so-called recess gate that etches a semiconductor substrate to form irregularities in the channel formation portion has been studied.

In general, a method of fabricating a semiconductor device having a recess gate, first, forming a device isolation layer on a silicon substrate to separate a device isolation region from an active region, and then forming a mask defining a recess region of the gate on the substrate of the active region. Then, the silicon substrate is etched by a predetermined thickness using an etching mask to form a trench. In addition, a general gate forming process, that is, a gate oxide layer, a gate electrode, and a hard mask are sequentially stacked on the substrate, and then a mask defining a gate formation region is formed on the substrate to overlap the trench, and the mask is formed as an etching mask. And etching the gate oxide layer to form a gate pattern. Next, a gate spacer is formed on sidewalls of the gate pattern, and a plug for connecting a source and a drain is formed.

As described above, the semiconductor element having the recess gate manufactured by the prior art has a trench having a predetermined depth in the silicon substrate at a position corresponding to the gate formation region of the active region, so that the length of the channel is defined by the profile of the trench. As a result, a short channel effect is minimized due to high integration of the device.

However, in the conventional method of manufacturing a transistor having a recess gate, a trench for recessing the substrate is first formed by a first mask process, and then a second mask process is performed on the substrate on which the trench is formed to overlap the trench. To form. As such, the two-time mask process has difficulty in aligning the gate pattern exactly on the trench due to the high integration of DRAM memory cells. That is, there is a problem that the characteristics of the device are unstable because the trench and the gate pattern are misaligned.

Meanwhile, a sufficient area must be secured in order to proceed with an etching process for forming a plug in the semiconductor substrate. However, as described above, as the design rule decreases, the size of the device also decreases, and thus there is a problem that an area for forming a plug in the etching process cannot be secured.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. In a DRAM memory cell according to high integration, a recess gate capable of stabilizing device characteristics by aligning a recess region and a gate pattern formation region by a damascene method is disclosed. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a structure.

Another object is to form a plug that is self-aligned without damaging the gate electrode by using the pad nitride film.

In order to achieve the above object, the present invention provides a method of forming a pad oxide layer and a pad nitride layer pattern on a semiconductor substrate to define an isolation region and an active region, and etching the silicon substrate of the isolation region by a predetermined depth to form a first trench. Forming a device isolation layer by filling a gap fill oxide layer in the first trench, forming a photoresist pattern defining a recessed region on the pad nitride layer of the active region, and etching the photoresist pattern as an etch mask Forming a second trench by etching the pad nitride layer, the pad oxide layer, and the semiconductor substrate in the active region to a predetermined depth; forming a gate oxide layer on an inner wall of the second trench; Sequentially forming a conductive film and an insulating film on the pad; Forming a gate electrode by chemical mechanical polishing until the upper surface of the layer is exposed, removing the pad nitride layer and the pad oxide layer on the active region, forming a gate spacer on the sidewall of the gate electrode; A method of manufacturing a semiconductor device having a recess gate, the method comprising: forming a source and a drain where the pad oxide film and the pad nitride film are removed, and generating a plug connecting the source and the drain.

The forming of the device isolation layer may include depositing an oxide layer such that the first trench is buried, and chemically polishing the gap fill oxide layer to a point at which the upper surface of the pad nitride layer is exposed. The method may include depositing an insulator on the entire surface of the substrate on which the gate electrode is formed, and selectively etching the insulator to leave only the side of the gate electrode. However, the depth of the first trench is preferably made deeper than the depth of the second trench.

In addition, the forming of the plug may include the steps of depositing a plug material where the pad nitride film and the pad oxide film are removed, and chemically or mechanically polishing the plug material to a point where an upper surface of the gate electrode insulating layer is exposed. Depositing polysilicon by a growth method, and then depositing doped polysilicon thereon, and chemically mechanically polishing the doped polysilicon to a point where the upper surface of the gate electrode insulating film is exposed. Can be.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Advantages and features of the present invention, and a method of achieving the same will be apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be embodied in various forms beyond the embodiments. In addition, like reference numerals refer to like elements throughout the specification.

1 to 18C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device having a recess gate according to an exemplary embodiment of the present invention.

First, as shown in FIG. 1, the pad oxide film 2 and the pad nitride film 3 are sequentially formed on the semiconductor substrate 1. And as shown in FIG. 2A, the 1st photosensitive film pattern 4 which defines an element isolation region is formed on it. In this case, the pad oxide layer 2 is deposited to a thickness of about 100 GPa to relieve stress of the silicon substrate 1 and the pad nitride layer 3 and to serve as an etch stop layer when the subsequent pad nitride layer 3 is removed. The pad nitride layer 3 may serve as an etching mask in subsequent various trench etching processes, or serve as a polishing stop layer in a chemical mechanical polishing process.

Subsequently, as shown in FIG. 2B, the pad nitride layer 3 and the pad oxide layer 2 are sequentially etched using the first photoresist pattern 4 as an etching mask to define an isolation region on the substrate 1. do.

As shown in FIG. 3, the semiconductor substrate 1 is etched to a predetermined depth using the patterned pad nitride film 3 as a mask to form a first trench in the semiconductor substrate 1.

Next, as shown in FIG. 4, the gap fill oxide film 5 is buried in the entire surface of the semiconductor substrate 1 so as to sufficiently fill the first trench, and then the pad nitride film 3 is used as the etch stop film. The chemical mechanical polishing (CMP) of the gapfill oxide film 5 is performed until the upper surface of (3) is exposed. Accordingly, as shown in FIG. 5, the gap fill oxide film 5 forms the device isolation film 5 embedded only in the first trench, and the device isolation film 5 connects the semiconductor substrate 1 to the active region. It is divided into device isolation regions.

As shown in FIG. 6, a second photoresist layer pattern 6 defining a recessed region and a gate formation region is defined on the pad nitride layer 3 of the substrate 1 on which the device isolation layer 5 is formed. Form.

Subsequently, as shown in FIG. 7A, the pad nitride film 3, the pad oxide film 2, and the semiconductor substrate 1 in the active region are etched to a predetermined depth by using the second photoresist pattern as a mask. Form a second trench. Here, the second trench formed under the substrate 1 with respect to the surface of the semiconductor substrate 1 defines a recessed region, and the pad nitride film 3 and the pad oxide film 2 patterned on the semiconductor substrate 1. Defines a gate formation region. In other words, the present invention applies a damascene technique using the pad nitride film 3 to the process of defining the gate formation region and the recess region, so that the gate formation region and the recess region are accurately formed in a single mask process. It can be self-aligned to match. Accordingly, the problem of misalignment of the gate formation region and the recess region due to the conventional two-step mask process is solved.

In addition, the depth of the second trench is preferably formed to have a smaller depth than the depth of the first trench forming the device isolation layer 5. In addition, during the etching process for forming the second trench, a portion of the upper surface of the device isolation layer 5 may also be lost, so that the height of the device isolation layer 5 is lowered. A plan view of the process that has been performed so far can be confirmed through FIG. 7B.

Thereafter, as shown in FIG. 8, a thermal oxidation process is performed on the substrate 1 on which the second trench is formed to form a gate oxide film 7 on the inner wall of the second trench, and as shown in FIG. 9. Similarly, a conductive film 8 having a thickness thick enough to completely fill the second trench is formed thereon.

As shown in FIG. 10A, after the conductive film 8 has been subjected to chemical mechanical polishing (CMP) to the time point at which the surface of the pad nitride film 3 is exposed, the conductive film 8 is subjected to the pad nitride film ( 3) Etch back down. In this case, it is preferable to use etchback rather than chemical mechanical polishing (CMP) to reduce nitride film loss. A plan view of the process that has been performed so far can be confirmed through FIG. 10B.

After that, as shown in FIG. 11, an insulating film 9 for insulating the conductive film 8 from the upper lamination and other wiring processes is deposited, and the pad nitride film 3 is used as an anti-polishing film as shown in FIG. Thus, only the insulating film 9 on the gate electrode is removed.

Next, as shown in FIG. 13A, the pad nitride film 3 and the pad oxide film 2 are removed. Meanwhile, during the process of removing the pad nitride film 3 and the pad oxide film 2, a portion of the upper surface of the device isolation film 5 is removed to lower the height of the device isolation film 5 exposed on the surface of the semiconductor substrate 1. A plan view of the process that has been performed so far can be confirmed through FIG. 13B.

Thereafter, as shown in FIG. 14, the insulator 10 is deposited on the entire surface of the substrate 1 on which the gate electrode is formed, and then, as shown in FIG. 15A, it is selectively etched to remain only on the sidewall of the gate electrode. To form the gate spacer 10. A plan view of the process that has been performed so far can be confirmed through FIG. 15B.

Subsequently, a source / drain junction ion (not shown) is formed by implanting ions for forming a source / drain into the substrate 1 using the gate spacer 10 as a mask.

As shown in FIG. 16, after depositing a plug material for forming a source and a drain on the entire surface of the substrate 1 on which the gate electrode is formed, the surface of the gate electrode insulating layer 9 is exposed until the surface of the gate electrode insulating layer 9 is exposed. Mechanical polishing (CMP) or etchback (etchback) to form the contact 11 (see Figure 17a). A plan view of the process so far proceeds can be seen through Figure 17b.

In the formation of the plug according to another embodiment of the present invention, as shown in FIGS. 18A and 18B, first, the polysilicon 12 is grown by a selective growth method, and then the doped polysilicon 13 is deposited thereon. Can be used.

Thereafter, as illustrated in FIG. 18C, the contact 11 is formed by chemical mechanical chemical mechanical polishing (CMP) or etchback until the surface of the gate electrode insulating film 9 is exposed.

According to the present invention, a method of manufacturing a semiconductor device having a recess gate capable of stabilizing device characteristics by aligning a recess region and a gate pattern formation region by a damascene method in a DRAM memory cell according to high integration can be provided. It can be effective.

In addition, the pad nitride film may also be used to form a self-aligned plug without damaging the gate electrode.

Claims (6)

Defining a device isolation region and an active region by forming a pad oxide layer and a pad nitride layer pattern on the semiconductor substrate; Etching the silicon substrate of the device isolation region by a predetermined depth to form a first trench; Filling the gap fill oxide layer in the first trench to form an isolation layer; Forming a photoresist pattern defining a recessed region on the pad nitride layer of the active region; Etching the pad nitride layer, the pad oxide layer, and the semiconductor substrate in the active region using the photoresist pattern as an etch mask to form a second trench; Forming a gate oxide film on an inner wall of the second trench; Sequentially forming a conductive film and an insulating film on the entire surface of the resultant product in which the gate oxide film is formed; Chemically and mechanically polishing the insulating layer until the upper surface of the pad nitride layer is exposed to form a gate electrode; Removing the pad nitride film and the pad oxide film over the active region; Forming a gate spacer on sidewalls of the gate electrode; Forming a source and a drain where the pad oxide film and the pad nitride film are removed; Generating a plug connecting the source and the drain; A semiconductor device manufacturing method having a recess gate comprising a. The method of claim 1, wherein a depth of the first trench is deeper than a depth of the second trench. The method of claim 1, wherein forming the device isolation layer comprises: depositing an oxide layer to bury the first trench; And chemically polishing the gap fill oxide layer to a point where the upper surface of the pad nitride layer is exposed. The method of claim 1, wherein the forming of the spacers comprises: depositing an insulator on an entire surface of the substrate on which the gate electrode is formed; Selectively etching the insulator and leaving only the side surface of the gate electrode to form a recess gate. The method of claim 1, wherein forming the plug comprises: depositing a plug material where the pad nitride film and the pad oxide film are removed; And chemically polishing the plug material until the upper surface of the gate electrode insulating layer is exposed. The method of claim 1, wherein the forming of the plug comprises: growing polysilicon by a selective growth method; Depositing doped polysilicon over the polysilicon; And chemically polishing the doped polysilicon until the upper surface of the gate electrode insulating layer is exposed.

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