KR20060029762A - Thin Film Formation Method of Semiconductor Device - Google Patents

Abstract

In the thin film formation method having a low dielectric constant, the substrate is first loaded into the reaction chamber. A silicon source gas, a fluorine source gas, an oxygen gas, and hydrogen gas for reducing the sputtering effect of the formed thin film are respectively supplied to the substrate, and a plasma is generated to form an insulating film. According to the above process, a gap fill property is improved and a thin film having a low dielectric constant is formed.

Description

Method for forming a thin film in semiconductor device

1 to 2 are cross-sectional views for explaining the method for forming an insulating film of the present invention.

3 is a cross-sectional view for describing a process of filling a gap by an HDP-CVD process when the gap has a first aspect ratio.

4 is a cross-sectional view for describing a process of filling a gap by an HDP-CVD process when the gap has a second aspect ratio.

5 to 9 are cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention.

The present invention relates to a method for forming a thin film of a semiconductor device. More specifically, the present invention relates to a method of forming an insulating film having a low dielectric constant.

Recently, the LSI semiconductor device, the ultra-fast SRAM device, and the flash memory device have become a serious problem due to the response delay caused by the increase of parasitic capacitance. The parasitic capacitance is mainly generated as the metal wires are very close between the metal wires and the arrangement of the metal wires has the same structure as the capacitor. Therefore, in order to reduce the parasitic capacitance, an interlayer insulating film formed between the metal wirings must be formed as an insulating material having a low dielectric constant.

The insulating material having a low dielectric constant may be formed by a spin-on dielectric (SOD) method and a chemical vapor deposition method (hereinafter, referred to as CVD), and it is known that the CVD method is more advantageous in terms of film stability. Examples of the insulating film having a low dielectric constant that can be formed by the CVD method include a fluorine-containing silicon oxide film (FSG film) and an SiOC film.

The silicon oxide film (SiO2), which is mainly used as an interlayer insulating film in the manufacture of semiconductor devices, has a dielectric constant of about 4.1. On the other hand, the FSG film has a dielectric constant of about 3.4 to 3.7, and the SiOC film has a dielectric constant of about 3.0. Therefore, when the FSG film or the SiOC film is formed of the interlayer insulating film between the metal wiring and the metal wiring, parasitic capacitance can be reduced to some extent.

However, although the FSG film and SiOC have relatively low dielectric constants, the films are not easy to apply to the manufacture of semiconductor devices. For example, in the case of the FSG film, the content of fluorine in the film must be increased in order to lower the dielectric constant, but in the case of the fluorine, there is a problem in that the stability of the film is lowered because out diffusion occurs.                         

In addition, the SiOC film has a micro-pore at the bonding center, and has a low dielectric constant by the pore. However, an increase in the voids results in a less dense membrane, which results in poor mechanical properties of the membrane. Moreover, the SiOC film is also difficult to be used to fill gaps between metal wires because of poor gap fill properties, and is currently used only when metal wires are formed by damascene processes.

An object of the present invention is to form an insulating thin film having low dielectric constant and excellent gap fill characteristics in a semiconductor device.

In order to achieve the above object, the thin film forming method of the present invention first loads a substrate into a reaction chamber. Subsequently, a silicon source gas, a fluorine source gas, an oxygen gas, and hydrogen gas for reducing the sputtering effect of the formed thin film are supplied to the substrate, and a plasma is generated to form an insulating film.

According to the method, by introducing hydrogen gas having a very small particle during the deposition process, it is possible to reduce the effect of sputtering the upper portion of the thin film during the deposition process. Therefore, the gap filling capability is improved when the insulating film is embedded between the patterns very densely on the substrate.

The thin film forming method of the present invention will be described.

First, a substrate having a stepped portion formed on its surface is loaded into the reaction chamber.                     

A silicon insulating gas, a fluorine source gas, an oxygen gas, and a hydrogen gas are respectively supplied into the substrate, and a plasma is generated to form an insulating film filling the stepped portion. The insulating film formed by the above process is a fluorinated silicon oxide film (hereinafter referred to as FSG film). Here, the silicon source gas, the fluorine source gas and the oxygen gas are source gases for forming the FSG film, and the hydrogen gas is provided as a carrier gas of the source gases. Specifically listing available gases, the silicon source gas may use SiH 4, and the fluorine source gas may use SiF 4.

The insulating film is formed by a high density plasma chemical vapor deposition process (hereinafter referred to as HDP-CVD process). The HDP-CVD process is typically performed at high vacuum and high power compared to atmospheric pressure chemical vapor deposition (AP-CVD), low pressure chemical vapor deposition (LP-CVD), or plasma enhanced chemical vapor deposition (PE-CVD). . Therefore, when the film is formed by the HDP-CVD process, the film structure is dense and the mechanical properties of the film are excellent. Here, the mechanical property refers to a property that can obtain reproducible results when performing unit processes such as etching and polishing.

The HDP-CVD process is performed at high vacuum and high power to generate sputtering by ion bombardment. In the case of the present invention, the membrane is sputtered by the hydrogen gas. However, since the particles of the hydrogen gas are very small, the etching effect of the film by the sputtering is small, thereby improving the gap fill capability. In addition, as the fluorine is included in the silicon oxide film, the polarity of ions and electrons is reduced, thereby decreasing the dielectric constant of the insulating film.

In order to further reduce the dielectric constant of the insulating film, a gas containing carbon may be further introduced together with the silicon source gas, the fluorine source gas, the oxygen gas, and the hydrogen gas when the insulating film is formed. As described above, when a gas containing carbon is further introduced, fine pores are formed in the insulating film, and the pores may be formed of an insulating film having a lower dielectric constant.

According to the above-listed methods, the gap fill characteristics can be improved and an insulating film can be formed with a low dielectric constant. This can be actively applied to form a structure such as an interlayer insulating film formed between metal wirings.

Hereinafter, with reference to the accompanying drawings will be described in detail the thin film formation method of the present invention.

1 to 2 are cross-sectional views for explaining the method for forming an insulating film of the present invention.

Referring to FIG. 1, a substrate 10 in which metal wiring patterns 12 are densely formed on a surface thereof is provided.

Specifically, a lower structure (not shown) for forming a semiconductor device is formed on the substrate 10, and a metal film (not shown) is formed on the lower structure. The metal film includes an aluminum film or a tungsten film. The hard mask layer is formed on the metal layer, and the hard mask layer is partially etched by performing a photolithography process to form the hard mask pattern (not shown). The metal wiring pattern 12 is formed by etching the metal layer using the hard mask pattern as an etching mask.                     

Typically, the metal wiring pattern 12 is formed to be very high in order to reduce the resistance of the wiring, while the semiconductor device is highly integrated, and the line width d1 and the metal wiring pattern 12 of the metal wiring pattern 12 are increased. The space | interval d2 is formed very narrow. Therefore, the gap between the metal wiring patterns 12 is formed narrow in the horizontal direction and deep in the vertical direction. Specifically, the aspect ratio (aspect ratio) of the gap has a ratio of 1: 3 or more.

Subsequently, the substrate on which the metal wiring pattern 12 is formed is loaded into the reaction chamber.

Referring to FIG. 2, a silicon source gas, a fluorine source gas, and an oxygen gas are supplied onto a substrate having the metal wiring pattern 12, and hydrogen gas is supplied as a carrier gas of the gases. By generating a plasma, an FSG film 14 filling at least the gap between the metal wiring patterns is formed.

In detail, the silicon source gas may use SiH 4, and the fluorine source gas may use SiF 4. At this time, the flow rate ratio of the SiH 4: SiF 4: O 2: H 2 introduced into the chamber may be 1: 0.1 to 10: 0.1 to 10: 1 to 200.

Looking at the other conditions for forming the FSG film 14, the pressure in the chamber maintains 1 to 1000mTorr. In addition, the source power is applied from 500 to 9000 W to form a plasma in the chamber. Then, the bias power is applied to more than 0 and less than 5000W. The bias power may not be applied in some cases.                     

When the deposition process is performed while the gases are introduced into the chamber, the FSG film 14 is formed and at the same time, sputtering is generated by hydrogen gas. However, since the hydrogen gas has a very small particle size, the deposited FSG film 14 by sputtering is very etched. Therefore, it is possible to minimize the gap fill is prevented by the sputtering by introducing the hydrogen gas.

Hereinafter, the relationship between the sputtering and the gap fill will be described in more detail.

3 is a cross-sectional view for describing a process of filling a gap by an HDP-CVD process when the gap has a first aspect ratio. 4 is a cross-sectional view for describing a process of filling a gap by an HDP-CVD process when the gap has a second aspect ratio higher than that of the first aspect ratio.

In the structure shown in FIG. 3, patterns 102 are formed on a substrate 100, and the gaps between the patterns 102 have a relatively low aspect ratio of less than 1: 3. In depositing the film 104 to fill the gap, the gap fill effect is increased as the films 106 deposited at the top inlet portion of the gap are redeposited on the bottom of the gap while being etched by sputtering. However, as the semiconductor device is increasingly integrated, the aspect ratio of the gap is increased, so that the sputtering becomes an obstacle to the gap fill.

Specifically, as shown in FIG. 4, when the gap between the patterns 102a has a relatively high aspect ratio of 1: 3 or more, the films 106a deposited at the upper inlet portion of the gap are formed by sputtering. After etching, it is deposited on the side rather than falling to the bottom of the gap, making the profile of the gap more negative. Therefore, when performing the HDP-CVD process for filling the gap with a high aspect ratio, it is preferable to adjust the process so that sputtering hardly occurs.

To this end, the gap fill characteristics can be improved by using hydrogen gas having relatively small particles as the sputtering gas, without sputtering with a gas having relatively large particles such as Ar or He as in the related art.

The FSG film formed by the above-described process has a SiO 2 structure as a back born, and some of the Si—O bonds in the SiO 2 network structure are replaced by Si—F bonds. The Si-F bond has a smaller ionic and electronic polarity than the Si-O bond. Therefore, the FSG film has a lower dielectric constant than the conventional SiO 2 film. In addition, the gap fill effect can be maximized by using the hydrogen gas as a carrier gas.

By further introducing a gas containing carbon into the deposition gas used in the above-described method, an interlayer insulating film having a lower dielectric constant can be formed.

Specifically, a substrate is formed on the surface of which metal wiring patterns are densely formed. In general, the metal wiring pattern is formed very high in order to reduce the resistance of the wiring, while the semiconductor device is highly integrated, and the size of the metal wiring pattern and the spacing between the metal wiring patterns are very narrow. Therefore, a gap is formed between the metal wiring patterns in the horizontal direction and deep in the vertical direction, and specifically, the aspect ratio of the gap is 1: 3 or more.

The substrate on which the metal wiring pattern is formed is loaded into the reaction chamber.

Subsequently, a gas containing silicon source gas, fluorine source gas, oxygen gas and carbon is supplied onto a substrate having the metal wiring pattern, and hydrogen gas is supplied as a carrier gas of the gases. The plasma is generated to form a carbon doped FSG film (hereinafter referred to as a carbon-doped FSG film) filling a gap between the metal wiring patterns.

In detail, the silicon source gas may use SiH 4, and the fluorine source gas may use SiF 4. In addition, the carbon-containing gas may be a hydrogenated gas or an organosiloxane source gas.

Examples of the hydrocarbon gas include CH 4, C 2 H 4, C 2 H 6, C 2 H 2, and C 6 H 6, which may be used alone or in combination. In addition, examples of the organosiloxane source gas include methyltriethoxylsilane (MTES), diethoxymethylsilane (DEMS), dimethoxymethylsilane (DMOMS), tetramethylcyclotetrasiloxane (TOMCATS), dimethyldimethoxysilane (DMDMOS), dimethyldimethoxysilylcyclohexane (DMDOSH), and trimethylsilane alone (Z3MS). Can be used in combination.

 At this time, the flow rate ratio of the gas containing SiH 4: SiF 4: O 2: H 2: carbon flowing into the chamber is 1: 0.1 to 10: 0.1 to 10: 1 to 200: 0.1 to 300.

Looking at the conditions for forming the insulating film, the pressure in the chamber is maintained at 1 to 1000mTorr. In addition, the source power is applied from 500 to 9000 W to form a plasma in the chamber. Then, the bias power is applied to more than 0 and less than 5000W. The bias power may not be applied in some cases.

According to the above process, an interlayer insulating film further introduced with a gas containing carbon is further formed. Therefore, fine voids are formed in the carbon bond in the interlayer insulating film. The minute pores serve to further lower the dielectric constant of the interlayer insulating film. As a result, an interlayer insulating film having a lower dielectric constant than that of the existing FSG film can be formed.

Unlike the conventional SiOC film, the film is formed by a high-density plasma process performed under high vacuum and high power conditions, and since the structure of the film is based on Si-O, the film has excellent mechanical properties.

In addition, as the hydrogen flows in, the gapfill capability may be improved, thereby forming an interlayer insulating layer having no void between the metal lines. Therefore, it is possible to prevent process defects that may be caused by the voids.

Hereinafter, an embodiment in which the thin film forming method of the present invention described above is specifically applied to a semiconductor device will be described.

5 to 9 are cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention.

Referring to FIG. 5, a device isolation layer 202 is formed by performing a device isolation process such as a shallow trench device isolation (STI) process or a silicon partial oxidation (LOCOS) process on the semiconductor substrate 200, thereby forming the semiconductor substrate 200. ) Is divided into an active region and a field region. Subsequently, a gate oxide film (not shown) is formed on the active region by thermal oxidation.

A gate conductive layer and a hard mask layer are sequentially formed on the gate oxide layer, and patterned to form a gate structure (not illustrated) in which a gate conductive layer pattern (not shown) and a hard mask pattern (not shown) are stacked. . Gate spacers (not shown) made of silicon nitride are formed on both sidewalls of the gate structure.

Using the gate structure as an ion implantation mask, impurities are implanted into a semiconductor substrate between the gate structures by an ion implantation process to form source / drain regions. Through the subsequent process, the source region (not shown) is described as connected to the bit line and the drain region 204 is connected to the capacitor.

A first interlayer insulating layer 206 filling the gate structure is deposited. The first interlayer insulating layer 206 may be formed of silicon oxide, and specifically, may be formed using BPSG, PSG, USG, SOG, TEOS, or HDP-CVD oxide.

Next, the first interlayer insulating layer 206 is partially etched to form first contact holes (not shown) that expose the source / drain regions. By filling a conductive material in the first contact hole, a first pad electrode (not shown) for connecting with the bit line and a second pad electrode 208 for connecting with the capacitor are formed, respectively.

Next, a second interlayer insulating film 210 is formed on the first interlayer insulating film 208 on which the first and second pad electrodes are formed.                     

Referring to FIG. 6, the second interlayer insulating layer 210 is partially etched to form a second contact hole (not shown) that exposes the first pad electrode. While filling the second contact hole, a first conductive layer (not shown) is formed on the second interlayer insulating layer 210 to form a bit line. The first conductive layer may be formed of a metal. Specifically, in order to form a first conductive film made of metal, a barrier metal film (not shown) is formed on the second contact hole and the second interlayer insulating film to prevent diffusion of metal atoms. A tungsten film (not shown) is formed on the second interlayer insulating film 210 while filling the second contact hole on the barrier metal film.

A second hard mask pattern 214 is formed on the first conductive layer to pattern the bit line. Next, the first conductive layer is patterned using the second hard mask pattern 214 as a mask to form bit line contacts (not shown) and bit lines 212.

Bit line spacers 216 made of silicon nitride are formed on both sides of the stacked structure of the bit line 212 and the second hard mask pattern 214.

Referring to FIG. 7, a third interlayer insulating layer 218 is formed to fill the bit line 212 and the second hard mask pattern 214.

However, the bit line 212 is formed of a metal having low resistance, and a bit line spacer 216 made of silicon nitride having a high dielectric constant is formed at a side thereof. Therefore, the third interlayer insulating layer 218 may be formed of an insulating material having a low dielectric constant to minimize parasitic capacitance. In addition, since the height of the structure in which the bit lines 212 and the second hard mask patterns 214 are stacked is about 3000 to about 5000 m and the spacing between the bit lines is about 300 to 1000 m, the third interlayer insulating film 218 ) Is very difficult to landfill without voids. Therefore, when forming the third interlayer insulating film 218, it should be used under the condition that the gap fill characteristics are excellent.

As described above, in order to form the third interlayer insulating film 218 having excellent gap fill characteristics and low dielectric constant, a gas including silicon source gas, fluorine source gas, and oxygen gas is supplied to the substrate, and the carriers of the gases are Hydrogen gas is supplied as gas. In addition, in order to further reduce the dielectric constant of the third interlayer insulating layer 218, a gas containing carbon may be further supplied. Then, high density plasma is generated.

In detail, the silicon source gas may use SiH 4, and the fluorine source gas may use SiF 4.

In addition, the carbon-containing gas may be a hydrogenated gas or an organosiloxane source gas. Examples of the hydrocarbon gas include CH 4, C 2 H 4, C 2 H 6, C 2 H 2, and C 6 H 6, which may be used alone or in combination. In addition, examples of the organosiloxane source gas include methyltriethoxylsilane (MTES), diethoxymethylsilane (DEMS), dimethoxymethylsilane (DMOMS), tetramethylcyclotetrasiloxane (TOMCATS), dimethyldimethoxysilane (DMDMOS), dimethyldimethoxysilylcyclohexane (DMDOSH), and trimethylsilane alone (Z3MS). Can be used in combination.                     

At this time, the flow rate ratio of the gas containing SiH 4: SiF 4: O 2: H 2: carbon flowing into the substrate may be 1: 0.1 to 10: 0.1 to 10: 1 to 200: 0.1 to 300.

Looking at the conditions for forming the third interlayer insulating film 218, the pressure in the chamber in which the process is performed is maintained 1 to 1000mTorr. In addition, the source power is applied from 500 to 9000 W to form a plasma in the chamber. Then, the bias power is applied to more than 0 and less than 5000W. The bias power may not be applied in some cases.

When the deposition process is performed according to the process conditions, a third interlayer insulating layer 218 having a low dielectric constant having a dielectric constant k of about 2.5 to about 4 is formed. And, since the sputtering is generated by hydrogen gas during the deposition process, the gap fill characteristics are improved. As a result, the third interlayer insulating layer 218 may be formed so that voids do not occur between the bit lines, and the inter-contact bridge defect, which may be generated by the voids, may be minimized. In addition, the film is formed by a high-density plasma process performed under high vacuum and high power conditions, and since the film structure is based on Si-O, the mechanical properties of the film are excellent.

In addition, when additional gas containing carbon is further introduced, fine voids are formed in the carbon bond in the third interlayer insulating film 218. Therefore, the dielectric constant of the third interlayer insulating layer 218 is further lowered by the minute gap.

Referring to FIG. 8, the third interlayer insulating layer 218 and the second interlayer insulating layer 206 are partially etched to form a third contact hole (not shown) exposing the second pad electrode 208. After performing the etching process, a wet cleaning process for removing reaction by-products generated during etching is generally performed. An etching process for forming the third contact hole may be performed to self-align to the structure including the bit line and the second hard mask pattern.

However, since the mechanical properties of the third interlayer insulating layer 218 are excellent, excessively vulnerable portions of the third interlayer insulating layer 208 may be excessively formed during the etching and cleaning processes of the third interlayer insulating layer 208. Almost no problems such as being eliminated occur. Thus, a reproducible contact hole profile can be obtained.

Subsequently, a conductive material is formed to fill the third contact hole 218 to form a lower electrode contact 220.

9, a cylindrical capacitor 230 is formed on the lower electrode contact 220 and the third interlayer insulating layer 218. A fourth interlayer insulating layer 232 is formed on the capacitor 230, and then an upper wiring 234 is formed on the fourth interlayer insulating layer 232. Thereafter, the DRAM device is completed by forming an upper interlayer insulating layer 236 filling the upper wiring 234. Typically, the upper wiring 234 is formed by depositing and patterning a metal material such as aluminum or tungsten.

When forming the upper interlayer insulating layer 236 to fill the upper wiring 234, the method of forming the interlayer insulating layer according to the exemplary embodiment of the present invention may be applied in the same manner. That is, the upper interlayer insulating layer may be formed by performing the same process as that of forming the third interlayer insulating layer 218. In this case, gaps between the upper interconnections 234 may be filled without voids, and parasitic capacitances generated between the upper interconnections 234 may be reduced.

In addition, when the gate electrode of the transistor is made of a metal, the thin film forming method can be actively applied to the interlayer insulating film filling the gate electrode.

As described above, according to the present invention, it is possible to form an interlayer insulating film having a low dielectric constant and an improved gap fill capability in a semiconductor device manufacturing process. Therefore, when the interlayer insulating film having a low dielectric constant is used as a film filling a gap between conductive patterns having a low resistance such as a metal, parasitic capacitors can be reduced. Therefore, problems such as a decrease in response speed caused by the parasitic capacitor can be reduced. In addition, since the gap fill property of the interlayer insulating film is excellent, a very narrow and deep gap between the conductive patterns may be filled without voids. Therefore, the defect caused by the voids in the gap can be reduced.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (13)

Loading the substrate into the reaction chamber; And And supplying a silicon source gas, a fluorine source gas, an oxygen gas, and hydrogen gas to reduce the sputtering effect of the formed thin film to the substrate, and generating a plasma to form an insulating film. Thin film formation method. The method of claim 1, wherein patterns are formed on the substrate, and the insulating layer is formed to fill the gaps between the patterns. The method of forming a thin film of a semiconductor device according to claim 1, wherein the pattern is a metal wiring pattern. The method of claim 1, wherein the silicon source gas is SiH 4, and the fluorine source gas is SiF 4. The method of claim 4, wherein the flow rate ratio of SiH 4: SiF 4: O 2: H 2 is 1: 0.1-10: 10.0.1-10: 1-200. The method for forming a thin film of a semiconductor device according to claim 1, wherein a gas containing carbon is further introduced when forming the insulating film. The method of claim 6, wherein the carbon-containing gas is a hydrocarbon gas or an organosiloxane source gas. The method of claim 7, wherein the hydrogenated gas is selected from the group consisting of CH 4, C 2 H 4, C 2 H 6, C 2 H 2, C 6 H 6, and a mixture thereof. 8. The method of claim 7, wherein the organosiloxane source gas is MTES, DEMS. DMOMS, TOMCATS, DMDMOS, DMDOSH. At least one selected from the group consisting of Z3MS thin film forming method of a semiconductor device. 7. The thin film formation of a semiconductor device according to claim 6, wherein the flow rate ratio of the gas containing SiH4: SiF4: O2: H2: C is 1: 0.1 to 10: 0.1 to 10: 1 to 200: 0.1 to 300. Way. The method of forming a semiconductor device according to claim 1, wherein the pressure in the chamber at the time of forming the insulating film is maintained at 1 to 1000 mTorr. The method for forming a thin film of a semiconductor device according to claim 1, wherein a source power in the chamber at the time of forming the insulating film is more than 500W and less than 9000W and a bias power is more than 0W and less than 5000W. The method of claim 12, wherein the bias power is not applied.

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