KR20060021099A - How to Write Data to NAND Flash Memory - Google Patents

Abstract

The present invention relates to a method for writing data into a NAND flash memory in a host and a NAND flash memory having different write units. According to the present invention, a step of receiving and storing data of a first unit from the host and performing a dummy operation are performed. This operation is performed until data of the N-th first unit is received. When the data of the N-th first unit is received, the data on which the dummy operation is performed and the N-th data are provided to the NAND flash memory.

Description

Data writing method of NAND flash memory {DATA WRITE METHOD OF NAND FLASH MEMORY}

1 is a read / write timing diagram of a small block flash memory.

2 is a read / write timing diagram of a large block flash memory.

3 is a block diagram of a NAND flash memory according to the present invention.

4 is a data writing timing diagram according to a conventional method.

5 is a data write timing diagram according to the method according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: host 200: NAND flash memory

300: controller 201: page register

302: SRAM

The present invention relates to a data writing method of a NAND flash memory. More particularly, the present invention relates to a method of writing data into a NAND flash memory when the host and the NAND flash memory have different write units.

NAND flash memory can be roughly divided into small block flash memory and large block flash memory.

1 is a read / write timing diagram of a small block flash memory. The read / write unit of small block flash memory is 528 bytes. TR (the time the data reaches the register from the cell) of the small block flash memory is up to 12ms, and the serial page access time / 1 byte of data is stored in register or global buffer. Time to reach / O) is 50 ms. And tPROG (time to program from register to cell) is typically 200 ms. Also, nop, which can be programmed continuously without erasing the same word line, is 0 to 511 bytes, that is, once in the main array, and 512 to 527 bytes, that is, twice in the spare array. Referring to FIG. 1, a command for performing a pointer operation during reading is 00h and a program command is 80h. 70h is a command for reading a state. When the program is ready for 80h, the data in the register is programmed into the cell at the 10h command.

2 is a read / write timing diagram of a large block flash memory. The read / write unit of a large block flash memory is 2112 bytes. The tR of a large block flash memory is up to 25 ms and the serial page access time is 50 ms. And tPROG is typically 250 Hz. Also, nop, which can be programmed continuously without erasing the same word line, is 0 to 2047 bytes, that is, four times in the main array, and 2048 to 2112 bytes, that is, four times in the spare array. The same commands as those of FIG. 1 among the commands shown in FIG. 2 perform the same operation. However, in a large block flash memory, since a command is input over two cycles, data is read from the cell in the 30h command after the 00h command.

As described above, the small block flash memory and the large block flash memory are different from each other. In some cases, the host system and the flash memory have different structures. For example, a host system using an xD picture card is a system that recognizes only a small block flash memory. This is the case when an XD picture card using a large block flash memory is used.

In such a case, there is a need for an apparatus and method for converting between small block flash memory to large block flash memory or large block flash memory to operate as small block flash memory. The conversion controller and the conversion flash transition layer (FTL) play this role. The conversion controller takes the data from the host and delivers it to NAND flash memory. At this time, the conversion FTL causes the host system to actually write the data into the memory cell that stores the data of the flash memory every 528 bytes every 528 bytes.

In this case, since four repetitive writes are performed on the same page, a problem of increasing stress in the memory cell occurs. Considering 26.4 ms (50 ms * 528 bytes) and 528 bytes program time of approximately 250 ms, the time taken to transfer data from the I / O to the registers takes 1105.6 ms. Therefore, there is a problem in that a large write time is required compared to 325 ms when writing 2112 bytes, which is an advantage of a large block flash memory, at a time.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a data writing method of a NAND flash memory which reduces cell stress caused by repeated programs and improves data writing time.

According to an aspect of the present invention, there is provided a method of writing a data in a NAND flash memory, the method comprising: writing data received from a host having a first writing unit into a NAND flash memory having a second writing unit; Receiving and storing data of a first unit from the host; b) performing a dummy operation; c) repeating the operations a) and b) until the data of the N-th first unit is accepted; And d) providing the N-th data and the N-th data to the NAND flash memory in which the step c) is performed when the data of the N-th first unit is received.

In this embodiment, the data is stored in the SRAM in step a).

In this embodiment, the data is stored in the page register in the NAND flash memory in step a).

In this embodiment, the method further includes e) writing the provided data to the NAND flash memory.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram of a NAND flash memory according to the present invention.

Referring to FIG. 3, a controller 300 is included between the host 100 and the NAND flash memory 200. In the present invention, the host 100 recognizes only a small block memory, but the NAND flash memory 200 to be coupled thereto is a large block memory. Therefore, the controller 300 is required to make it compatible. Inside the controller 300, a host interface 301 region, an SRAM 302, and a NAND interface 303 region exist.

Although not shown, system software, called a conversion FTL, functions together with the controller 300 to convert the small block flash memory to act as a large block flash memory. Translation FTL provides a mapping function that translates and manages addresses for small block flash memory to physical addresses of large block flash, manages unexpected power drops, converts data when needed, and blocks bad blocks in use. block) Management and wear management function. The transform FTL allocates a log block from a free block and writes to the log block by applying a log scheme when performing a write operation. If there is no log block or no free block, merge is performed to secure the free block. Merge means creating a data block by copying only the latest valid data from the data block and the previously allocated log block to a new free block, and then making the old data block and the log block with the copied data into the free block. In this way, when the free block is secured, the free block is allocated to the log block, and then the requested data or erase mark is written to the log block.

When the host 100 receives a write request in units of 528 bytes, the conversion FTL converts the address of the small block flash memory into the large block flash memory address. The data is stored in the storage device until the data written at the same address is 2112 bytes. As the data storage location, the SRAM 302 in the controller 300 or the page register 201 in the NAND flash memory 200 may be used.

When the 528 byte write request is made four times, the host interface 301 writes one to three times in a dummy operation. When the fourth data comes in, the previous data, the fourth data, and a total of 2112 bytes of data are actually written to the NAND flash memory 200.

4 is a data writing timing diagram according to the conventional method, and FIG. 5 is a data writing timing diagram according to the method according to the present invention.

In the drawing, the Long R / B time means the time for actually programming the NAND flash memory. And short R / B time means the time to program by dummy operation. It takes 0.5㎲, the minimum tPROG required by the host.

Therefore, according to the conventional method, since the host actually writes to the NAND flash memory every time a 528-byte data write request is made, the time taken to transfer data from the I / O to the register every time is 26.4 ms (50 ms * 528 bytes). ) And 528 byte program time took 250 ms. Therefore, the total time to write 2112 bytes to NAND flash memory was 1105.6 ms.

However, according to the data writing method of the NAND flash memory according to the present invention, the first to third data of the data that the host requests to write to the NAND flash are virtually stored in the storage device after the program, that is, the short R / B time. At this time, the host recognizes that data is stored in the NAND flash memory. When the fourth 528 byte data write request is made, the data stored in the storage device and the fourth requested data are actually written to the large block flash memory. Therefore, at this time, 250 ms, which is a time spent writing 2112 bytes, is consumed. Therefore, writing to the large block flash memory is completed with a total of 251.5 ms time. Therefore, it is possible to write 2112-byte data by spending about a quarter of the time compared with 1105.6 ms when writing 528-byte data requested to be written from the host four times.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, according to the present invention, stress of the memory cell due to repetitive writing can be prevented, and writing time can be shortened.

Claims (6)

A method of writing data received from a host having a write unit as a first unit into a NAND flash memory having a write unit as a second unit, a) receiving and storing data of a first unit from the host; b) performing a dummy operation; c) repeating the operations a) and b) until the data of the N-th first unit is accepted; And and d) providing the N-th data and the N-th data to the NAND flash memory in which step c) is performed when data of the N-th first unit is received. Way. The method of claim 1, And storing the data in the SRAM in the step a). The method of claim 1, And storing the data in the page register in the NAND flash memory in step a). The method of claim 1, e) writing the provided data to the NAND flash memory. The method of claim 1, And the first unit of the host is 528 bytes. The method of claim 1, And the second unit of the NAND flash memory is 2112 bytes.

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