KR20060018699A - Pad placement method of semiconductor device - Google Patents

Abstract

In the method of arranging pads of a semiconductor device, the semiconductor device is divided into four bank areas by vertically and horizontally divided into four bank areas, and pads corresponding to the TSOP method are arranged between banks in which the divided banks face each other. The pads corresponding to the FBGA method are disposed at the center area and disposed at both edges of the semiconductor device, so that only one product design can be applied to the TSOP method and the FBGA package method simultaneously. You can choose the package type according to your needs.

Semiconductor, pad, batch, chip

Description

Pad placement method of semiconductor device {METHOD FOR DISPOSING PAD IN SEMICONDUCTOR DEVICE}             

1 is a diagram showing the arrangement of pad rows in a typical TSOP package;

2 is a view showing the arrangement of pad rows in the case of a typical FBGA package,

3 illustrates an arrangement of pad rows that may simultaneously correspond to TSOP and FBGA packages in accordance with a preferred embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

110 to 140: bank

200: bonding pad

200T: Pad corresponding to TSOP method

200T ': TSOP pads without bonding required

200F: Pad corresponding to FBGA method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging pads of a semiconductor device, and more particularly, to a method of arranging pads of a semiconductor device capable of simultaneously applying a thin small out-line package (TSOP) and a fine pitch ball grid array (FBGA).

Conventionally, TSOP packages using lead frames have become the mainstream of packages of semiconductor devices. Since the lead frame is used when packaging the semiconductor device with this TSOP, the design of the lead frame is very difficult when the pad is placed at the edge of the chip. As shown in FIG. 1, a lead 0n chip (LOC) structure is used. The pad was placed in the center of the chip.

As such, the semiconductor device package in which the TSOP package has become mainstream has a surface in which semiconductor chips are bonded using a printed board instead of a TSOP package using a lead frame in accordance with the trend of miniaturization, light weight, high speed, and multifunctionality of electronic products. By arranging solder balls on the opposite side of the surface, a highly pitched ball grid array (BGA) package, particularly a fine pitch ball grid array (CSP), is a chip scale package (CSP). FBGA: Fine Pitch Ball Grid Array) is used. Such FBGA is mainly used in mobile products that require miniaturization and low power consumption. In this case, when packaged as FBGA, a multi chip package is also used. Therefore, pads are not disposed at the center of the chip, and pads are disposed at the edge of the chip as shown in FIG.

On the other hand, in the case of FBGA, since TSOP is expensive, the TSOP is still used depending on the type of the product in which the package is used or the needs of the consumer in terms of actual demand.

However, in the case of a configuration in which the pad arrangement of the semiconductor memory device differs according to the current packaging method of the semiconductor device, that is, in the case of the FBGA package, the pad row is arranged at the edge of the chip, and in the case of TSOP, the pad row is located at the center of the chip. In the case of arranging, even in the same product, there is a problem of being manufactured separately according to the type of package.

In addition, as the semiconductor products are diversified and highly integrated, it is not preferable that the arrangement of the pads is fixed according to the type of the package for ease of design of the semiconductor products.

Therefore, an object of the present invention is to provide a method for arranging pads of a semiconductor device which can be applied to FBGA and TSOP simultaneously.

In accordance with an aspect of the present invention, in the method of arranging pads of a semiconductor device, the semiconductor device is divided into four bank regions by vertically and horizontally divided into four bank regions, and the pads corresponding to the TSOP method face each other. The pads may be disposed in a central area between banks, and pads corresponding to the FBGA method may be disposed at both edges of the semiconductor device, thereby simultaneously applying to the TSOP method and the FBGA package method using only one product design.

In addition, bonding pads among the pads corresponding to the TSOP method may be disposed in a central area between banks in which the divided banks face each other, and remaining pads except the bonding pads among the pads corresponding to the TSOP method and the FBGA. Pads corresponding to the method may be disposed at both edges of the semiconductor device.

In addition, the pad corresponding to the TSOP method disposed on both edges of the semiconductor device may include a power applying pad and a test pad.

In addition, the power applying pad and the test pad may be a pad corresponding to the TSOP method and a pad corresponding to the FBGA method.

In addition, the same address pad is disposed in both the center region between the banks and both edges of the semiconductor device.

Hereinafter, a method of arranging pads of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to the accompanying FIG. 3. FIG. 3 is a diagram illustrating arrangement of pad rows that may simultaneously correspond to TSOP and FBGA packages according to a preferred embodiment of the present invention.

First, referring to FIG. 3, the semiconductor device is divided into four banks 110 to 140 divided horizontally and vertically. In this case, each bank 110 to 140 forms a memory cell array including a plurality of memory cells.

The pads 200T corresponding to the TSOP method are formed between the opposite banks, for example, the bank 110 and the bank 120, and the center region between the banks 130 and 140 between the banks 130 and 140. That is, the pads to be connected to the memory cell array and the lead frame in each of the banks 110 to 140 are disposed in the center region between the banks. At this time, between the banks 110 to 140, an input / output circuit for performing data input and output to the outside and a data bus for performing data transfer between the memory cell arrays are provided. Input and output circuits are provided in the edge regions on both sides, but the display is omitted in order to more clearly show the arrangement of the pads according to the present invention.

In this way, only one product design can be applied to the TSOP method and the FBGA package method simultaneously, and the package method can be selectively used according to the type of product or the needs of the product designer.

Meanwhile, in another embodiment of the present invention, the entire pad 200T corresponding to the TSOP method is not disposed in the inter-bank center area, but only pads bonded to the memory cell array, such as an input / output pad, in the inter-bank center area. 3, the remaining pads of the pads corresponding to the TSOP method except for the bonding pads, for example, a power supply pad and a test pad, etc., as indicated by reference numeral 200T 'in FIG. 3. May be disposed together with the pads 200F corresponding to the FBGA scheme. At this time, any of the pads 200T corresponding to the TSOP method that are not bonded to the memory cell array may be provided at both edges of the semiconductor device.

Meanwhile, in another embodiment of the present invention, pads provided at both edges of the semiconductor device among the pads 200T corresponding to the TSOP method, such as a power applying pad and a test pad, may be pads 200F corresponding to the FBGA method. Used in common with these fields, the semiconductor device can be miniaturized.

On the other hand, in another embodiment of the present invention, the same address pad may be disposed in both the inter-bank center region and both edges of the semiconductor device. As such, by arranging the same address pads in both the center region between the banks and both edges of the semiconductor device, when the FBGA and TSOP methods are used simultaneously, the pads when bonding the memory cell array and the TSOP method pads 200T, Constraints due to the arrangement position of the can be relaxed.

According to the present invention, only one product design can be applied simultaneously to the TSOP method and the FBGA package method, and the package method can be selected according to the type of product or the needs of the product designer.

Claims (5)

In the method of arranging the pad of the semiconductor device, Divide the semiconductor device vertically and horizontally into partitions into four bank regions, Pads corresponding to the thin small out-line package (TSOP) method is disposed in a central region between banks in which the divided banks face each other, Pads corresponding to the fine pitch ball grid array (FBGA) method may be disposed at both edges of the semiconductor device. Pad placement method of semiconductor device. The method of claim 1, Bonding pads among the pads corresponding to the TSOP method are disposed in a central area between banks in which the divided banks face each other, The remaining pads of the pads corresponding to the TSOP method except for the bonding pads and the pads corresponding to the FBGA method are disposed at both edges of the semiconductor device. The method of claim 2, Pads corresponding to the TSOP method, which are disposed on both edges of the semiconductor device, the power supply pad and the test pad, characterized in that the pad arrangement method of the semiconductor device. The method of claim 3, wherein And a pad corresponding to a TSOP method and a pad corresponding to an FBGA method are commonly used as the power applying pad and the test pad. The method according to any one of claims 1 to 4, And placing the same address pad in both the center region between the banks and both edges of the semiconductor device.

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