KR20050069150A - Lateral double-diffused metal oxide semiconductor device - Google Patents

Abstract

The present invention relates to a horizontal MOS device, and more particularly to a horizontal MOS device capable of reducing the resistance between the source and the drain.

The object of the present invention is a semiconductor substrate of the first conductivity type; A second conductivity type well region formed in the semiconductor substrate; A buried layer of a second conductivity type formed in the well region; A first conductive body region formed on a surface of the substrate above the well region in which the buried layer is not formed; A source region of a second conductivity type formed on a surface of the body region and not deeper than the body region; A second conductive drain region formed on the buried layer, the depth of which is not deeper than the buried layer; And a device isolation layer separating the body region and the drain region, and a second conductive plug layer formed between the drain region and the investment layer to connect the drain and investment layer. Achieved by the device.

Therefore, in the lateral type DMOS device of the present invention, by embedding the buried layer and the plug layer in the drain region, the current passing through the source and the channel reaches the wide diffusion layer of the drain, thereby reducing the resistance between the source and the drain, It is also possible to prevent leakage to the substrate.

Description

Lateral type MOS device {Lateral double-diffused metal oxide semiconductor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to Lateral Double-Diffused Metal Oxide Semiconductor (LDMOS) devices, and more particularly to a Lateral Dimos device capable of reducing the resistance between the source and the drain.

The commonly used power MOS Field Effect Transistors (hereinafter referred to as `` MOSFETs '') have higher input impedance than bipolar transistors, so they have high power gain and very simple gate drive circuits. In addition, since it is a unipolar device, there is an advantage that there is no time delay caused by accumulation or recombination by a minority carrier while the device is turned off. Therefore, applications in switching mode power supplies, lamp ballasts, and motor drive circuits are on the rise. As such power MOSFETs, a double diffused MOSFET (DMOSFET) structure using a planar diffusion technique is widely used. A typical LDMOS transistor is US Patent NO. No. 6, which was patented by Sel Colak on November 10, 1981. 4,300,150. In addition, a technique for integrating an LDMOS transistor with a CMOS transistor and a bipolar transistor has been reported by Vladimir Rumennik in A 1200 BiCMOS Technology and Its Application, ISPSD 1992, Page 322-327, and also in 'Recent Advances in Power Integrated Circuits with High'. Level Integration ', ISPSD 1994, 348 by Stephen P, Robb.

It is important to apply DMOS transistors to power devices capable of handling high voltages. For such devices, one characteristic merit is in a current handling capacity per unit area or ON-resistance per unit area. Since the voltage ratio is determined, the ON-resistance per unit area can be reduced by decreasing the cell area of the MOS device.

In the field of power transistors, the cell pitch of the device is defined by the combined width of the contact region and polycrystalline silicon (polysilicon), which form its gate and source electrode, respectively. For DMOS power transistors, a well known technique for reducing the width of the polycrystalline silicon region is to reduce the p-type well junction depth. However, the minimum junction depth is defined by the required breakdown voltage.

Conventional LDMOS devices are well suited for application to VLSI processes because of their simple structure. However, these LDMOS devices have been considered to have poorer characteristics than the vertical DMOS (VDMOS) devices, and as a result, they have not received enough attention. Recently, it has been demonstrated that RESURF (Reduced SURface Field) LDMOS devices have excellent ON-resistance (Rsp). However, the structure of these devices is not only applicable to devices whose source is grounded, but also very complicated and difficult to apply.

In particular, in the past, DMOS transistors have been used as discrete power transistors or as components in monolithic integrated circuits. DMOS transistors are basically composed of semiconductor substrates because they are manufactured according to self-matching fabrication sequences.

The channel body region is formed by implanting one type of dopant (p-type or n-type impurity) through an aperture in a mask of gate forming material to provide a channel region that self-aligns with the gate. Typically formed. At this time, the source region is formed by injecting a dopant of a conductivity type opposite to that of the channel body region through the aperture, so that the source is self-aligned to both the gate electrode and the channel body region. This gives a relatively compact structure.

Referring to FIG. 1, a prior art LDMOS transistor device 10 is illustrated. The device has substantially two LDMOS transistors 10a and 10b.

The transistor element 10a is formed on an SOI substrate having a silicon substrate 11, a buffer oxide film 12, and a semiconductor layer 14. The semiconductor layer 14 is illustrated covering the silicon substrate 11. The field effect transistor (FET) of the conventional device includes a source region 16a and a drain region 18a. The n-type doped source region 16a is formed in the p-type doped well region 20. The well region 20 is often referred to as a P-shaped body. This p-type body 20 may extend through the semiconductor layer 14 to the upper surface of the buffer oxide film 12 as illustrated, or the region may be sufficient in the semiconductor layer 14. have.

The drain region 18a is adjacent to the other end of the field insulating region 23a. The field insulating region 23a includes a field oxide film such as, for example, thermally grown silicon oxide.

The gate electrode 26a is formed on the surface of the semiconductor layer 14. The gate electrode 26a extends from a portion of the source region 16a to the field insulating region 23a and has polysilicon doped with impurities. The gate 26a is isolated from the surface of the semiconductor layer 14 by a gate dielectric 28a. The gate dielectric 28a may comprise an oxide or nitride, or a compound thereof (ie, a stacked NO or ONO layer).

A sidewall insulating region (not shown) may be formed on the sidewall of the gate electrode 26a. The sidewall region typically comprises an oxide such as silicon oxide or a nitride material such as silicon nitride.

Highly doped body region 30 is also illustrated in FIG. 1. This body region 30 is included to have good contact with the p-type body 20. The body region 30 is more heavily doped than the p-type body 20.

Source / drain contacts 32a and 34 are also included in the transistor element 10a. The contacts 32a and 34 are provided for electrically coupling the source / drain regions 16a and 18a to other components in the circuit. In Fig. 1, a single contact 34 is used for the source regions 16a, 16b of both transistors 10a, 10b. As such, a representative prior art is disclosed in US Pat. No. 5,369,045 to Wia T. Ng, et al.

However, the above technique has a problem in that resistance between the source and the drain due to current concentration increases in order for the current passing through the channel to reach the diffusion layer of the drain.

Accordingly, the present invention is to solve the problems of the prior art as described above, by inserting the buried diffusion layer and the plug diffusion layer in the drain region, since the current passing through the source and the channel reaches the wide diffusion layer of the drain between source / drain It is an object of the present invention to provide a horizontal MOS device capable of reducing the resistance of and preventing the leakage of electrons to the substrate.

The object of the present invention is a semiconductor substrate of the first conductivity type; A second conductivity type well region formed in the semiconductor substrate; A buried layer of a second conductivity type formed in the well region; A first conductive body region formed on a surface of the substrate above the well region in which the buried layer is not formed; A source region of a second conductivity type formed on a surface of the body region and not deeper than the body region; A second conductive drain region formed on the buried layer, the depth of which is not deeper than the buried layer; And a device isolation layer separating the body region and the drain region, and a second conductive plug layer formed between the drain region and the investment layer to connect the drain and investment layer. Achieved by the device.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

According to the present invention, a method of manufacturing a lateral dimming device is used to form an isolation layer. The device isolation layer is formed on the semiconductor substrate by the STI process, which is an existing process, or the device separator is formed by the LOCOS process. A thermal oxide film is then grown on the surface of the semiconductor substrate to form a pad oxide film. After defining a region where an N well is to be formed using a photolithography process, ion implantation of high concentration of N type impurities into the defined region is performed, and then the impurities are diffused through a predetermined heat treatment to form an N type well. Subsequently, the substrate is subjected to an ion implantation process with high energy and heat treated to form an N-type buried layer. Subsequently, the substrate is subjected to an ion implantation process with less energy than that for forming an N-type buried layer and heat-treated to form an N-type plug layer. Next, a self-aligned double diffused well is formed. An ion implantation process is performed to form a self-aligned double diffused well, and the substrate is subjected to Rapid Thermal Processing (RTP) to diffuse the ion implantation layers to form P-wells and N-wells. Next, polysilicon is deposited on the substrate and etched to form a gate. Next, an ion implantation process is performed on the substrate to form a source / drain region. When the source / drain is formed, ion implantation energy is performed at an ion implantation process with less energy than energy for forming the N-type plug layer.

2 is a cross-sectional view of a lateral DMOS device according to the present invention.

A second conductive well region 110 is formed in the first conductive semiconductor substrate 100 and the semiconductor substrate. A second conductive buried layer 120 is formed in the well region, and a first conductive body region 140 is formed on the surface of the substrate above the well region in which the buried layer is not formed. . A second conductive source region 160 is formed on the surface of the body region, the depth of which is not deeper than the body region. The plug layer 130 of the second conductivity type and the drain region 170 of the second conductivity type are perpendicular to the buried layer. The drain region is divided into the body region and the device isolation layer 150. The drain region, the plug layer and the buried layer are more heavily doped than the wells.

The gate 180 is formed by contacting a portion of the body region and extending to the device isolation layer. A gate oxide film is interposed below the gate.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, in the lateral type DMOS device of the present invention, by embedding the buried layer and the plug layer in the drain region, the current passing through the source and the channel reaches the wide diffusion layer of the drain, thereby reducing the resistance between the source and the drain, It is also possible to prevent leakage to the substrate.

1 is a cross-sectional view of a prior art LDMOS device.

2 is a cross-sectional view of a lateral DMOS device according to the present invention.

Claims (3)

A first conductive semiconductor substrate; A second conductivity type well region formed in the semiconductor substrate; A buried layer of a second conductivity type formed in the well region; A first conductive body region formed on a surface of the substrate above the well region in which the buried layer is not formed; A source region of a second conductivity type formed on a surface of the body region and not deeper than the body region; A second conductive drain region formed on the buried layer, the depth of which is not deeper than the buried layer; An isolation layer separating the body region and the drain region; And A second conductive plug layer formed between the drain region and the investment layer to connect the drain and investment layer; Horizontal type MOS device comprising a. The method of claim 1, And the buried layer has a higher doping concentration than the doping concentration of the well region. The method of claim 1, The buried layer, the plug layer and the drain, characterized in that formed in the vertical MOS device.