KR20050069585A - Isolation method for semiconductor device - Google Patents
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- KR20050069585A KR20050069585A KR1020030101797A KR20030101797A KR20050069585A KR 20050069585 A KR20050069585 A KR 20050069585A KR 1020030101797 A KR1020030101797 A KR 1020030101797A KR 20030101797 A KR20030101797 A KR 20030101797A KR 20050069585 A KR20050069585 A KR 20050069585A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
소자 분리막의 가장자리가 침식되는 현상으로 인한 소자간 브리지 및 험프 현상을 방지하여 소자의 전기적 특성을 향상시킬 수 있는 소자 분리 방법은, 반도체 기판 상에, 비활성 영역을 노출시키는 마스크를 형성하는 단계와, 반도체 기판을 식각하여 트렌치를 형성하는 단계와, 트렌치를 절연 물질로 매립하는 단계와, 마스크를 제거하여 소자 분리막을 형성하는 단계, 그리고 소자 분리막의 상단 가장자리에 절연막 스페이서를 형성하는 단계로 이루어진다.A device isolation method capable of improving the electrical characteristics of a device by preventing an inter-device bridge and a hump phenomenon caused by a phenomenon that the edge of the device isolation layer is eroded includes forming a mask for exposing an inactive region on a semiconductor substrate; Etching the semiconductor substrate to form a trench; filling the trench with an insulating material; removing the mask to form a device isolation layer; and forming an insulation spacer on an upper edge of the device isolation layer.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 소자 분리막의 침식으로 인한 소자간 브리지(bridge) 및 험프(hump) 현상을 방지할 수 있는 반도체 소자의 분리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of separating a semiconductor device capable of preventing bridge and hump phenomenon between devices due to erosion of the device isolation film.
반도체 소자의 고집적화에 따라 미세화 기술의 하나인 소자 분리에 관한 연구개발이 활발히 진행되고 있다. 현재 널리 사용되고 있는 소자 분리 기술인 쉘로우 트렌치 분리(Shallow Trench Isolation; 이하, "STI"라 칭함) 방법은 넓은 활성영역의 확보, 우수한 표면 평탄화 특성 및 두꺼운 소자 분리영역을 구현하여 소자간 분리에 탁월한 특성을 가진다. 도 1 및 도 2를 참조하여 종래의 STI 기술에 대해 간략히 설명한다.With the high integration of semiconductor devices, research and development on device isolation, which is one of the miniaturization techniques, is actively progressing. Shallow Trench Isolation (hereinafter referred to as "STI") method, a widely used device isolation technology, provides excellent active separation between devices by securing wide active area, excellent surface planarization, and thick device isolation area. Have 1 and 2, the conventional STI technique will be briefly described.
도 1을 참조하면, 반도체 기판(10) 위에 패드산화막(12), 질화막(14) 및 TEOS(16)를 차례로 형성한 후 소자 분리막이 형성될 영역의 TEOS(16)와 질화막(14)을 차례로 식각한다. 식각된 TEOS(16)와 질화막(14)을 마스크로 사용하여 패드산화막(12)과 반도체 기판(10)을 차례로 식각하여 반도체 기판에 트렌치를 형성한다.Referring to FIG. 1, after the pad oxide film 12, the nitride film 14, and the TEOS 16 are sequentially formed on the semiconductor substrate 10, the TEOS 16 and the nitride film 14 in the region where the device isolation film is to be formed are sequentially formed. Etch it. Using the etched TEOS 16 and the nitride film 14 as a mask, the pad oxide film 12 and the semiconductor substrate 10 are sequentially etched to form trenches in the semiconductor substrate.
도 2를 참조하면, 트렌치가 형성된 반도체 기판의 전면에 절연 물질인 O3 TEOS를 증착하여 트렌치를 매립한 다음 화학적 물리적 연마(Chemical Mechanical Polishing; CMP) 공정을 실시하여 상부의 TEOS를 제거한다. 다음, 활성영역에 남아 있던 질화막을 습식 식각하여 제거함으로써 소자 분리막(18)을 완성한다.Referring to FIG. 2, an O 3 TEOS, which is an insulating material, is deposited on the entire surface of the semiconductor substrate on which the trench is formed to fill a trench, and then a chemical mechanical polishing (CMP) process is performed to remove the upper TEOS. Next, the device isolation layer 18 is completed by wet etching and removing the nitride film remaining in the active region.
그런데, 이와 같은 종래의 STI 공정에 따르면, 활성영역에 잔류하던 질화막을 습식 식각하여 제거하는 과정에서 도 2에 도시된 바와 같이 가장자리의 소자 분리막(18)의 일부가 식각되는 현상이 발생한다. 이 상태에서 후속 공정에서 폴리실리콘막을 증착한 후 식각하여 게이트 전극을 형성하면, 폴리실리콘이 완전히 제거되지 않고 잔류하여 소자간에 브리지(bridge)가 발생하여 소자 분리 특성을 저하시키는 문제점이 있다. 또한, 소자 분리막이 침식되는 현상은 하나의 트랜지스터가 두 개의 임계전압을 갖게되는 험프(hump) 현상을 유발하여 소자의 특성을 악화시키는 문제가 있다.However, according to the conventional STI process, a portion of the edge isolation layer 18 is etched as shown in FIG. 2 in the process of wet etching and removing the nitride film remaining in the active region. In this state, when the polysilicon film is deposited and etched in a subsequent process to form a gate electrode, polysilicon is not completely removed and a bridge is formed between the devices, thereby degrading device isolation characteristics. In addition, a phenomenon in which the device isolation layer is eroded may cause a hump phenomenon in which one transistor has two threshold voltages, thereby deteriorating device characteristics.
본 발명이 이루고자 하는 기술적 과제는 소자 분리막의 가장자리가 침식되는 현상으로 인한 소자간 브리지 및 험프 현상을 방지하여 소자의 전기적 특성을 향상시킬 수 있는 소자 분리 방법을 제공하는 것이다.An object of the present invention is to provide a device isolation method that can improve the electrical characteristics of the device by preventing the bridge and the hump phenomena caused by the erosion of the edge of the device isolation layer.
상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체 소자 분리 방법은, 반도체 기판 상에, 상기 반도체 기판의 비활성 영역을 노출시키는 마스크를 형성하는 단계와, 상기 반도체 기판을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치를 절연 물질로 매립하는 단계와, 상기 마스크를 제거하여 소자 분리막을 형성하는 단계, 및 상기 소자 분리막의 상단 가장자리에 절연막 스페이서를 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above technical problem, the semiconductor device isolation method according to the present invention, forming a mask on the semiconductor substrate to expose the inactive region of the semiconductor substrate, and etching the semiconductor substrate to form a trench And filling the trench with an insulating material, removing the mask to form an isolation layer, and forming an insulation spacer at an upper edge of the isolation layer.
상기 마스크를 제거하여 소자 분리막을 형성하는 단계에서, 상기 마스크를 습식 식각하여 제거하는 것이 바람직하다.In the forming of the isolation layer by removing the mask, it is preferable to remove the mask by wet etching.
상기 절연막 스페이서는, 상기 절연막 스페이서를 형성하기 위한 소정의 식각 공정에 대해 상기 소자 분리막과 다른 식각율을 갖는 물질로 형성하는 것이 바람직하다. 특히,상기 절연막 스페이서는 질화막으로 형성하는 것이 더욱 바람직하다.The insulating film spacer may be formed of a material having an etching rate different from that of the device isolation film for a predetermined etching process for forming the insulating film spacer. In particular, the insulating film spacer is more preferably formed of a nitride film.
본 발명에 있어서, 상기 절연막 스페이서는 소자 분리막이 형성된 반도체 기판의 전면에 절연막을 증착하는 단계와, 증착된 절연막을 이방성 식각하는 단계로 형성할 수 있다.In the present invention, the insulating film spacer may be formed by depositing an insulating film on the entire surface of the semiconductor substrate on which the device isolation film is formed, and anisotropically etching the deposited insulating film.
이하 첨부 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3 내지 도 6은 본 발명에 따른 소자 분리 방법을 설명하기 위하여 도시한 단면도들이다.3 to 6 are cross-sectional views illustrating a device isolation method according to the present invention.
먼저, 도 3을 참조하면, 반도체 기판(30) 위에 완충용 패드 산화막(32)을 형성하고, 트렌치 형성용 마스크로서 질화막(34)과 TEOS(36)를 차례로 증착한다. 사진식각 공정을 실시하여 트렌치가 형성될 영역의 TEOS(36)와 질화막(34)을 차례로 이방성 식각한다. 식각된 TEOS(36)과 질화막(34)을 마스크로 하여 패드 산화막(32)과 반도체 기판(30)을 이방성 식각하여 트렌치를 형성한다.First, referring to FIG. 3, a buffer pad oxide film 32 is formed on a semiconductor substrate 30, and a nitride film 34 and a TEOS 36 are sequentially deposited as a trench forming mask. The photolithography process is performed to anisotropically etch the TEOS 36 and the nitride film 34 in the region where the trench is to be formed. The trench is formed by anisotropically etching the pad oxide film 32 and the semiconductor substrate 30 using the etched TEOS 36 and the nitride film 34 as a mask.
도 4를 참조하면, 트렌치가 형성된 반도체 기판의 전면에 절연 물질, 예를 들어 O3 TEOS를 트렌치가 충분히 매립될 정도의 두께로 증착한다. 다음에, CMP 공정을 실시하여 상부의 TEOS를 제거하고, 인산용액을 이용하여 활성영역에 잔류하던 질화막을 제거하여 소자 분리막(38)을 형성한다. 이 때, 소자 분리막(38)의 가장자리가 일부 식각되어 침식되는 현상이 발생한다.Referring to FIG. 4, an insulating material, for example, O 3 TEOS, is deposited on the entire surface of the semiconductor substrate on which the trench is formed to a thickness sufficient to fill the trench. Next, the upper TEOS is removed by performing a CMP process, and the nitride film remaining in the active region is removed using a phosphoric acid solution to form the device isolation film 38. At this time, the edge of the device isolation layer 38 is partially etched to cause erosion.
도 5를 참조하면, 반도체 기판의 전면에, 소정의 식각 공정에서 소자 분리막(38)과 다른 식각율을 갖는 절연 물질, 예를 들어 질화막을 증착한 다음, 증착된 질화막을 이방성 식각함으로써 소자 분리막(38)의 상단 가장자리에 스페이서(40)를 형성한다. 이 스페이서(40)로 인해 침식된 소자 분리막의 가장자리가 보상된다.Referring to FIG. 5, an insulating material having an etching rate different from that of the device isolation layer 38, for example, a nitride layer, is deposited on the entire surface of the semiconductor substrate, and then anisotropically etched the deposited nitride layer. A spacer 40 is formed at the top edge of 38. The spacer 40 compensates for the edge of the etched device isolation layer.
도 6은 소자 분리막이 완성된 반도체 기판 상에 게이트 전극(42)을 형성한 상태를 보인 것이다. 소자 분리막(38)이 침식된 부분에 질화막 스페이서(40)가 형성되어 있기 때문에 폴리실리콘막의 잔류로 인한 소자간 브리지 유발 및 험프 현상이 방지되어 소자 분리 특성 및 전기적 특성을 향상시킬 수 있다.FIG. 6 illustrates a state in which a gate electrode 42 is formed on a semiconductor substrate on which a device isolation film is completed. Since the nitride spacer 40 is formed at the portion where the device isolation layer 38 is eroded, the bridge isolation and the hump phenomenon between the devices due to the residual of the polysilicon layer are prevented, thereby improving device isolation and electrical characteristics.
이상의 설명에서와 같이, 본 발명에 따른 소자 분리 방법에 의하면, 소자 분리막의 상단부에 절연막 스페이서를 형성함으로써 소자 분리막의 침식으로 인한 소자간 브리지 유발 및 험프 현상이 방지되어 소자 분리 특성 및 전기적 특성을 향상시킬 수 있다. 또한, 활성 영역에 잔류하던 질화막을 제거하기 위한 습식식각을 과도하게 진행하더라도 소자 분리막의 침식을 스페이서의 두께를 조절함으로써 보상하여 주기 때문에, 질화막을 제거하기 위한 습식 식각 공정시 식각 조건을 별도로 조정할 필요가 없어 공정 마진(margin)을 충분히 확보할 수 있다.As described above, according to the device isolation method according to the present invention, by forming an insulating film spacer on the upper end of the device isolation film to prevent the bridge between the devices caused by the erosion of the device isolation film and the hump phenomenon to improve the device isolation characteristics and electrical characteristics You can. In addition, even if the wet etching for removing the nitride film remaining in the active region is excessively performed, the etch of the device isolation layer is compensated by adjusting the thickness of the spacer, so the etching conditions need to be adjusted separately during the wet etching process for removing the nitride film. There is no sufficient margin of the process.
도 1 및 도 2는 종래의 소자 분리 방법을 설명하기 위하여 도시한 단면도들이다.1 and 2 are cross-sectional views illustrating a conventional device isolation method.
도 3 내지 도 6은 본 발명에 따른 소자 분리 방법을 설명하기 위하여 도시한 단면도들이다.3 to 6 are cross-sectional views illustrating a device isolation method according to the present invention.
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| KR100734670B1 (en) * | 2005-12-26 | 2007-07-02 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
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| KR100734670B1 (en) * | 2005-12-26 | 2007-07-02 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
| US7655524B2 (en) | 2005-12-26 | 2010-02-02 | Dongbu Hitek Co., Ltd. | Method for manufacturing isolation layer having barrier layer formed thereon |
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