KR20050060033A - Image or video display device and method of controlling a refresh rate of a display - Google Patents

Abstract

The video or image display apparatus 100 of the present invention includes a display 110 for displaying an image; A display refresh circuit (200) coupled to the display (110) for refreshing an image on the display (110); And a processor 108 coupled to the display 110 and the display refresh circuit 200 and processing the received image to determine the type of image being displayed. The processor 108 changes or stops the clock signal provided to the display refresh circuit in accordance with the displayed image. This provides the advantage that by changing or stopping the refresh rate based on the type of image being displayed, the power consumption of the display device can always be minimized without feeling flicker of the display device.

Description

IMAGE OR VIDEO DISPLAY DEVICE AND METHOD OF CONTROLLING A REFRESH RATE OF A DISPLAY}

The present invention relates to a method of reducing the power consumption of a display. The present invention is applicable to a display device used in a battery-powered device such as a personal digital assistant (PDA) or a mobile phone, where the battery power for the operation and refresh of the display is limited, but is not limited thereto.

Next generation mobile and fixed communication systems are expected to provide video and image transmission capabilities as well as more conventional voice and data services. As such, as video and image services in communications devices become more and more common, improvements in video / image compression techniques are expected to meet the expected consumer needs within the available communications bandwidth.

Moreover, as mobile users wish to access better services such as text strings, text messages, emails, images and / or videos while on the move, such similar improvements are needed in display technology. If current users flow in the direction of demanding smaller, lighter, and more portable wireless communication devices, such display improvements will be considered a special market of particular importance for portable communication device manufacturers.

In the case of portable battery powered devices, it is important to minimize power consumption in order to increase battery life under recharging operation. Colored thin film transistor (TFT) liquid crystal displays (LCDs) are increasingly used in such devices. For such displays, power consumption depends primarily on the following characteristics:

(i) refresh rate,

(ii) color balance,

(iii) the amount of image data (pixel) detail displayed.

If the LCD panel displays an image, the image is blurred over time. Therefore, it is necessary to refresh it so that the image remains distinct. Therefore, pixel data is constantly retrieved from memory and provided to the LCD for use in image refreshing one pixel at a time.

As is known, the refresh rate of the display should be set sufficiently so that the human eye cannot feel the difference between the images before and after the refresh. Otherwise, you will feel flickering of the image.

Therefore, there is a need to provide a portable communication device with a display and method that reduces the refresh rate of the display, especially when displaying a static image, thereby reducing the power consumption of the display and display driver circuitry.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a battery powered wireless subscriber unit suitable for supporting the inventive concept of a preferred embodiment of the present invention.

2 is a block diagram of a preferred display driver device of the subscriber unit of FIG.

3 is a graphical diagram of a display refresh operation.

4 is a timing diagram of a subscriber unit suitable for supporting the inventive concept of the preferred embodiment of the present invention.

5 is a block diagram of a portion of a processor system that handles providing a clock signal, in accordance with a preferred embodiment of the present invention.

6 is a flowchart of a preferred process for adapting the refresh rate of a display, in accordance with a preferred embodiment of the present invention.

According to a first aspect of the present invention, there is provided a method for refreshing an image on a display device as claimed in claim 1.

According to a second aspect of the present invention, there is provided an image or video communication apparatus as claimed in claim 5.

According to a third aspect of the present invention, there is provided a display driver for controlling the refresh rate of a display device as claimed in claim 7.

According to a fourth aspect of the present invention, there is provided a video or image display apparatus as claimed in claim 8.

According to a fifth aspect of the present invention, there is provided a display driver for controlling the refresh rate of a display device as claimed in claim 12.

Another form of the invention is as claimed in the dependent claims.

In summary, the present invention provides a means for changing or stopping the clock provided to the display refresh circuit to stop or change the refresh rate of the display depending on the type of image being displayed. As such, when the display does not need to be refreshed based on the displayed image, a reduction in the overall power consumption of the display device can be achieved.

As such, by stopping the refresh operation of the control / driver circuit for a predetermined period, the length of the refresh cycle is increased, thereby reducing the refresh rate.

In summary, the inventors of the present invention have recognized that there is no distinction of refresh rate due to the differentness of the image displayed today. Therefore, the same refresh rate is applied to both static images and motion pictures. Among other things, static, i.e., fixed, images do not require high refresh rates, such as moving pictures such as video clips. As a result, when the static image is displayed, the display is refreshed more than necessary, and this refresh rate consumes unnecessary power.

A preferred embodiment of the present invention will be described with reference to a portable cellular phone. However, the inventive concept disclosed herein is a personal digital assistant (PDA), portable or mobile radio, laptop computer, wireless networking personal computer (PC), or any other digital with display supporting video / image transfer. It should be appreciated that the device is equally applicable to any other video or image display device, such as a device.

1, a block diagram of a cellular subscriber unit 100 suitable for supporting the inventive concept of a preferred embodiment of the present invention is shown. Subscriber unit 100 preferably includes an antenna 102 coupled to the duplex filter, and an antenna switch or circulator 104 that separates the receiver and transmitter in subscriber unit 100.

The receiver chain, as is well known, includes a scanning receiver front end circuit 106 (which effectively provides reception, filtering and intermediate or baseband frequency conversion). The scanning receiver front end circuit 106 is coupled in series to the signal processing function 108. The output of this signal processing function 108 is provided to a suitable output device 110, such as a screen or flat panel liquid crystal display. This screen or flat panel display 110 includes a display driver circuit 111.

Each time an image is refreshed on the screen or flat panel display 110, it is common for each pixel in the display device to be refreshed.

The receiver chain also includes a received signal strength indicator (RSSI) circuit 112 coupled to a controller 114 that maintains full subscriber unit control. The controller 114 is coupled with a timer 118 that controls timing of operation (including transmission or reception of time dependent signals) within the cellular subscriber unit 100. The controller 114 is also coupled to the signal processing function 108 (generally implemented in the DSP) and the scanning receiver front end circuit 106 that receive the transmitted video or image signal.

Therefore, the controller 114 may receive bit error rate (BER) or frame error rate (FER) data from the reconstruction information.

According to a preferred embodiment of the invention, the interaction between the microprocessor 108 and the output device 110 and the display driver circuit 111 is adapted to reduce the power consumption of each element. Power consumption reduction is achieved by the microprocessor 108 that determines or is notified of the type of image displayed on the display 110, such as static or video. In response to the determination or notification, the microprocessor 108 adapts or stops the refresh operation of the display, thereby reducing the power consumption of each device used for the refresh operation. One example of determining the type of image displayed is simply identifying the image by file type (eg, bitmap is a static image and MPEG is a video clip). Alternatively, there is a way to set the default mode to a substantially static image and return the microprocessor to normal refresh operation only when certain applications (i.e. capable of displaying video clips, etc.) are executed.

2 is a block diagram of a liquid crystal display (LCD) control / driver circuit 200, in accordance with a preferred embodiment of the present invention. A microprocessor, such as the microprocessor 108 of FIG. 1, initializes the LCD controller 140 and the DMA controller 220 through the control register 132. The microprocessor 108 manages the contents of the image memory 210 via the address bus 134 and the data bus 136. In this regard, in accordance with a preferred embodiment of the present invention, the microprocessor determines the type of image being displayed.

The LCD controller 140 also connects to the LCD panel 110 through three timing links 142a, 142b, 142c that provide timing signals, namely a vertical (V) sync signal, a horizontal (H) sync signal, and a pixel clock, respectively. Connected. The DMA controller 220 drives the pixel data bus 144 to provide pixel data to the LCD panel 110 through the data latch 240. The LCD panel 110 includes an LCD display and a control circuit (not shown).

LCD controller 140 also provides timing control signals to LCD panel 110, DMA controller 220, and data latch 240 to coordinate the retrieval and valid generation of pixel data. The DMA controller 220 retrieves pixel data of an image displayed from the memory device 210 through an address bus and a data bus. The pixel data retrieved from the memory is transferred to the data latch 240.

The LCD panel 110 receives a timing signal provided by the LCD controller 140 and retrieves data of each pixel in response to the timing signal. The LCD panel 110 then systematically displays the corresponding image one pixel at a time.

If microprocessor 108 determines the image as a static or substantially static (video) image, microprocessor 108 initiates an appropriate image refresh operation. Suitable image refresh operations include temporarily stopping the timing signals provided to the aforementioned devices used in the refresh operation, or reducing the rate of the timing signals provided to these devices so that the refresh rate is reduced.

The LCD control / driver circuit 200 shown in FIG. 2 is merely one example of a suitable LCD driver circuit arrangement, and other suitable circuitry known otherwise would be suitable for facilitating and carrying out the inventive concepts disclosed herein. You should know that it may.

If the LCD panel displays an image, the image is blurred over time. Therefore, it is necessary to refresh it so that the image remains distinct. Therefore, the pixel data is constantly retrieved from the memory and provided to the LCD panel for use in image refresh one pixel at a time.

As is known, the refresh rate of the display should be set sufficiently so that the human eye cannot feel the difference between the images before and after the refresh. Otherwise, you will feel flickering of the image. Each time the image is refreshed, it is common to refresh each pixel in a row (320-360) starting at the upper left corner 310, as shown in FIG. 3, so that each pixel in the display device is refreshed. The exception to this is when interleaving is used, in which case the pixels in the even lines are refreshed alternately.

The display refresh operation is preferably controlled in response to the state of the specific signal timing 410 as shown in the graph 400 of FIG. A preferred embodiment of the present invention is a vertical sync signal (V-sync) 420, a horizontal sync signal (H-Sync) 430, a data signal 440 and a pixel clock associated with a display along with the received video or image signal. The timing of the signal including the signal 450 is used. The frequency of the horizontal sync signal (H-Sync) 430 and the pixel clock signal 450 is a multiple of the frequency of the vertical sync signal (V-sync) 420.

The vertical sync signal (V-sync) 420 is used to notify the display apparatus 110 of the start of the integration of the next entire image or the start of the refresh of a portion of the current image. The vertical sync signal (V-sync) 420 basically controls when the vertical alignment of the refresh operation returns to the top of the display device as illustrated by the upper left corner 310 of FIG. 3. As such, in the exemplary embodiment, the display refresh rate is basically set by causing the refresh cycle to start again at the top in every low pulse of the vertical synchronization signal V-sync.

The horizontal sync signal (H-Sync) 430 is used to notify the refresh start timing of the pixel of the next horizontal line (row). Therefore, the horizontal sync signal (H-Sync) 430 controls when the horizontal alignment of the refresh operation returns to the beginning of a new row, ie, to the left side of the screen of the display 110.

The data signal 440 includes data for each pixel of the display device. This data is divided into blocks, each block representing a row on the display device. As shown in FIG. 4, these blocks correspond to a horizontal sync signal (H-Sync) 430. Furthermore, the data contained in one row is divided into a series of pixels, each pixel preferably being divided into bits relating to the primary color, ie red, green and blue.

According to a preferred embodiment of the present invention, the microprocessor 108 monitors the timing signal of the refresh operation of the display. The monitored timing signal is preferably one of a vertical sync signal (V-sync), a horizontal sync signal (H-Sync) and a pixel clock. In the case of the control driver circuit 200 shown in FIG. 2, the vertical synchronization signal V-sync is also provided to the microprocessor 108, for example, via a general purpose input / output port (not shown) of the microprocessor 108. The microprocessor 108 may monitor the vertical sync signal V-sync.

In the illustrated embodiment, the microprocessor 108 is preferably the main processor of the device including the display and control / driver circuitry. However, it should be appreciated that the apparatus may include another processor (not shown) that performs a different task than controlling the display and control / driver circuitry. In this case, unlike the above, another processor of the apparatus may monitor the vertical synchronization signal V-sync.

If the microprocessor 108 determines the opportunity to reduce or stop the refresh rate based on the type of image displayed on the LCD panel 110, the microprocessor 108 may provide a clock provided to the control / driver circuit 200. The refresh operation is stopped by stopping the signal (not shown). The clock signal for the illustrated control / driver circuit 200 is provided to the LCD controller 140 to control the timing and synchronization of the various components of the control / driver circuit 200 during the refresh operation. Stopping the provided clock signal has the effect of essentially making the control / driver circuit 200 "freeze" except for the microprocessor 108.

The stopping of the clock signal is preferably accomplished by the microprocessor 108 or another processor of the device through a clock management function that can be integrated into the microprocessor 108 or another processor of the device.

Alternatively, referring to the preferred embodiment of the present invention of FIG. 5, clock signal control may be provided by a separate clock management unit 570 (FIG. 5). In this regard, the clock manager 570 controls the clock signals provided to various components of the device, including the display 110 and the control / driver circuit 200. When the clock manager 570 stops the clock signal to the control / driver circuit 200, this is preferably performed under the instruction from the microprocessor 108 as described below.

Based on the type of image being displayed, the microprocessor determines when to resume the clock signal, ie, the refresh operation, for the control / driver circuit 200. The period during which the clock signal is stopped is selected such that the image displayed on the display has no effect on the human eye.

As such, the normal refresh rate of the display 110 controlled by the control / driver circuit 200 allows the display to be refreshed frequently enough so that a video such as a video clip is properly displayed so that the user of the device does not feel flickering or the like. Can be. When a static image is displayed that does not require a high refresh rate, such as a moving picture, the refresh rate can be reduced by periodically stopping the refresh operation as described above.

In the case of reducing the refresh rate in this way, it is desirable to stop the clock signal once every refresh cycle, i.e. once every complete display refresh. This can be most easily accomplished by monitoring the vertical sync signal (V-Sync) as described above. As can be seen from Figure 4, in the exemplary embodiment, the vertical sync signal (V-Sync) is set to "high" during the refresh cycle (vertical sync signal (V-Sync) duty cycle). At the end of the refresh cycle, the vertical sync signal V-Sync goes " low " for a short period 422, then goes high again to signal the start of the next refresh cycle.

In a preferred embodiment of the present invention, the microprocessor 108 monitors the vertical sync signal (V-Sync). Upon detecting a low signal representing a short period between refresh cycles, the microprocessor 108 stops or causes a stop of the clock signal to the control / driver circuit 200 for a predetermined period of time. This has the effect of extending the period between refresh cycles, effectively reducing the number of refresh cycles per second, thereby reducing the refresh rate. As such, by changing the period for stopping the clock signal to the control / driver circuit 200, the refresh rate can be variably reduced as required.

As such, the microprocessor 108 controls the refresh rate based on the type of image being displayed, thereby solving the problem of providing an unnecessarily high refresh rate, causing the display and display control / driver circuitry to consume unnecessarily high power. Can be.

According to a preferred embodiment of the present invention, there is provided a display device, such as a mobile communication device, comprising a display and display control / driver circuit implementing the above method of the present invention.

5 shows a processor (CPU), such as the microprocessor 108 of FIG. 2, peripheral components of the microprocessor 108 in the processor system 500, such as a traffic controller (TC) 520, and a display driver circuit ( LCD) 200, such as the control / driver circuit shown in FIG. 2, an external memory interface (EMIF) 540, etc., is a block diagram of a portion of processor system 500 that handles providing clock signals.

In the illustrated embodiment, the display driver 200 is a liquid crystal display driver used to drive a liquid crystal display (not shown), such as a thin film transistor (TFT) display, and is used with the processor system 500. However, it should be understood that the liquid crystal display driver may be replaced by a driver for another type of display used with the processor system 500 within the scope of the inventive concept.

As can be seen, oscillator 550 provides a clock signal to processor system 500. This clock signal is used as a source of another clock signal within the processor system 500. Therefore, the clock signal will be referred to as a seed clock signal later. In the exemplary embodiment, the seed clock signal has a frequency of 12 MHz.

Processor system 500 includes a digital phase locked loop (DPLL) 560 that accepts a 12 MHz seed clock signal from oscillator 550. DPLL 560 uses the seed clock signal to multiply and / or diminish it to produce a reference clock signal REF_CLK that is an output.

Processor system 500 also includes a clock management unit 570 that accepts a reference clock signal generated by DPLL 560 and provides a clock management function of the device. The clock manager 570 multiplies and / or diminishes the reference clock signal from the DPLL 560 to provide respective clock signals to the microprocessor 108 and its peripheral components. As such, in the illustrated embodiment, the clock management unit clock signal CPU_CLK to microprocessor 108, clock signal TC_CLK to traffic controller 520, clock signal LCD_CLK to display driver 200, and external memory interface. Provide a clock signal EMIF_CLK to 540 along with another clock signal required within processor system 500.

The clock rate provided to each of the microprocessor 108 and its peripheral components 520, 200, 540 depends entirely on the reference clock signal REF_CLK generated at the DPLL 560, and is generated at the clock manager 570. It depends individually on the specific clock signals CPU_CLK, TC_CLK, LCD_CLK and EMIF_CLK.

The DPLL 560 and the clock manager 570 are each configurable by the microprocessor 108 so that the microprocessor 108 can adjust the clock signal provided to each. As such, the microprocessor 108 may alter the clock signal provided to itself and its peripheral components through the reconfiguration of the DPLL 560 as a whole, and / or individually through the reconfiguration of the clock manager 570. have.

In accordance with the present invention, the display control / driver circuit 200 controls the refresh operation of the display (not shown) of the device.

According to the timing signal of the refresh operation of the display, for example, the clock signal provided to the control / driver circuit by the clock management unit 570 is interrupted, and the refresh operation is stopped. This is preferably initiated by the microprocessor 108, in which case the microprocessor 108 monitors the timing signal and stops the clock signal to the display control / driver circuit 200 when necessary. Instruct 570.

Preferably, after a predetermined period of time determined by the microprocessor 108 in accordance with the image displayed on the display, the clock signal to the control / driver circuit is resumed. For example, the resumption of the clock signal for the control / driver circuit is made in response to the signal transmitted from the microprocessor 108 to the clock manager 570, whereby the refresh operation resumes. The period during which the clock signal is stopped is selected such that the image displayed on the display has no effect on the human eye.

Referring now to FIG. 6, shown is a flow diagram of a preferred process for adapting the refresh rate of a display, in accordance with a preferred embodiment of the present invention. This process includes the step of receiving an image to be displayed by the processor (step 610). Next, at step 620, determine the type of image displayed by any known mechanism. The processor (or clock management function) then changes or stops one or more clock signals provided to any circuit or device in the display refresh (control and / or driver) circuit for a predetermined period of time, thereby refreshing the displayed image. To change.

The above-described image or video communication device and display refresh control method provide at least some of the following advantages.

(i) By changing or stopping the refresh rate based on the type of image being displayed, the display viewer / user can minimize power consumption of the display device without feeling flicker of the display device.

(ii) It is possible to dynamically optimize the power consumption of the display device while maintaining the quality of the viewing image or video.

All other features and embodiments illustrated in the disclosure and / or drawings herein are merely preferred additions and / or alternatives, and are not intended to limit the scope of the invention.

While specific preferred embodiments of the present invention have been disclosed above, those skilled in the art will be able to readily apply modifications and variations of such inventive concepts.

As such, there has been disclosed a portable communication device having a display and method capable of reducing the refresh rate of the display, particularly when displaying static images, which almost solves the problems of known display technologies.

Claims (12)

In a method 600 for refreshing an image on a display, Receiving (610) an image displayed on a display; Processing (620) the received image to determine the type of image being displayed; Changing or stopping the refresh rate of the displayed image based on the type of image (630) Refresh method comprising a. 2. The method of claim 1, wherein varying or stopping the refresh rate further comprises changing or stopping a clock signal provided to a circuit required for a display refresh operation. 3. The method of claim 1 or 2, wherein changing or stopping the refresh rate (630) further comprises changing or stopping the clock signal for a predetermined period of time depending on the type of image being displayed. Refresh method. 3. The method of claim 2, wherein varying or stopping the clock signal comprises at least one of timing parameters: a vertical sync signal 420, a horizontal sync signal 430, a data signal 440, and a pixel rate signal 450. A refresh method based on changing or stopping one. An image or video communication device (100) configured to perform the steps of the method described in claim 1. The image or video of claim 5, wherein the image or video communication device 100 is one of a cellular phone, a portable or mobile radio, a personal digital assistant (PDA), a laptop computer, and a wireless networking personal computer (PC). Communication device. A display driver (111) for controlling the refresh rate of a display device (110) configured to perform any of the steps of the method as set forth in claim 1. A display 110 for displaying an image; A display refresh circuit (200) coupled to the display (110) for refreshing an image on the display (110); A processor 108 coupled to the display 110 and the display refresh circuit 200 and processing the received image to determine the type of image being displayed Including; The processor (108) is to change or stop the clock signal provided to the display refresh circuit in accordance with the displayed image. 9. The system of claim 8, further comprising a clock management function 570 coupled to and controlled by the processor 108, The clock management function 570 changes or stops the clock signal provided to the display refresh circuit 200 in response to a control signal from the processor 108 based on the displayed image. Device. 10. The processor 108 according to claim 8 or 9, wherein the processor 108 comprises timing parameters relating to the display 110, namely a vertical sync signal 420, a horizontal sync signal 430, a data signal 440 and a pixel rate. And determine the time to change or stop the clock signal for the display refresh circuit (200) based on a timing signal of at least one of the signals (450). 10. A video or image display apparatus according to claim 8 or 9, wherein the processor (108) determines a time period for changing or stopping the clock signal according to the type of image displayed. Display driver (111) configured to control the refresh rate of display device (110) according to claim 8.