KR20050043656A - Nonvolatile memory - Google Patents

Abstract

A nonvolatile memory is provided that can cope with two types of external supply voltages, stabilize the operation near the threshold voltage for switching the external supply voltage, and stabilize the operation during write / erase. A nonvolatile memory having a power supply circuit having a hysteresis comparator having two voltage levels as a threshold value, wherein when the external supply voltage rises, the detection signal becomes " H " The internal step-down circuit operates, generates and supplies an internal operating voltage of 2.2 V, and then detects 2.1 V, whereby the detection signal becomes "L", and supplies the external supply voltage as an internal operating voltage as it is, Even if the external supply voltage becomes unstable near 2.3V, since the detection signal remains " H ", the internal operating voltage does not change.

Description

Nonvolatile Memory {NONVOLATILE MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory, and more particularly to a technique effective for application to a nonvolatile memory such as a flash memory (flash EEPROM) corresponding to two types of external supply voltages.

According to the present inventors, the following techniques can be considered with respect to the nonvolatile memory.

For example, as a nonvolatile memory corresponding to two types of external supply voltages, the technique as described in patent document 1 is mentioned. The technique of this patent document 1 is comprised so that two types of supply voltages Vcc of 5V and 3V may be supplied from the exterior, and an internal circuit will operate | move with 3V internal operating voltage. The internal operating voltage is switched to a threshold value to step down the external supply voltage or to use it as it is. When 5V is supplied, it is stepped down to 3V, and when 3V is supplied, it is used as it is. In addition, the high voltage (Vpp) required for writing and erasing is also supplied from the outside.

[Patent Document 1]

Japanese Patent Application Laid-Open No. 5-12890

By the way, as a result of the present inventor's examination of the above description of the nonvolatile memory, the following has become clear.

For example, in the technique described in the patent document 1, since switching of two types of voltages is determined as a single threshold value, when operating at a voltage near the threshold value, the switching operation is frequent and the operation may become unstable. . That is, as shown in Figs. 10A and 10B, when the external supply voltage Vcc becomes unstable at about 4.0V near the threshold, the detection signal also has an external supply voltage of 4.0V. If it exceeds, it becomes "H", and in 4.0V or less, it becomes "L", and this "H" and "L" are repeated, and the external supply voltage is stepped down to generate an internal operating voltage or the external supply voltage is in that state. It becomes unstable to switch whether to use it as an internal operating voltage as it is.

In addition, since the high voltage Vpp is supplied from the outside, writing / erase is not considered.

Accordingly, it is an object of the present invention to provide a nonvolatile memory capable of stabilizing the operation in the vicinity of a threshold voltage for switching two external supply voltages.

Another object of the present invention is to provide a nonvolatile memory capable of stabilizing an operation during writing / erasing.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Among the inventions disclosed herein, an outline of representative ones will be briefly described as follows.

The present invention is applied to a nonvolatile memory corresponding to two types of external supply voltages, has a hysteresis comparator therein, and when the external supply voltage rises, the internal step-down circuit operates by detecting the first voltage level. And a power supply circuit which generates and supplies an internal operating voltage that is smaller than an absolute voltage level than one voltage level, and then supplies the external supply voltage as an internal operating voltage by detecting a second voltage level that is smaller than an absolute value than the first voltage level. will be.

In this nonvolatile memory, it has a voltage generation circuit which generates a write / erase / verify / read voltage based on the internal operating voltage supplied from the power supply circuit. In addition, the voltage generating circuit includes a plurality of stages of the charge pump circuit, and switches the number of stages of the charge pump circuit in correspondence with the first external supply voltage level and the second external supply voltage level smaller than the first external supply voltage level. It is. In particular, the first external supply voltage level is 3V, and the second external supply voltage level is 1.8V.

In addition, this nonvolatile memory has a memory array including multi-value memory cells that store multi-bit data in one memory cell, and is applied to multi-value nonvolatile memory.

<Example>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in all the drawings for demonstrating an Example, the same code | symbol is attached | subjected to the member which has the same function in principle, and the repeated description is abbreviate | omitted.

Example 1

First, an example of a schematic configuration of a nonvolatile memory of Embodiment 1 of the present invention will be described with reference to FIG. 1 shows a schematic configuration diagram of a nonvolatile memory.

The nonvolatile memory of the first embodiment is made of, for example, a flash memory, and includes an input / output circuit 5 composed of a multiplexer 1, a data input buffer 2, a control signal buffer 3, and a power supply circuit 4. A logic circuit 10 composed of a page address buffer 6, an input data controller 7, a column address counter 8, a read / write / erase controller 9, a memory array 11, and an X decoder ( 12) a memory circuit 17 comprising a data register 13, a Y gate 14, a Y decoder 15, a data output buffer 16, a read / write / erase voltage generation circuit 18, and the like. do.

In the input / output circuit 5, the multiplexer 1 inputs and outputs data through the data input / output terminals I / O1 to I / O8, and the input / output is switched in the multiplexer 1. The input data through this multiplexer 1 is output to the input data controller 7 of the logic circuit 10 via the data input buffer 2. Each control signal input terminal CE (chip enable), RE (lead enable), WE (write enable), WP (write protect), CLE (command latch enable), ALE (address) Each control signal is input through latch enable), PRE (power on auto read enable), and DSE (deep standby enable), and the control signal is read from the logic circuit 10 from the control signal buffer 3. It is output to the write / erase controller 9. Further, a control signal is output directly from the read / write / erase controller 9 via the control signal output terminal R / B (ready / busy). In each of these control signals, CE, RE, WE, WP, DSE and B are inverted signals as indicated by bars in the drawings.

In this input / output circuit 5, the power supply circuit 4 is supplied with an external supply voltage through the power supply terminal Vcc, and the power supply circuit 4 generates an internal operating voltage to generate the logic circuit 10, read / write / write the power supply circuit 4. The erase voltage generation circuit 18 is supplied. The input / output circuit 5 is also supplied with a ground voltage via the ground terminal Vss. For example, as an example, the external supply voltage supplied through the power supply terminal Vcc is two types of external supply voltage levels of 3V system and 1.8V system, and an internal operating voltage of 2.2V is generated for supply of any voltage level. And output.

In the logic circuit 10, a control signal is input from the multiplexer 1 and the read / write / erase controller 9 into the page address buffer 6, and the control signal of the page address is input to the X decoder of the memory circuit 17. It is output to (12). The data from the data input buffer 2 and the control signal from the read / write / erase controller 9 are input to the input data controller 7, and the control signal of the input data is supplied to the Y gate of the memory circuit 17. It is outputted to 14. The control signal is input from the read / write / erase controller 9 to the column address counter 8, and the column address is output to the Y decoder 15 of the memory circuit 17. The control signal is input to the read / write / erase controller 9 from the multiplexer 1 and the control signal buffer 3, and each control signal is input to each circuit in the logic circuit 10, the control signal buffer 3, The data output buffer 16 and the read / write / erase voltage generation circuit 18 in the memory circuit 17 are output.

In the memory circuit 17, multi-value memory cells for storing multi-bit data in one memory cell are arranged in an array at the intersection of word lines and bit lines. Each memory cell in the memory array 11 is arbitrarily selected by the X decoder 12, the Y gate 14, and the Y decoder 15, and reads data, writes data, and data for the selected memory cell. Is erased. These read, write, and erase data are temporarily stored in the data register 13, and the read data are temporarily stored in the data output buffer 16 and output.

Next, with reference to FIG. 2, an example of the schematic structure of a power supply system in a nonvolatile memory of the first embodiment will be described. 2 shows a schematic configuration diagram of a power supply system.

The power supply system is provided with an external supply voltage through the power supply terminal Vcc, and generates an internal operating voltage through the power supply circuit 4 from the external supply voltage, and the internal operating voltage is the logic circuit 10 or the read / write. / Erasing voltage generating circuit 18 is supplied. In this read / write / erase voltage generation circuit 18, the booster circuit boosts the internal operating voltage, and the booster circuit lowers the internal operating voltage, and various operations such as a read voltage, a write voltage, an erase voltage, and a verify voltage are performed. The voltage is generated and supplied to the memory circuit 17. In this memory circuit 17, the generated voltages are used for a read operation, a write operation, an erase operation, and the like. For example, as an example, the internal operating voltage is 2.2V, the read voltage is -5Vmax, the write voltage is -15Vmax, and the erase voltage is --18Vmax. In addition, the boosting circuit includes, for example, a charge pump circuit (FIG. 9, the external supply voltage Vcc becomes an internal operating voltage) as described in Embodiment 2 described later.

Next, an example of the threshold voltage distribution of the multi-value memory cell in the nonvolatile memory of the first embodiment will be described with reference to FIG. 3. 3 is an explanatory diagram of threshold voltage distribution of a multi-value memory cell, (a) shows a binary memory cell of a comparative example, and (b) shows a four-value memory cell.

A multi-value (four-value) memory cell can store multiple bits (two bits) of data in one memory cell, and the binary value (threshold voltage Vth distribution shown in Fig. 3A) has a value of "1". And "0"), as shown in Fig. 3B, from the smaller threshold voltage Vth distribution, "00", "01", "10", and "11". Four values of the distribution of can be stored.

In the write operation, for example, in the "00" distribution, the upper determination voltage is set to VWE1 and the lower determination voltage is set to VWV1, respectively. Similarly, in the "01" and "10" distributions, the upper determination voltages are VWE2 and VWE3, respectively. The lower determination voltage is set to VWV2 and VWV3, respectively, and the "11" distribution is set to the lower determination voltage of VWV4. Further, in the read operation, for example, between the read voltage Vr1, the "01" distribution, and the "10" distribution between the read voltage Vr2, the "10" distribution, and the "11" distribution between the "00" distribution and the "01" distribution. The read voltages Vr3 are set respectively.

4, an example of the configuration of the power supply circuit in the nonvolatile memory of the first embodiment will be described. 4 shows a circuit diagram of a power supply circuit.

The power supply circuit 4 is composed of an initial circuit 21, a voltage detection circuit 22, a constant voltage circuit 23, a switching circuit 24, and the like. In particular, the power supply circuit 4 has a hysteresis comparator therein and an external supply voltage rises. At the time of detection of the first voltage level, an internal step-down circuit comprising a constant voltage circuit 23 or the like is operated to generate and supply an internal operating voltage smaller than the first voltage level as an absolute value, and thereafter, the first voltage level. It is configured to supply the external supply voltage as the internal operating voltage by detecting the second voltage level which is smaller as the absolute value. For example, as an example, the first voltage level is set to 2.2V, the second voltage level is set to 2.1V, and the internal operating voltage is set to 2.2V.

The initial circuit 21 is a circuit for initializing an internal circuit when the power is turned on, and is connected to a power supply line of an external supply voltage, and the output line is a MOS transistor T3 of the voltage detection circuit 22, the constant voltage circuit 23, and the like. It is connected to the gate of T16 and used as a gate control signal.

The voltage detection circuit 22 is a circuit for detecting the voltage level of the external supply voltage. The voltage detection circuit 22 detects the voltage level at the high level when the level of the external supply voltage rises and at the low level when the level of the external supply voltage increases due to the hysteresis characteristics. The voltage detection circuit 22 constitutes a hysteresis comparator consisting of seven MOS transistors T1 to T7 connected between a power supply line of an external supply voltage and a ground line, and this output line is connected to an inverter IV1 of the switching circuit 24. Connected. In the MOS transistors T1 to T7 constituting this hysteresis comparator, the MOS transistor T3 is gate controlled by the output signal from the initial circuit 21, and the MOS transistor T5 is gate controlled by the signal from the switching circuit 24. .

The constant voltage circuit 23 is a circuit for generating a constant voltage for determining the step-down level, and is composed of six MOS transistors T11 to T16 connected between a power supply line and a ground line of an external supply voltage, and these MOS transistors T11 to T16. In, MOS transistor T16 is gate controlled by the output signal from initial circuit 21.

The switching circuit 24 is a circuit for switching whether to step down the external supply voltage or output as an internal operating voltage as it is. The switching circuit 24 includes two stages of inverters IV1 and IV2 and two MOS transistors T21 and T22. The output signal from the voltage detection circuit 22 is input to the inverter IV1, and is connected to the gate of the MOS transistor T5 of the voltage detection circuit 22 from the inverter IV2 of the subsequent stage. The output line of the inverter IV2 at the rear stage is connected to the gate of the MOS transistor T21 and used as a gate control signal. The gate of the MOS transistor T22 is connected to the connection node of the MOS transistor T11 and the MOS transistor T12 of the constant voltage circuit 23, and the gate is controlled.

5 and 6, an example of the operation of the power supply circuit will be described. 5 shows a waveform diagram of the operation of the voltage detection circuit in the power supply circuit. Fig. 6 is a waveform diagram of the operation of the power supply circuit, in which (a) shows the case where the external supply voltage is stepped down, and (b) does not conflict with the external supply voltage.

As shown in Fig. 5, as the external supply voltage, when the voltage level rises with the passage of time from the time of power supply and the voltage becomes constant at a predetermined time, the inside of the voltage detection circuit 22 is supplied. Since the node B exhibits a constant voltage characteristic with respect to the external supply voltage, when the detection voltage is exceeded, the output C of the voltage detection circuit 22 changes from "L" to "H". That is, the operation waveform of the internal node B of the voltage detection circuit 22 has a small rising angle compared with the external supply voltage, and thus becomes constant at a fast time. The detection voltage is a voltage at which the operating waveform of the internal node B intersects with the inversion voltage (node B input inverter).

In Fig. 6, 3.3V is supplied as an external supply voltage, and when this voltage is stepped down, as shown in Fig. 6A, the external supply voltage rises with the passage of time from when the power is turned on. The operating waveform becomes constant at 3.3V. In the supply state of the external supply voltage, the output A of the initial circuit 21 changes from " L " to " H " after a predetermined time has elapsed since the power supply is turned on, and then the operation waveform is the same as the external supply voltage. do. On the basis of these external supply voltages and the output A of the initial circuit 21, the output C of the voltage detection circuit 22 changes from "L" to "H" when the detection voltage is reached. The same operation waveform as the output A of the initial circuit 21 is obtained. Therefore, when the external supply voltage exceeds the detection voltage, the internal operating voltage output from the power supply circuit 4 is stepped down and output as the internal operating voltage.

In addition, when 1.8V is supplied as an external supply voltage and this voltage is not stepped down, as shown in FIG.6 (b), an external supply voltage rises with time passing from the time of power supply, The operating waveform becomes constant at 1.8V. In the supply state of the external supply voltage, the output A of the initial circuit 21 changes from " L " to " H " after a predetermined time has elapsed since the power supply is turned on, and then the operation waveform is the same as the external supply voltage. do. And based on these external supply voltages and the output A of the initial circuit 21, since the output C of the voltage detection circuit 22 does not reach a detection voltage, it maintains the state of "L". Therefore, since the external supply voltage does not exceed the detection voltage, the internal operating voltage output from the power supply circuit 4 is output as the internal operating voltage as it is.

Next, the stability of the operation of switching the external supply voltage in the power supply circuit will be described with reference to FIG. 7. Fig. 7 is an explanatory diagram of the stability of the operation of switching the external supply voltage, (a) shows the relationship between the voltage waveform and the detection signal, and (b) shows the generation of the internal operating voltage corresponding to the level of the detection signal.

In the first embodiment, as described above, the power supply circuit 4 has a hysteresis comparator having, for example, two voltage levels of 2.3 V and 2.1 V as threshold values, as shown in FIG. As shown in Fig. 2), when the external supply voltage rises, the detection signal becomes " H " upon detection of the first voltage level of 2.3 V, and the internal step-down circuit made up of the constant voltage circuit 23 and the like operate, thereby operating 2.2. Generate and supply an internal operating voltage of V. Thereafter, the detection signal becomes " L " by detecting the second voltage level of 2.1 V, and the external supply voltage is supplied as it is as the internal operating voltage. Therefore, even if the external supply voltage Vcc becomes unstable at around 2.3 V, since the detection signal remains " H ", even when the external supply voltage is stepped down and supplied internally, the switching circuit 24 is reduced. Since does not operate, the internal operating voltage does not fluctuate.

Therefore, according to the nonvolatile memory of the first embodiment, by employing a hysteresis comparator having two thresholds, the threshold voltage at the time of switching down the external supply voltage or supplying it as the internal operating voltage as it is is near. Since the unstable operation in NR is eliminated, the operation in the vicinity of the threshold voltage for switching the external supply voltage can be stabilized.

In addition, since the internal operating voltage does not fluctuate, the internal voltage at the time of write / erase boosting the internal operating voltage is stabilized, whereby the write / erase operation can be stabilized.

In addition, when the nonvolatile memory like the first embodiment is mounted in a memory card or the like and used as an external storage medium such as a personal computer or a portable device, and the battery operation is considered, the external supply is compared with the case where an AC power supply is used. Since the voltage tends to be unstable, the nonvolatile memory according to the present embodiment is particularly effective for applying to a dual voltage product of battery operation.

Example 2

First, with reference to FIG. 8, an example of schematic structure of a power supply system is demonstrated in the nonvolatile memory of Example 2 of this invention. 8 shows a schematic configuration diagram of a power supply system.

In the nonvolatile memory of the second embodiment, the difference from the first embodiment is that the internal operating voltage generated from the external supply voltage is supplied only to the logic circuit 10, and to the read / write / erase voltage generation circuit 18. The external supply voltage is supplied directly. Other configurations, functions of the circuits, and the like are the same as those in the first embodiment.

That is, in the power supply system in the nonvolatile memory of the second embodiment, an external supply voltage is supplied through the power supply terminal Vcc, and generates an internal operating voltage through the power supply circuit 4 from this external supply voltage, and this internal operation. The voltage is supplied to the logic circuit 10. In addition, the read / write / erase voltage generation circuit 18a is directly supplied with an external supply voltage, boosts the external supply voltage in the boosting circuit, and step-downs the external supply voltage in the step-down circuit, thereby reducing the read voltage, the write voltage, Various operation voltages such as an erase voltage and a verify voltage are generated and supplied to the memory circuit 17. In this memory circuit 17, the generated voltages are used for a read operation, a write operation, an erase operation, and the like.

Next, an example of the configuration of the charge pump circuit in the read / write / erase voltage generation circuit will be described with reference to FIG. 9. 9 shows a circuit diagram of a charge pump circuit in a read / write / erase voltage generation circuit.

The read / write / erase voltage generation circuit 18a has a built-in charge pump circuit for boosting the external supply voltage. The charge pump circuit is composed of a plurality of capacitor elements C1 to C8 and a plurality of switch circuits S0 to S8 and S4 ', and operates in response to an external supply voltage. It operates as a pump of the capacitors C1 to C4 and the four-stage configuration in which the switch circuits S1 to S3 and S4 'are paired, and when 1.8V is supplied, the boost stage is eight steps (each capacitor C1 to C8 and each It is comprised so that it may operate as a pump of 8 steps structure which pairs switch circuits S1-S8.

For example, during 3V operation, the control circuits Φa, / Φa and / Φa 'are activated, and the control signals Φb and / Φb are controlled so as to activate the four-stage switch circuits S1 to S3 and S4'. By outputting the voltage charged in the capacitors C1 to C4, the boost stage is operated as a pump of four stages. In the 1.8V operation, the control signals Φa, / Φa, φb, and / Φb are activated, and the control signals Φa 'are controlled so as to operate the eight-stage switch circuits S1 to S8 to operate the capacitors C1 to C8. The step-up stage is operated as an eight-stage pump by outputting the voltage charged in the second stage.

Therefore, according to the nonvolatile memory of the second embodiment, the same effects as those of the first embodiment can be obtained. In particular, the logic circuit 10 operates stably by fixing the operating voltage and at the same time read / write / erase voltage. The efficiency of the charge pump circuit can be raised by directly inputting the external supply voltage to the generation circuit 18a.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the Example, this invention is not limited to the said Example, Of course, it can change variously in the range which does not deviate from the summary.

For example, in the above embodiment, although the flash memory is described as an example of the nonvolatile memory, the present invention can also be applied to a nonvolatile memory such as an EEPROM.

Among the inventions disclosed herein, the effects obtained by the representative ones are briefly described as follows.

(1) By employing a hysteresis comparator having two threshold values of the first and second voltage levels, it is possible to determine whether to step down the external supply voltage or to supply it as an internal operating voltage as it is. The unstable operation can be eliminated to stabilize the operation near the threshold voltage for switching the external supply voltage.

(2) By generating the write / erase voltage based on the internal operating voltage, in the nonvolatile memory of the single power supply operation which does not supply high voltage externally, in particular, the internal voltage at the time of writing / erasing is stabilized, and therefore at the time of writing / erasing It can stabilize the operation.

1 is a schematic structural diagram showing a nonvolatile memory of Embodiment 1 of the present invention;

Fig. 2 is a schematic structural diagram showing a power supply system in the nonvolatile memory of Embodiment 1 of the present invention.

3A and 3B are explanatory diagrams showing threshold voltage distributions of multi-value memory cells in the nonvolatile memory according to the first embodiment of the present invention.

Fig. 4 is a circuit diagram showing a power supply circuit in the nonvolatile memory of Embodiment 1 of the present invention.

Fig. 5 is a waveform diagram showing the operation of the voltage detection circuit in the power supply circuit in the nonvolatile memory of Embodiment 1 of the present invention.

6A and 6B are waveform diagrams showing the operation of the power supply circuit in the nonvolatile memory according to the first embodiment of the present invention.

7A and 7B are explanatory diagrams showing the stability of an operation of switching an external supply voltage in the nonvolatile memory according to the first embodiment of the present invention.

Fig. 8 is a schematic structural diagram showing a power supply system in the nonvolatile memory of Embodiment 2 of the present invention.

Fig. 9 is a circuit diagram showing a charge pump circuit in a read / write / erase voltage generation circuit in the nonvolatile memory of Embodiment 2 of the present invention.

10A and 10B are explanatory diagrams showing instability of an operation of switching an external supply voltage in a nonvolatile memory of a comparative example examined as a premise of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: multiplexer

2: data input buffer

3: control signal buffer

4: power circuit

5: input / output circuit

6: page address buffer

7: input data controller

8: column address counter

9: read / write / erase controller

10: logic circuit

11: memory array

12: X decoder

13: data register

14: Y gate

15: Y decoder

16: data output buffer

17: memory circuit

18, 18a: read / write / erase voltage generation circuit

21: initial circuit

22: voltage detection circuit

23: constant voltage circuit

24: switching circuit

Claims (5)

Has a hysteresis comparator therein, and when the external supply voltage rises, the internal step-down circuit operates by detection of the first voltage level, generates and supplies an internal operating voltage smaller than the first voltage level as an absolute value, and thereafter. And a power supply circuit for supplying an external supply voltage as an internal operating voltage by detecting a second voltage level that is smaller than the first voltage level as an absolute value. The method of claim 1, And a voltage generation circuit for generating a write / erase / verify / read voltage based on the internal operating voltage supplied from the power supply circuit. The method of claim 2, The voltage generation circuit includes a plurality of stage charge pump circuits, And the number of stages of the charge pump circuit is switched in correspondence to a first external supply voltage level and a second external supply voltage level smaller than the first external supply voltage level. The method of claim 3, And the first external supply voltage level is a 3V system, and the second external supply voltage level is a 1.8V system. The method of claim 1, A nonvolatile memory, characterized by having a memory array consisting of multivalued memory cells storing multiple bits of data in one memory cell.