KR20050012006A - Method of manufacturing pmosfet device including plug implantation using decaborane ion beam - Google Patents

Abstract

The present invention provides a method of manufacturing a pMOS transistor capable of reducing the manufacturing cost while having electrical properties of a low contact resistance similar to that of plug ion implantation using a mixed ion implantation method of ₄₉ BF ₂ ⁺ ions and ₁₁ B ⁺ ions. According to an aspect of the present invention, there is provided a method of manufacturing a PMOS transistor, the method including forming an insulating film on a semiconductor substrate on which a p-type source / drain is formed, and contact holes in the insulating film to expose a portion of the p-type source / drain. Forming a plug ion implantation region by ion implanting boron ions extracted from decarborene (B ₁₀ H ₁₄ ) molecules into the semiconductor layer exposed to the bottom of the contact hole; and forming a plug ion implantation region in the contact layer. Filling the hole.

Description

Manufacturing method of PMOS transistor including plug ion implantation using decaborene {METHOD OF MANUFACTURING PMOSFET DEVICE INCLUDING PLUG IMPLANTATION USING DECABORANE ION BEAM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of manufacturing a pMOSFET that includes plug implantation.

In the memory device of 0.15㎛ or more, the contact hole connecting the source / drain junction of the pMOS device to the metal wiring is 0.04㎛ ² or more, and the contact resistance between the metal wiring and the source / drain junction required by the conventional contact hole forming method is required. However, in the highly integrated memory device having a thickness of 0.15 μm or less, the contact hole size becomes very small, such as 0.04 μm ² or less, so that the contact resistance may be secured by performing an additional ion implantation process after forming the source / drain junction and forming the contact hole.

This additional ion implantation process is also referred to as a plug implantation process. In general, a contact resistance of a junction is formed before forming a metal wiring after forming a contact hole in a source / drain junction in a metal contact formation process of a semiconductor device. In order to improve the performance, an additional ion implantation process is performed with the same type of dopant as the source / drain junction.

For example, in the case of a pMOS transistor, the conventional plug ion implantation is used to compensate for etch damage of a junction when forming a contact hole in a source / drain junction, to improve junction leakage current due to substrate loss during etching, and to form silicide during a metallization process. the dopant loss and ₄₉ BF ₂ ⁺ ions, or ₁₁ B ⁺ ions in the source / drain junctions for the purpose of preventing an increase in contact resistance of the silicide and hence injection.

However, the plug ion implantation process using only ₄₉ BF ₂ ⁺ ions is advantageous in terms of suppressing diffusion of boron (B) ions by fluorine (F) ions. Since silicon compounds and precipitates are formed to prevent uniform formation of the silicide film, it becomes a factor of increasing contact resistance and nonuniformity thereof.

In addition, the plug ion implantation process using only ₁₁ B ions has a problem of deeply forming source / drain junctions due to channeling phenomenon of boron (B) ions having a small mass and transient enhanced diffusion (TED).

Therefore, in the case of implanting ₄₉ BF ₂ ⁺ ions or ₁₁ B ⁺ ions, it is not suitable for application by a method of obtaining a desired low contact resistance in a highly integrated device.

On the other hand, ₁₁ B ⁺ ions to only improve the issue of when to inject the amorphous speech line for implanting B ⁺ ions was ₁₁ lines amorphous by implanting germanium (Ge) or silicon (Si) have been proposed.

However, the preamorphization method in which boron (B) is ion implanted with low energy after preamorphous crystallization by ion implantation of germanium (Ge) or silicon (Si) is heavily contaminated with the ion source region of the ion implanter during germanium ion implantation or silicon ion implantation. As a result, frequent maintenance is required, and the production cost of low energy boron ions is incurred due to the high cost of device manufacturing, it is not applicable to mass production of memory semiconductor devices.

To improve this problem, mixed implantation of ₄₉ BF ₂ ⁺ and ₁₁ B ⁺ ions, that is, mixed ion implantation with low fluorine (F) implantation, is used for source / drain junction ion implantation or plug ion implantation. How to do this has been proposed.

1A to 1C are cross-sectional views illustrating a method of manufacturing a pMOS transistor using a mixed ion implantation method of ₄₉ BF ₂ ⁺ ions and ₁₁ B ⁺ ions according to the prior art.

As shown in FIG. 1A, after forming a field oxide film 12 as an isolation layer in a predetermined region of the semiconductor substrate 11, an n-type well 13 defining a pMOS region is formed in the semiconductor substrate 11. A gate structure including the gate insulating film 14 and the gate electrode 15 is formed on a selected region of the semiconductor substrate 11 by a known method.

Next, after the insulating layer is deposited on the semiconductor substrate 11, the entire surface is etched to form spacers 16 on both side walls of the gate electrode 15.

Next, a p-type dopant, for example, ₄₉ BF ₂ ⁺ ions or ₁₁ B ⁺ ions is implanted into the semiconductor substrate 11 outside the spacer 16 to form the p-type source / drain junction 17. In this case, the p-type source / drain junction 17 may have a source-drain extension (SDE) structure, and the SDE structure may be formed by ion implantation before forming the spacer 16.

Thereafter, after the interlayer insulating film 18 is deposited on the semiconductor substrate 11, a photosensitive film pattern 19 for exposing the p-type source / drain junction 17 on the interlayer insulating film 18 is known. Form by Thereafter, the interlayer insulating layer 18 is etched using the photoresist pattern 19 as an etch mask to form the contact hole 20. In this case, as an etching process for forming the contact hole 20, the surface of the p-type source / drain junction 17 may be partially damaged or the surface layer of the semiconductor substrate 11 may be damaged.

Next, in order to secure the contact resistance while healing the damaged portion of the p-type source / drain junction 17, plug ion implantation is performed to form the plug ion implantation region 21. First, the p-type source / drain junction is primarily used. by implanting BF ₂ ⁺ ions ₄₉ to 17, then screen the surface of an amorphous p-type source / drain junction (17).

Then, as shown in FIG. 1B, again ₁₁ B ⁺ ions are implanted into the source / drain junction 17 again. As a result, the plug ion implantation region 21 is a region in which ₄₉ BF ₂ ⁺ ions and ₁₁ B ⁺ ions are mixed and implanted.

Thereafter, as shown in FIG. 1C, after the photosensitive film pattern 19 is removed, a laminated film of the silicide film 22 and the diffusion barrier metal film 23 in contact with the exposed p-type source / drain junction 17 is formed. After that, the metal wiring 24 is formed. For example, the silicide film 22 is a titanium silicide film (Ti-silicide) formed by depositing a titanium film and reacting with the semiconductor substrate 11, and the diffusion preventing metal film 23 is a titanium nitride film (TiN) or titanium. It is a laminated film of the film Ti and the titanium nitride film TiN.

The above-described prior art plug ion some of the total dose required for each hour infusion ₄₉ BF ₂ ⁺ ions previously implanted into and to minimize channeling phenomenon during ion implantation of a subsequent ₁₁ B ⁺ ions in the amorphous layer or a crystal defect layer Is formed first, and then the remaining amount of implantation required is ionized with ₁₁ B ⁺ ions to satisfy the principle. The mixed ion implantation method is designed as a countermeasure against preamorphization using germanium (Ge) or silicon (Si) ions, and is known to improve productivity compared to preamorphization.

The above-described mixed ion implantation method of ₄₉ BF ₂ ⁺ ion and ₁₁ B ⁺ ion forms a source / drain junction or plug ion implantation region having a low concentration of fluorine, which is advantageous for the formation of a silicide layer forming dopant activation and contact, As a result, the contact resistance is lowered and the on-current of the pMOS device is increased.

However, the mixed ion implantation method of ₄₉ BF ₂ ⁺ ion and ₁₁ B ⁺ ion still retains fluorine, which causes fluorine bubbles and precipitates of fluorine compounds due to fluorine remaining in the subsequent heat treatment process. There is a problem. In addition, if fluorine remains, there is a problem that the formation of the silicide film formed on the source / drain junction is prevented, resulting in uneven contact resistance.

In addition, the mixed ion implantation method of ₄₉ BF ₂ ⁺ ion and ₁₁ B ⁺ ion requires a low energy ion implantation of 5 keV or less during the subsequent implantation process, ₁₁ B ⁺ ion, and thus still has a disadvantage in that the manufacturing cost increases.

The present invention has been made to solve the above problems of the prior art, to provide a method of manufacturing a pMOS transistor that can reduce the manufacturing cost while having an electrical characteristic of a low contact resistance similar to the mixed ion implantation method. There is this.

1A to 1C are cross-sectional views illustrating a method of manufacturing a pMOS transistor using a mixed ion implantation method of ₄₉ BF ₂ ⁺ ions and ₁₁ B ⁺ ions according to the prior art.

2 is a graph showing the boron concentration distribution in the substrate when ₁₁ B ⁺ , ₄₉ BF ₂ ⁺ , B ₁₀ H ₁₄ ⁺ are ion-implanted into the silicon substrate,

3 is a graph showing the boron concentration distribution when ion implantation of B ₁₀ H ₁₄ ⁺ and ₄₉ BF ₂ ⁺ at about the same depth;

4 is a process flowchart showing a manufacturing method of a pMOS transistor according to a first embodiment of the present invention;

5 is a process flowchart showing the manufacturing method of the pMOS transistor according to the second embodiment of the present invention;

6 is a process flowchart showing a manufacturing method of a pMOS transistor according to a third embodiment of the present invention;

7 is a process flowchart showing the manufacturing method of a pMOS transistor according to a fourth embodiment of the present invention;

8A to 8D are cross-sectional views illustrating a method of manufacturing the pMOS transistor according to FIG. 4;

9 is a view comparing the contact resistance according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 field oxide film

33: n-type well 34: gate insulating film

35 gate electrode 36 spacer

37: p-type source / drain junction 38: interlayer insulating film

39: photosensitive film pattern 40: contact hole

41 plug ion implantation region 42 metal film for silicide formation

43 diffusion barrier metal film 44 silicide film

45: metal wiring

A method of manufacturing a PMOS transistor of the present invention for achieving the above object comprises forming an insulating film on a semiconductor substrate on which a p-type source / drain is formed, and contact holes in the insulating film to expose a portion of the p-type source / drain. Forming a plug ion implantation region by ion implanting boron ions extracted from the decarborene molecule into the semiconductor layer exposed to the bottom of the contact hole, and filling the contact hole with a conductive film; Characterized in that, the step of forming the plug ion implantation region is decarborene (B₁₀H₁₄Boron extracted from Ion implantation, with ion implantation energy of 5keV ~ 40keV, ion implantation of 1.0E14ions / cm²-1.0E15ions / cm²It is characterized in that the ion implantation, the p-type source / drain₄₉BF₂ ⁺ion,₁₁B⁺ion,₄₉BF₂ ⁺With ion₁₁B⁺It is characterized in that the ion is selected from a mixture of ions and boron ions extracted from the decarborene molecule and formed by ion implantation.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

Decaborane, an ion implantation source to be applied in an embodiment of the present invention described below, is a large molecule having a molecular formula of B ₁₀ H ₁₄ , and when ionized, provides molecular ions including 10 boron atoms. Decaborene is a compound that is a good source of boron implants.

In particular, since the decaborene ion beam can inject 10 times the amount of boron ion per unit of current that can be injected by a monoatomic boron ion beam, these decarborene ion beams can be used to produce high implantation / Suitable for low energy ion implantation process.

In addition, since the decaborene ion beam is split into each boron atom of approximately 1/11 of the original beam energy at the workpiece surface to be ion implanted, the decaborene ion beam can be transferred at 11 times the energy of the boron ion beam energy having an equivalent atomic amount. When the boron ion implantation is almost the same ion implantation depth. Due to this feature, decarborene ion beam has an advantage that it can be used without difficulty of low energy ion beam extraction.

When ionizing the decarborene molecules (B ₁₀ H ₁₄ ) described above and ionizing large ions in the form of B ₁₀ H ₁₄ ⁺ , the ion implantation energy of 11 times higher than the boron ion implantation method can be used. Not only can beam current be secured, but also 10 boron per decarborene molecule ions can achieve the same doping effect with boron ion implantation by about 1/10 lower than the boron ion implantation method and ₄₉ BF ²⁺ ion implantation method.

2 is a graph showing the boron concentration distribution in the substrate when ₁₁ B ⁺ , ₄₉ BF ₂ ⁺ and B ₁₀ H ₁₄ ⁺ are ion-implanted onto the silicon substrate, respectively.

In Figure 2, the abscissa represents the depth in the substrate and the ordinate represents the boron concentration. The curves p1, p2 and curve p3 represent the cases of ₁₁ B ⁺ , ₄₉ BF ₂ ⁺ and B ₁₀ H ₁₄ ⁺ . Here, the ion implantation of boron ion is composed of 5keV ion implantation energy and 1 × 10 ¹⁴ / cm ² dose, and the ₄₉ BF ₂ ⁺ ion implantation is 5keV ion implantation energy and 1 × 10 ¹⁴ / cm ² dose The ion implantation of B ₁₀ H ₁₄ ⁺ proceeded with an ion implantation energy of 5 keV and a dose of 1 × 10 ¹³ / cm ² .

Upon implantation of ₁₁ B ⁺ , boron ions are implanted deep into the substrate and the peak value of the profile is located at a position deeper than 10 nm. ₄₉ In the case of BF ₂ ⁺ B ₁₀ H and when ion implantation of ₁₄ ⁺ is commonly located at a peak value of about 3nm profile, more rapidly reduce the concentration of boron in the deep position.

In addition, curves p1 and p2 show different reduction profiles, curves p3 have a narrower distribution of boron, and when comparing curves p1 and p2, the peak height of curve p1 is higher than the peak height of curve p2. This means that the same boron ion implantation can be obtained at an implantation rate of 1/10 of the ₄₉ BF ₂ ⁺ ion implantation dose when implanting B ₁₀ H ₁₄ ⁺ .

B ₁₀ H ₁₄ ⁺ and ₄₉ BF ₂ ⁺ ions were implanted with the same ion implantation energy. When ion implantation is performed at the same ion implantation energy, it can be seen that B ₁₀ H ₁₄ ⁺ can be implanted more shallowly than ₄₉ BF ₂ ⁺ . In addition, when implanting boron at the same depth, it can be seen that the ion implantation energy for B ₁₀ H ₁₄ ⁺ can be set higher than the ion implantation energy of ₄₉ BF ₂ ⁺ .

3 is an experimental result when ion implantation of B ₁₀ H ₁₄ ⁺ and ₄₉ BF ₂ ⁺ at about the same depth, the abscissa represents the depth in the substrate, and the ordinate represents the boron concentration. Curve p4 is the result of ion implantation of B ₁₀ H ₁₄ ⁺ with 10keV ion implantation energy and 1 × 10 ¹³ / cm ² , and curve p5 is 5keV ion implantation energy and 1 × 10 ¹⁴ / cm ² . This is the result of ion implantation of ₄₉ BF ₂ ⁺ as the injection amount. As shown in the figure, curve p4 and curve p5 show the same distribution. As a result, when boron is ion-implanted using B ₁₀ H ₁₄ ⁺ as an ion implantation source, the ion implantation energy is doubled as ion implantation energy at the time of ion implantation using ₄₉ BF ₂ ⁺ as an ion implantation source.

Hereinafter, a method for forming a contact of a semiconductor device using decarborene ion implantation will be described with reference to the accompanying drawings.

4 is a process flowchart illustrating a method of manufacturing a pMOS transistor according to a first embodiment of the present invention.

As shown in FIG. 4, the field oxide film forming process (S1), the n-type well forming process (S2), the gate insulating film and gate electrode forming process (S3), the p-type source / drain junction forming process (S4), and the contact Hole formation process (S5), decaborene (B₁₀H₁₄Boron Extracted from Molecules The plug ion implantation process using ions (S6), the activation heat treatment process (S7), the silicide film and the anti-diffusion metal film forming process (S8), metal wiring forming process (S9).

In FIG. 4, the field oxide film formation process S1 is performed through the STI or LOCOS method, and the n-type well formation process S2 is performed by ion implantation of an n-type dopant such as phosphorus (P), and a gate insulating film and a gate. In the electrode forming process (S3), the gate insulating film is selected from a thermal oxide film, an oxynitride film, a high dielectric film, or a laminated film of an oxide film / high dielectric film, and the gate electrode is formed of a polysilicon film, a polysilicon film, and a silicide layer. One of a lamination film, a lamination film of a polysilicon film and a metal film, a silicon germanium film, a lamination film of a silicon germanium film and a metal film, or a metal film is selected and used.

The p-type source / drain junction formation process S4 is selected from ₄₉ BF ₂ ⁺ ion implantation method, ₁₁ B ⁺ ion implantation method, and mixed ion implantation method of ₄₉ BF ₂ ⁺ ion and ₁₁ B ⁺ ion.

In the contact hole forming process S5, a portion of the p-type source / drain junction is exposed by etching the interlayer insulating layer.

And decaboren (B₁₀H₁₄Boron Extracted from Molecules The plug ion implantation process using ions (S6) is performed by decaborene (B) at the exposed p-type source / drain junction.₁₀H₁₄Boron extracted from As a process of forming a plug ion implantation region by ion implantation of ions, as described above,₄₉BF₂ ⁺With ion₁₁B⁺It is a plug ion implantation method that can reduce manufacturing cost while having low contact resistance electrical characteristics similar to the mixed ion implantation method of ions.

In addition, the activation heat treatment process S7 is a heat treatment process for electrically activating the dopant after the plug ion implantation process, and releases fluorine (F) ions implanted during the p-type source / drain junction formation process (S4) during heat treatment to the outside. It also works.

In addition, the silicide film and the diffusion preventing metal film forming process (S8) is a process of forming a silicide film that is easy to form an ohmic contact, and forming a diffusion barrier metal film that prevents mutual diffusion between the p-type source / drain junction and the metal wiring. And a heat treatment process for forming the silicide film.

Finally, the metallization process (S9) is a process of forming a metallization connected to the p-type source / drain junction, and patterning after depositing aluminum, aluminum alloy, tungsten, copper or copper alloy on the diffusion barrier metal film To form.

5 is a process flowchart illustrating a method of manufacturing a pMOS transistor according to a second embodiment of the present invention.

As shown in FIG. 5, a field oxide film forming process (S11), an n-type well forming process (S12), a gate insulating film and a gate electrode forming process (S13), and decaborene (B).₁₀H₁₄P-type source / drain junction formation process (S14), contact hole formation process (S15), and decaborene (B) using boron ions extracted from the molecule₁₀H₁₄Boron Extracted from Molecules The plug ion implantation process using ions (S16), the activation heat treatment process (S17), the silicide film and the anti-diffusion metal film forming process (S18), metal wiring forming process (S19).

In FIG. 5, the field oxide film forming process S11 is performed through the STI or LOCOS method, and the n-type well forming process S12 is performed by ion implantation of an n-type dopant such as phosphorus (P), and a gate insulating film and a gate. In the electrode forming process (S13), the gate insulating film is selected from a thermal oxide film, a nitride oxide film, a high dielectric film, or a laminated film of an oxide film / high dielectric film, and the gate electrode is a polysilicon film, a polysilicon film and a silicide laminated film, One of a polysilicon film and a metal film laminated film, a silicon germanium film, a silicon germanium film and a metal film laminated film, or a metal film is selected and used.

In addition, the p-type source / drain junction forming process (S14) may include a first embodiment selected from ₄₉ BF ₂ ⁺ ion implantation method, ₁₁ B ⁺ ion implantation method, and mixed ion implantation method of ₄₉ BF ₂ ⁺ ion and ₁₁ B ⁺ ion. different. That is, an ion implantation method containing no fluorine, for example, boron ions extracted from the decarborene (B ₁₀ H ₁₄ ) molecule is ion implanted to form a p-type source / drain junction.

In the contact hole forming process S15, a portion of the p-type source / drain junction is exposed by etching the interlayer insulating layer.

And decaboren (B₁₀H₁₄Boron Extracted from Molecules The plug ion implantation process using ions (S16) is performed on decaborene (B) in the exposed p-type source / drain junction.₁₀H₁₄Boron extracted from A process of forming a plug ion implantation region by implanting ions.

In addition, the activation heat treatment process (S17) is a heat treatment process for electrically activating the dopant after the plug ion implantation process.

In addition, the silicide film and the diffusion barrier metal film forming process (S18) is a process of forming a silicide film that is easy to form an ohmic contact, and forming a diffusion barrier metal film that prevents mutual diffusion between the p-type source / drain junction and the metal wiring. And a heat treatment process for forming the silicide film.

Finally, the metallization process (S19) is a process of forming a metallization connected to the p-type source / drain junction, and patterning after depositing aluminum, aluminum alloy, tungsten, copper or copper alloy on the diffusion barrier metal film To form.

Unlike the first embodiment, the second embodiment described above proceeds with ion implantation of boron ions extracted from decarborene molecules for both ion implantation and plug ion implantation for forming a p-type source / drain junction.

As described above, the use of decarborene for p-type source / drain junction and plug ion implantation fundamentally prevents problems due to fluorine content in the subsequent silicide film formation process, resulting in better contact resistance than the first embodiment. Become.

6 is a process flowchart illustrating a method of manufacturing a pMOS transistor according to a third embodiment of the present invention.

Referring to FIG. 6, a field oxide film forming process (S21), an n-type well forming process (S22), a gate insulating film and a gate electrode forming process (S23), a p-type source / drain junction forming process (S24), and contact hole formation Course (S25), decaborene (B₁₀H₁₄Boron extracted from A plug ion implantation process using ions (S26), a silicide film (a dopant injected during the plug ion implantation process is activated during heat treatment), a diffusion barrier metal film formation process (S27), and a metal wiring formation process (S28).

The third embodiment shown in Figure 6 is the same as the first embodiment, the plug ion implantation process (S26) is decaboren (B₁₀H₁₄Boron extracted from It proceeds using ions.

If there is a difference, the first embodiment decaborene (B₁₀H₁₄Boron extracted from After the plug ion implantation process using ions (S6), the activation heat treatment process (S7) was performed, but in the third embodiment, the dopant implanted during the plug ion implantation process during the formation of the silicide film and the diffusion barrier metal film (S27) is activated. . That is, the dopant implanted during the plug ion implantation process is activated during the heat treatment to form the silicide layer.

Therefore, while the third embodiment realizes the effect of using decarborene molecules for the plug ion implantation, unlike the first embodiment, the activation heat treatment process is omitted, and thus an additional effect of reducing the heat burden caused by a plurality of heat treatment processes is obtained. Get

7 is a process flowchart illustrating a method of manufacturing a pMOS transistor according to a fourth embodiment of the present invention.

Referring to FIG. 7, a field oxide film forming process (S31), an n-type well forming process (S32), a gate insulating film and a gate electrode forming process (S33), and decaborene (B).₁₀H₁₄P-type source / drain junction formation process (S34), contact hole formation process (S35), and decaborene (B) using boron ions extracted from molecules₁₀H₁₄Boron Extracted from Molecules A plug ion implantation process using ions (S36), a silicide film (the dopant injected during the plug ion implantation process is activated during heat treatment), a diffusion barrier metal film formation process (S37), and a metal wiring formation process (S38).

In the fourth embodiment shown in FIG. 7, the p-type source / drain junction formation process S34 and the plug ion implantation process S36 are performed in the same manner as in the second embodiment.₁₀H₁₄Boron extracted from It proceeds using ions.

If there is a difference, the second embodiment decaborene (B₁₀H₁₄Boron extracted from After the plug ion implantation process using the ion (S16), the activation heat treatment process (S17) was performed, but in the third embodiment, the dopant implanted during the plug ion implantation process is activated during the silicide film and the diffusion barrier metal film formation process (S37). . That is, the dopant implanted during the plug ion implantation process is activated during the heat treatment to form the silicide layer.

Therefore, while the fourth embodiment realizes the effect of using the decarborene molecule for the plug ion implantation, and unlike the second embodiment, the activation heat treatment process is omitted, and thus the additional effect of reducing the heat burden caused by the multiple heat treatment processes Get

Decaborene (B in FIGS. 4 to 7)₁₀H₁₄Boron extracted from In the plug ion implantation process using ions, the ion implantation energy is 5keV ~ 40keV, and the ion implantation amount is 1.0E14ions / cm²-1.0E15ions / cm²to be.

As mentioned above, decaborene (B₁₀H₁₄Boron extracted from Since ions are implanted and plug ions are implanted, fluorine is not contained at all. This₄₉BF₂ ⁺Ion or₁₁B⁺There is no fluorine bubble and precipitates of fluorine compounds in the subsequent heat treatment process caused by excessive fluorine injection when formed by implanting ions. It essentially prevents non-uniformity of contact resistance.

Furthermore, as in the second and fourth embodiments, the use of p-type source / drain junction and plug ion implantation to decaborene fundamentally prevents problems due to fluorine content in the subsequent silicide film formation process. The contact resistance is further excellent as compared with the first and third embodiments.

8A to 8D are cross-sectional views illustrating a method of manufacturing the pMOS transistor according to FIG. 4.

As shown in FIG. 8A, a field oxide film 32 as an isolation layer is formed in a predetermined region of the semiconductor substrate 31 by using a shallow trench isolation (STI) method or a local oxidation of silicon (LOCOS) method.

Next, an n-type dopant such as phosphorous (P) is ion-implanted into the semiconductor substrate 31 to form an n-type well 33, and then a gate insulating film 34 and a gate electrode on the semiconductor substrate 31 are formed. (35) is formed.

At this time, the gate insulating film 34 may be selected from a thermal oxide film, an oxynitride film, a high dielectric film, or a laminated film of an oxide film / a dielectric film. The gate electrode 35 is selected from among a polysilicon film, a polysilicon film and a silicide lamination film, a polysilicon film and a metal film lamination film, a silicon germanium film, a silicon germanium film and a metal film lamination film, or a metal film. In this case, a hard mask such as a silicon nitride film may be included on the top.

After the insulating layer is deposited on the semiconductor substrate 31, the entire surface is etched to form spacers 36 on both sidewalls of the gate electrode 35. At this time, the insulating layer forming the spacer 36 uses a silicon nitride film, a silicon oxide film, or a combination of a silicon nitride film and a silicon oxide film.

Next, a p-type dopant, for example, ₄₉ BF ₂ ⁺ ions or ₁₁ B ⁺ ions is implanted into the semiconductor substrate 31 outside the spacer 36 to form the p-type source / drain junction 37. At this time, the p-type source / drain junction 37 may have an SDE structure, and the formation of the SDE structure follows a known method. In the case of a buried channel pMOS device, a source / drain junction without SDE may be used.

As shown in FIG. 8B, an interlayer insulating film 38 is deposited on the semiconductor substrate 31. In this case, the interlayer insulating film 38 is a film in which a BPSG (Bop Phospho Silicate Glass) for gap fill, a High Density Plasma Chemical Vapor Deposition (HDP CVD) film, or a low dielectric constant film is stacked on the silicon oxide film or the silicon nitride film.

Next, a photosensitive film pattern 39 for exposing the p-type source / drain junction 37 on the interlayer insulating film 38 is formed by a known photolithography method.

Next, the interlayer insulating layer 38 is etched using the photoresist pattern 39 as an etch mask to form the contact hole 40. In this case, the surface of the p-type source / drain junction 37 may be partially damaged by an etching process for forming the contact hole 40.

Next, plug ion implantation is performed in order to secure contact resistance while healing the damage site of the p-type source / drain junction 37. The decaborene molecule (B ₁₀ H ₁₄ ) is applied to the p-type source / drain junction 37. The boron ions extracted from the cavities are implanted at an ion implantation energy of 5 keV to 40 keV and an implantation amount of 1.0E14ions / cm ^{2 to} 1.0E15ions / cm ² to form a plug ion implantation region 41.

As shown in FIG. 8C, after the photoresist pattern 39 is removed, the plug ion implantation region 41a is activated by performing annealing to electrically activate the dopant injected into the plug ion implantation region 41. To form.

At this time, the activation heat treatment of the dopant proceeds at a temperature for activating the dopant injected into the plug ion implantation region 41 while being lower than 1414 ° C, which is the melting point of silicon, for example, 750 ° C to 1100 ° C. During this heat treatment, the dopants implanted in the plug ion implantation region 41 are electrically activated. Preferably, the heat treatment uses rapid heat treatment (RTP) or spike rapid heat treatment (Spike-RTP). For example, rapid heat treatment progresses in the range of 750 degreeC-1050 degreeC, and spike rapid heat processing progresses in the range of 850 degreeC-1100 degreeC.

Since the plug ion implantation region 41 is formed by ion implantation of boron ions extracted from the decaborene molecule as described above, fluorine (F) is not fundamentally contained, and the p-type source / drain junction is formed through such heat treatment. Fluoride remaining in the inside is released to the outside. As a result, since the fluorine (F) compound is not disturbed during the subsequent silicide film formation, the contact resistance is uniform.

As a result, the plug ion implantation region 41a activated through heat treatment is modified into an electrically activated p ⁺ doped layer while forming stable bonds between the implanted dopants and silicon. That is, boron (B) and silicon (Si) form a stable bond during the heat treatment.

As shown in FIG. 8D, the silicide forming metal film 42 and the diffusion barrier metal film 43 are sequentially deposited on the interlayer insulating film 39 including the contact hole 41, and then the plug ion implantation region 41a is formed. The silicide film 44 is formed by inducing a reaction of the constituent elements constituting the silicon atom 42 with the silicon atom of ().

Here, as the silicide-forming metal film 42, a titanium film (Ti), a titanium silicon film (TiSi _x ), a cobalt film (Co), a nickel film (Ni), or a platinum film (Pt) is used as is known. For example, a titanium nitride film (TiN) or a tungsten nitride film (WN) is used as the diffusion barrier metal film 43 that prevents the interaction between the metal wiring and the p-type source / drain junction 37.

For example, when the titanium film Ti is used as the silicide formation metal film 42 and the titanium nitride film TiN is used as the diffusion barrier metal film 43, the silicide film 44 is formed at 650 ° C to 900. This is possible by carrying out Rapid Thermal Process (RTP) at ° C. During the rapid thermal treatment (RTP) process, the silicon atoms forming the plug ion implantation region 41a and the titanium of the titanium film, which is the silicide-forming metal film 42, react to form a titanium silicide film (Ti-silicide). As described above, the silicide layer 44 facilitates the formation of ohmic contacts used for the purpose of reducing contact resistance.

Meanwhile, the titanium nitride film TiN serves as the diffusion preventing metal film 43 and prevents the titanium film Ti from being exposed to the atmosphere, thereby forming titanium oxide from the formation of a natural oxide film and the generation of pollutant sources. It also serves to protect the film (Ti).

After the silicide film 44 is formed, a metal film such as aluminum (Al), aluminum alloy, tungsten (W), copper (Cu) or copper alloy is deposited on the diffusion barrier metal film 43, and then metal wiring is formed. The metallization 45 is formed through a patterning process. At this time, the diffusion preventing metal film 43 and the silicide forming metal film 42 formed on the interlayer insulating film 39 are also patterned at the same time.

The p-type source / drain junction 37 is formed by implanting ₄₉ BF ₂ ⁺ ions or ₁₁ B ⁺ ions. Alternatively, the p-type source / drain junction 37 may be formed by continuously implanting ₄₉ BF ₂ ⁺ ions and ₁₁ B ⁺ ions. It may be.

8A to 8D, the p-type source / drain junction 37 is formed by a mixed ion implantation method of ₄₉ BF ₂ ⁺ ions, ₁₁ B ⁺ ions, ₄₉ BF ₂ ⁺ ions, and ₁₁ B ⁺ ions. However, as in the second embodiment (FIG. 5) and the fourth embodiment (FIG. 7), the p-type source / drain junction 37 may be formed by ion implantation of boron ions extracted from the decaborene molecule.

And, as in the third embodiment (FIG. 6) and the fourth embodiment (FIG. 7), activation of the dopant implanted into the plug ion implantation region may be performed during the heat treatment process to form a subsequent silicide film. In this case, since the p-type source / drain junction and the plug ion implantation region are formed by ion implanting boron ions extracted from the decaborene molecule (see FIG. 5), the ion implantation method having the lowest fluorine content is more effective than other embodiments. Low contact resistance can be obtained.

9 is a contact resistance distribution diagram according to the application of different ion implantation method. In FIG. 9, the abscissa represents contact resistance [㏀ / contact], the ordinate represents cumulative probability [%], and the curve p6 is the result of plug ion injection through a mixed injection method of ₄₉ BF ₂ ⁺ / ₁₁ B ⁺ , p7 is the result of plug ion implantation through ₄₉ BF ₂ ⁺ ion implantation method, and p8 is the result of plug ion implantation through B ₁₀ H ₁₄ ion implantation method.

As shown in FIG. 9, the contact resistance of ₄₉ BF ₂ ⁺ / ₁₁ B ⁺ was lower than that of ₄₉ BF ₂ ⁺ ion implantation, and the B ₁₀ H ₁₄ ion implantation was used. It can be seen that the contact resistance is significantly lower than the above two ion implantation methods.

In the above-described embodiments, the metal wiring connected to the source / drain junction without the contact plug is exemplified. However, the present invention is also applicable to the case of forming the metal wiring with the contact plug.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

According to the present invention, a plug ion implantation region having a very low fluorine ion content can be formed to satisfy the contact resistance required in a highly integrated device of 100 nm or less in which the contact hole area is extremely small, thereby ensuring the yield of highly integrated devices. There is.

In addition, since the decaborene molecular ion can be used 11 times higher than the conventional boron ion implantation, a higher beam current can be extracted, and boron implanted at an ion implantation rate of 1/10 of the boron ion implantation. Since the ionized water can be the same, the productivity of the plug ion implantation process can be greatly improved by 10 times or more.

And, it is possible to implement a high-performance devices at a low cost compared to the low energy boron ion implantation a line that requires amorphization ion implantation and a combined boron ion implantation and the ₄₉ BF twist legislation ₂ ⁺ ₁₁ B of the low-energy.

In addition, since only the ion generator of the conventional ion implanter can be modified and used, the plug ion implantation can be efficiently performed without developing a new ion implanter, thereby reducing the investment cost.

In addition, the pre-crystallization ion implantation method and the low energy boron ion implantation method facilitate the contamination of the ion source region of the ion implanter, so that the replacement and maintenance cycle of the ion source is short, but the present invention provides a relatively long maintenance cycle of the ion source. Therefore, there is an effect that can minimize the emission of environmental pollutants generated during the maintenance of the ion source.

Claims (11)

forming an insulating film on the semiconductor substrate on which the p-type source / drain is formed; Forming a contact hole in the insulating film to expose a portion of the p-type source / drain; Forming a plug ion implantation region by ion implanting boron ions extracted from the decarborene molecule on the semiconductor substrate exposed to the bottom of the contact hole; And Filling the contact hole with a conductive film Method of manufacturing a PMOS transistor comprising a. The method of claim 1, Forming the plug ion implantation region, Decaborene (B₁₀H₁₄Boron extracted from Ion implantation, with ion implantation energy of 5keV ~ 40keV, ion implantation of 1.0E14ions / cm²-1.0E15ions / cm²A method of manufacturing a PMOS transistor characterized in that the ion implantation. The method of claim 1, The p-type source / drain, _A method of manufacturing a PMOS transistor, characterized in that it is formed by ion implantation of ₄₉ BF ₂ ⁺ ions, ₁₁ B ⁺ ions, or a mixed ion of ₄₉ BF ₂ ⁺ ions and ₁₁ B ⁺ ions. The method of claim 1, The p-type source / drain, A method of manufacturing a PMOS transistor, characterized in that the boron ions extracted from the decarborene molecule are formed by ion implantation. The method of claim 1, Filling the contact hole with the conductive film, Sequentially forming a silicide forming metal film and a diffusion preventing metal film in the contact hole; Forming a silicide film to be bonded to the plug ion implantation region through heat treatment and activating a dopant implanted in the plug ion implantation region; And Filling the contact hole with a metal film Method of manufacturing a PMOS transistor comprising a. The method of claim 5, And the silicide film is formed by heat treatment at a temperature of 650 ° C to 900 ° C. The method of claim 1, Filling the contact hole with the conductive film, Heat treatment step for activating the boron ions implanted in the plug ion implantation region Sequentially forming a silicide forming metal film and a diffusion preventing metal film in the contact hole; Forming a silicide film bonded to the plug ion implantation region through a heat treatment; And Filling the contact hole with a metal film Method of manufacturing a PMOS transistor comprising a. The method of claim 7, wherein The heat treatment step for activating, A method of manufacturing a PMOS transistor, comprising rapid thermal treatment (RTP) or spike rapid thermal treatment (Spike-RTP). The method of claim 8, The rapid heat treatment is performed in the range of 750 ° C to 1050 ° C. The method of claim 8, The spike rapid thermal treatment proceeds in the range of 850 ° C to 1100 ° C. The method of claim 7, wherein The heat treatment for forming the silicide film is performed at a temperature of 650 ° C to 900 ° C.