KR20050009466A - Stress-reduced polymetal gate electrode and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A stress-reduced polymetal gate electrode and a fabricating method thereof are provided to improve a refresh characteristic and reliability by implanting ions into a low resistant metal to adjust a thermal expansion coefficient thereof. CONSTITUTION: A gate insulating layer(302) is formed on a semiconductor substrate(301). A gate stack(300) is formed on the gate insulating layer. The gate stack includes a polysilicon layer(303) as a bottom layer, a hardmask insulating layer(307) as a top layer, and a metal layer(305) formed therebetween. The metal layer has a minimum thermal expansion coefficient difference in comparison with the hardmask insulating layer and the polysilicon layer. An ion implantation buffer layer(306) is formed on the metal layer to perform a buffering function in an impurity implantation process.

Description

Stress-reduced polymetal gate electrode and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polymetal gate electrode and a method of manufacturing the same. More particularly, the present invention relates to a gate electrode structure and a method of manufacturing the same. will be.

As is well known, the gate electrode of the MOSFET has been formed using poly-silicon (Poly-Si) in the manufacturing process of semiconductor devices such as DRAM, but the doped polysilicon alone is high due to the miniaturization of the gate line width due to high integration. The resistivity characteristic makes it difficult to apply to devices requiring fast operation.

This is a serious problem due to the high integration of semiconductor devices, and to improve this problem, for example, WSi _x / Poly-Si and a high melting point metal silicide film such as tungsten silicide (WSi _x ) and titanium silicide, Gate electrode technology of the same polycide structure has emerged. However, the gate electrode of the polyside structure also has a limitation in improving the operation speed of the ultra-high density semiconductor device because the sheet resistance rapidly increases at the gate line width of 90nm or less.

Recently, as a technology using a high melting point metal such as tungsten (W) as a gate electrode, a polymetal gate electrode structure such as a W / WN _x / Poly-Si structure is used. The W / WN _x / Poly-Si gate electrode structure has the advantage of having a resistance as low as 1/5 compared to the WSi _x / Poly-Si gate electrode structure. In the W / WN _x / Poly-Si gate electrode structure, the tungsten nitride film WN _x is a diffusion barrier formed between the upper layer tungsten (W) and the lower layer polysilicon (Poly-Si).

On the other hand, the W / WN _x / Poly-Si gate electrode structure has the advantage of low resistivity, but the mechanical stress caused by the hard mask nitride film deposited on the tungsten (W) is severely adversely affected the device. There is a problem affecting.

The above-described prior art and its problems will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views for manufacturing a W / WN _x / Poly-Si gate electrode as a method of manufacturing a polymetal gate electrode according to the prior art.

Referring to FIG. 1A, a gate oxide layer 102, a gate polysilicon layer 103, a diffusion barrier tungsten nitride layer (WN _x ) 104, and a gate tungsten layer 105 are formed on a silicon substrate 101. Laminate in order.

Subsequently, referring to FIG. 1B, a hard mask nitride layer 106 is formed on the tungsten layer 105.

Here, the reason why the hard mask nitride layer 106 is used is that the self-aligned contact (SAC) process, which is an essential manufacturing process of the DRAM device, is possible, and recently, the gate line width is smaller than 100 nm. As the gap between gate lines adjacent to each other is also narrowed, a loading effect occurs during the self-aligned contact etching, and thus a very thick hard mask nitride layer is required to increase the process margin.

Subsequently, the photoresist pattern 107 for gate patterning is formed as shown in FIG. 1C, and the mask insulating layer 106, the tungsten layer 105, and tungsten nitride are formed using the photoresist pattern 107 as an etching barrier as shown in FIG. 1D. The layer (WN _x ) 104 and the polysilicon layer 103 are etched to form the gate stack 100.

Thereafter, a gate reoxidation process is performed, and a typical series of transistor manufacturing processes such as LDD ion implantation, gate sidewall spacer formation, and source / drain ion implantation processes are performed to complete MOSFET fabrication.

2A to 2C illustrate problems of the prior art, in which the silicide layer WSix acts as a buffer in the gate stack of HM NIT / WSi _x / Poly-Si, which is a polyside structure, and HM NIT is a hard mask nitride layer. While mechanical stress caused by hard mask nitride does not significantly affect the device (see Fig. 2a), in the gate stack of HM NIT / W / WN _x / Poly-Si, the hard mask with tungsten (W) is the upper and lower layers. Since the coefficient of thermal expansion is more than twice as large as that of the nitride layer (HM NIT) and the polysilicon layer (Poly-Si), the stress of each of the thin films and the stress due to the difference in thermal expansion during the subsequent thermal process are greatly induced (see FIG. 2B). In addition, stress induced leakage current (SILC) rapidly deteriorates with the maximum temperature of the subsequent thermal process in the gate stack of HM NIT / W / WN _x / Poly-Si (see FIG. 2C), which is a gate by the subsequent thermal process. The stress induced in the stack directly adversely affects the lower gate oxide layer, which means that the refresh characteristics and the reliability of the device are degraded.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a polymetal gate electrode and a method of manufacturing the same, by controlling a thermal expansion coefficient of the metal for gate electrode to reduce mechanical stress generated in a subsequent thermal process. have.

1A through 1D are cross-sectional views of a method of manufacturing a polymetal gate electrode according to the related art, and a process for manufacturing a W / WN _x / Poly-Si gate electrode;

2a to 2c are experimental data showing the problems of the prior art,

3 is a cross-sectional view showing a structure of a polymetal gate electrode according to a preferred embodiment of the present invention;

4A-4G are process cross-sectional views illustrating a method for manufacturing the structure of FIG. 3.

※ Explanation of code for main part of drawing

401 silicon substrate 402 gate oxide film

403: polysilicon layer 404: diffusion barrier tungsten nitride film

405: Tungsten layer having a thermal expansion coefficient controlled by implanting impurities

406: ion implantation buffer layer 407: impurity ion implantation

408 hard mask nitride film 409 Regrown oxide film

400: gate stack

Polymetal gate electrode of the present invention for achieving the above object is a gate insulating layer formed on a semiconductor substrate; And a gate stack patterned on the gate insulating layer, wherein the gate stack includes a lower polysilicon layer, an upper layer hard mask insulating layer, and a metal layer interposed therebetween, wherein the metal layer is the hard mask insulating layer. And each of the polysilicon layers is impurity implanted to have a minimum difference in coefficient of thermal expansion.

In the present invention, the gate stack may further include an ion implantation buffer layer formed on the metal layer to function as a buffer when the impurity is implanted, and the ion implantation buffer layer is SiO ₂ , Si _x N ₄ , Al ₂ O ₃ It can be applied to any one layer selected from, or metal silicide, it is preferable to have a thickness of 10 ~ 1000Å in order to control the depth implanted into the metal layer.

In the present invention, the impurities are at least any one selected from the group of Ne, Ar, kr, Xe, P, B, F, Ti, Hf, Zr, Al, Cr, V, Ni, Co, Ta, C, Si and Ge. It may include one. In addition, the metal layer may use any one selected from the group of W, Mo, Ta, Ti, Ru, Ir, and Pt, and further include a diffusion barrier layer interposed between the polysilicon layer and the metal layer. The diffusion barrier layer may be any one selected from the group consisting of WN _x , SiN _x , TiAl _x N _y , HfN _x , ZrN _x , TaN _x , TiN _x , AlN _x , TaSi _x N _y , TiAl _x N _y It may include.

In addition, the polymetal gate electrode manufacturing method of the present invention, forming a gate insulating layer on a semiconductor substrate; Stacking a polysilicon layer and a metal layer on the gate insulating layer; Performing impurity ion implantation on the metal layer to control a thermal expansion coefficient of the metal layer: forming a hard mask insulating layer on the metal layer; And patterning the hard mask insulating layer, the metal layer, and the polysilicon layer by a gate electrode mask and an etching process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain in detail enough that a person having ordinary skill in the art to which the present invention pertains can easily carry out the technical idea of the present invention, the most preferred embodiments of the present invention and the effects thereof are referred to the accompanying drawings. This will be described.

3 is a cross-sectional view illustrating a polymetal gate electrode structure according to a preferred embodiment of the present invention, and FIGS. 4A to 4G are cross-sectional views illustrating a method for manufacturing the structure of FIG. 3.

Referring to FIG. 3, a gate oxide film 302 is formed on a silicon substrate 301, and a gate stack 300 is patterned on the gate oxide layer 102.

The gate stack 300 includes a polysilicon layer 302, a hard mask nitride layer 307, and a tungsten layer 305 interposed therebetween, wherein the tungsten layer 305 is formed of the hard mask nitride layer layer 307. Impurities are implanted into each of the polysilicon layers 303 to have a minimum difference in coefficient of thermal expansion.

Impurities implanted in the tungsten layer 305 serve to change the crystal structure of tungsten, form segregatin and solid solution in the grains of tungsten to change the coefficient of thermal expansion or form a stable structure.

Tungsten layer 305 implanted impurities are selected from the group of Ne, Ar, kr, Xe, P, B, F, Ti, Hf, Zr, Al, Cr, V, Ni, Co, Ta, C, Si and Ge At least one can be used.

The gate stack 300 further includes an ion implantation buffer layer 306 formed on the tungsten layer 305 to provide a buffer function when the impurities are implanted. The ion implantation buffer layer 306 may be formed of SiO ₂ , Si, or the like. Any one layer selected from _x N ₄ , Al ₂ O ₃ , or metal silicide may be used, and the thickness thereof may have a thickness of 10 to 1000 kPa to control the depth of ion implantation into the tungsten layer 305.

A tungsten nitride film (WN _x ) 304 is formed between the polysilicon layer 303 and the tungsten layer 305 as a diffusion barrier layer. The diffusion barrier tungsten nitride film 304 is formed of SiN _x , TiAl _x N _y , HfN _It can be replaced with any one selected from the group of _x , ZrN _x , TaN _x , TiN _x , AlN _x , TaSi _x N _y , TiAl _x N _y .

The ion implantation buffer layer 306 and the diffusion barrier tungsten nitride layer 304 may be omitted in the present invention.

The tungsten layer 305 may be replaced with any one selected from the group of Mo, Ta, Ti, Ru, Ir, and Pt.

A method for manufacturing the structure of FIG. 3 will be described with reference to FIGS. 4A-4G.

Referring to FIG. 4A, a gate oxide film 402 and a polysilicon layer 403 are stacked on a silicon substrate 401.

Here, the gate oxide layer 402 may use an insulating film containing nitrogen, such as an oxynitride instead of SiO ₂ , and may include Hf, Zr, Al, Ta, Ti, Ce, Pr, and La. It is also possible to use high-k insulating materials such as metal oxides. In addition, poly-Si _1-x Ge _x (x = 0.01 to 0.99) may be used instead of the polysilicon layer 403.

4B, a tungsten nitride layer (WN _x ) 404 and a tungsten layer 405, which are diffusion barriers, are stacked. The diffusion barrier layer can be omitted. In the present embodiment, the tungsten layer 405 is used as the metal, but other metals such as Mo, Ta, Ti, Ru, Ir, and Pt may be used, and the diffusion barrier may be SiN _x , TiAl in addition to the tungsten nitride film (WN _x ). _{It is possible to use x} N _y , HfN _x , ZrN _x , TaN _x , TiN _x , AlN _x , TaSi _x N _y , TiAl _x N _y , and the like. The tungsten layer 405 can be deposited by the PVD method or the CVD method, and the deposition thickness thereof can be about 50 to 1000 mW.

Next, referring to FIG. 4C, an ion implantation layer 406 is formed on the tungsten layer 405, and impurity ion implantation 407 is applied to the tungsten layer 405 as shown in FIG. 4D. As described above, the impurities injected into the tungsten layer 405 are Ne, Ar, kr, Xe, P, B, F, Ti, Hf, Zr, Al, Cr, V, Ni, Co, Ta, C, Si, and At least one selected from the group of Ge may be used, and the ion implantation buffer layer 406 may use any one selected from SiO ₂ , Si _x N ₄ , Al ₂ O ₃ , or metal silicide, and the thickness may be In order to control the depth of ion implantation into the tungsten layer 405 may have a thickness of 10 ~ 1000Å.

Next, referring to FIG. 4E, the hard mask nitride layer 408 is formed on the ion implantation buffer layer 406, and the gate stack 400 is patterned by a gate mask and an etching process as shown in FIG. 4F.

4G shows a state in which the oxide film 409 is regrown in the gate oxide film 402 and the polysilicon layer 403 by performing gate reoxidation. In order to oxidize the silicon substrate 401 and the polysilicon layer 403 while suppressing abnormal oxidation of the tungsten layer 405 during reoxidation, plasma oxidation using RF or a microwave wave is performed. It is preferable to use a gas such as Ar, Kr, etc. in forming plasma, form RF and microwave below 15 GHz, and apply gas such as H ₂ , D ₂ , O ₂ at a temperature of 450 ° C. or lower. Can be. Also applicable is a selective oxidation process which oxidizes in an H ₂ -rich / O ₂ atmosphere.

After that, a series of conventional processes for transistor manufacturing, such as LDD ion implantation, gate sidewall spacer formation, and source / drain ion implantation processes, are performed to complete MOSFET fabrication.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

By implanting impurities into the low-resistance metal used as the gate electrode as in the present invention, it is possible to change the metal structure or the coefficient of thermal expansion. That is, since the thermal expansion coefficient is substantially the same as that of the upper and lower materials, the mechanical stress caused by the gate stack can be minimized in subsequent thermal processes, thereby improving the refresh characteristics and reliability of the device. A metal gate electrode is provided.

Claims (13)

A gate insulating layer formed on the semiconductor substrate, and a gate stack patterned on the gate insulating layer; The gate stack includes a lower polysilicon layer and an upper layer hard mask insulating layer and a metal layer interposed therebetween, The metal layer is characterized in that the impurity is implanted to have a minimum thermal expansion coefficient difference for each of the hard mask insulating layer and the polysilicon layer Stress relief polymetal gate electrodes. The method of claim 1, And the gate stack further comprises an ion implantation buffer layer formed on the metal layer to provide a buffer function when implanting the impurities. The method according to claim 1 or 2, The impurity comprises at least one selected from the group of Ne, Ar, kr, Xe, P, B, F, Ti, Hf, Zr, Al, Cr, V, Ni, Co, Ta, C, Si and Ge A stress relief polymetal gate electrode, characterized in that. The method according to claim 1 or 2, The metal layer is a stress relief polymetal gate electrode, characterized in that any one selected from the group of W, Mo, Ta, Ti, Ru, Ir and Pt. The method according to claim 1 or 2, Further comprising a diffusion barrier layer interposed between the polysilicon layer and the metal layer, the diffusion barrier layer is WN _x , SiN _x , TiAl _x N _y , HfN _x , ZrN _x , TaN _x , TiN _x , AlN _x And TaSi _x N _y , TiAl _x N _y selected from the group of stress-relieved polymetal gate electrode. The method of claim 2, The ion implantation buffer layer is any one selected from SiO ₂ , Si _x N ₄ , Al ₂ O ₃ , or metal silicide, and has a thickness of 10 to 1000 kPa to control the depth of ion implantation into the metal layer. A polymetal gate electrode with reduced stress. Forming a gate insulating layer on the semiconductor substrate; Stacking a polysilicon layer and a metal layer on the gate insulating layer; Performing impurity ion implantation on the metal layer to control the thermal expansion coefficient; Forming a hard mask insulating layer on the metal layer; And Patterning the hard mask insulating layer, the metal layer, and the polysilicon layer by a gate electrode mask and an etching process Stress relief polymetal gate electrode manufacturing method comprising a. The method of claim 7, wherein The method of claim 1, further comprising forming an ion implantation buffer layer on the metal layer during the ion implantation. The method according to claim 7 or 8, The impurity includes at least one selected from the group of Ne, Ar, kr, Xe, P, B, F, Ti, Hf, Zr, Al, Cr, V, Ni, Co, Ta, C, Si, and Ge. A method for producing a stress relief polymetal gate electrode, characterized in that. The method according to claim 7 or 8, The metal layer is a stress relief polymetal gate electrode manufacturing method, characterized in that any one selected from the group of W, Mo, Ta, Ti, Ru, Ir and Pt. The method according to claim 7 or 8, Further comprising a diffusion barrier layer interposed between the polysilicon layer and the metal layer, the diffusion barrier layer is WN _x , SiN _x , TiAl _x N _y , HfN _x , ZrN _x , TaN _x , TiN _x , AlN _x And TaSi _x N _y , TiAl _x N _y , any one selected from the group consisting of stress relief polymetal gate electrode. The method of claim 8, The ion implantation buffer layer is any one selected from SiO ₂ , Si _x N ₄ , Al ₂ O ₃ , or metal silicide, and formed to have a thickness of 10 to 1000 kPa to control the depth of ion implantation into the metal layer. A stress-relieved polymetal gate electrode manufacturing method characterized by the above-mentioned. The method according to claim 7 or 8, The ion implantation is a stress relief polymetal gate electrode manufacturing method characterized in that the ion implantation energy of 1KeV to 1MeV and a dose of 5E ¹³ / cm 2 to 1E ¹⁶ / cm 2.